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review.blissroms.org / platform_art / 6c7d244058b74cdd61533968dd6cddd7003d2671 / . / src / compiler / Dataflow.cc
blob: 3f88ea5cbd361e4012f647a0fbf32c3a6a964c55 [file] [log] [blame]
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "Dataflow.h"
19//#include "libdex/DexOpcodes.h"
20
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]21namespace art {
22
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]23/*
24 * Main table containing data flow attributes for each bytecode. The
25 * first kNumPackedOpcodes entries are for Dalvik bytecode
26 * instructions, where extended opcode at the MIR level are appended
27 * afterwards.
28 *
29 * TODO - many optimization flags are incomplete - they will only limit the
30 * scope of optimizations but will not cause mis-optimizations.
31 */
32int oatDataFlowAttributes[kMirOpLast] = {
33 // 00 OP_NOP
34 DF_NOP,
35
36 // 01 OP_MOVE vA, vB
37 DF_DA | DF_UB | DF_IS_MOVE,
38
39 // 02 OP_MOVE_FROM16 vAA, vBBBB
40 DF_DA | DF_UB | DF_IS_MOVE,
41
42 // 03 OP_MOVE_16 vAAAA, vBBBB
43 DF_DA | DF_UB | DF_IS_MOVE,
44
45 // 04 OP_MOVE_WIDE vA, vB
46 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
47
48 // 05 OP_MOVE_WIDE_FROM16 vAA, vBBBB
49 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
50
51 // 06 OP_MOVE_WIDE_16 vAAAA, vBBBB
52 DF_DA_WIDE | DF_UB_WIDE | DF_IS_MOVE,
53
54 // 07 OP_MOVE_OBJECT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]55 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]56
57 // 08 OP_MOVE_OBJECT_FROM16 vAA, vBBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]58 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]59
60 // 09 OP_MOVE_OBJECT_16 vAAAA, vBBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]61 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]62
63 // 0A OP_MOVE_RESULT vAA
64 DF_DA,
65
66 // 0B OP_MOVE_RESULT_WIDE vAA
67 DF_DA_WIDE,
68
69 // 0C OP_MOVE_RESULT_OBJECT vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]70 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]71
72 // 0D OP_MOVE_EXCEPTION vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]73 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]74
75 // 0E OP_RETURN_VOID
76 DF_NOP,
77
78 // 0F OP_RETURN vAA
79 DF_UA,
80
81 // 10 OP_RETURN_WIDE vAA
82 DF_UA_WIDE,
83
84 // 11 OP_RETURN_OBJECT vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]85 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]86
87 // 12 OP_CONST_4 vA, #+B
88 DF_DA | DF_SETS_CONST,
89
90 // 13 OP_CONST_16 vAA, #+BBBB
91 DF_DA | DF_SETS_CONST,
92
93 // 14 OP_CONST vAA, #+BBBBBBBB
94 DF_DA | DF_SETS_CONST,
95
96 // 15 OP_CONST_HIGH16 VAA, #+BBBB0000
97 DF_DA | DF_SETS_CONST,
98
99 // 16 OP_CONST_WIDE_16 vAA, #+BBBB
100 DF_DA_WIDE | DF_SETS_CONST,
101
102 // 17 OP_CONST_WIDE_32 vAA, #+BBBBBBBB
103 DF_DA_WIDE | DF_SETS_CONST,
104
105 // 18 OP_CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
106 DF_DA_WIDE | DF_SETS_CONST,
107
108 // 19 OP_CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
109 DF_DA_WIDE | DF_SETS_CONST,
110
111 // 1A OP_CONST_STRING vAA, string@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]112 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]113
114 // 1B OP_CONST_STRING_JUMBO vAA, string@BBBBBBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]115 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]116
117 // 1C OP_CONST_CLASS vAA, type@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]118 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]119
120 // 1D OP_MONITOR_ENTER vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]121 DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]122
123 // 1E OP_MONITOR_EXIT vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]124 DF_UA | DF_NULL_CHK_0 | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]125
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]126 // 1F OP_CHK_CAST vAA, type@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]127 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]128
129 // 20 OP_INSTANCE_OF vA, vB, type@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]130 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]131
132 // 21 OP_ARRAY_LENGTH vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]133 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]134
135 // 22 OP_NEW_INSTANCE vAA, type@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]136 DF_DA | DF_NON_NULL_DST | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]137
138 // 23 OP_NEW_ARRAY vA, vB, type@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]139 DF_DA | DF_UB | DF_NON_NULL_DST | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]140
141 // 24 OP_FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]142 DF_FORMAT_35C | DF_NON_NULL_RET,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]143
144 // 25 OP_FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]145 DF_FORMAT_3RC | DF_NON_NULL_RET,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]146
147 // 26 OP_FILL_ARRAY_DATA vAA, +BBBBBBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]148 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]149
150 // 27 OP_THROW vAA
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]151 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]152
153 // 28 OP_GOTO
154 DF_NOP,
155
156 // 29 OP_GOTO_16
157 DF_NOP,
158
159 // 2A OP_GOTO_32
160 DF_NOP,
161
162 // 2B OP_PACKED_SWITCH vAA, +BBBBBBBB
163 DF_UA,
164
165 // 2C OP_SPARSE_SWITCH vAA, +BBBBBBBB
166 DF_UA,
167
168 // 2D OP_CMPL_FLOAT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]169 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]170
171 // 2E OP_CMPG_FLOAT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]172 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]173
174 // 2F OP_CMPL_DOUBLE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]175 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]176
177 // 30 OP_CMPG_DOUBLE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]178 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]179
180 // 31 OP_CMP_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]181 DF_DA | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]182
183 // 32 OP_IF_EQ vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]184 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]185
186 // 33 OP_IF_NE vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]187 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]188
189 // 34 OP_IF_LT vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]190 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]191
192 // 35 OP_IF_GE vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]193 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]194
195 // 36 OP_IF_GT vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]196 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]197
198 // 37 OP_IF_LE vA, vB, +CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]199 DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]200
201
202 // 38 OP_IF_EQZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]203 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]204
205 // 39 OP_IF_NEZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]206 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]207
208 // 3A OP_IF_LTZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]209 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]210
211 // 3B OP_IF_GEZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]212 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]213
214 // 3C OP_IF_GTZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]215 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]216
217 // 3D OP_IF_LEZ vAA, +BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]218 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]219
220 // 3E OP_UNUSED_3E
221 DF_NOP,
222
223 // 3F OP_UNUSED_3F
224 DF_NOP,
225
226 // 40 OP_UNUSED_40
227 DF_NOP,
228
229 // 41 OP_UNUSED_41
230 DF_NOP,
231
232 // 42 OP_UNUSED_42
233 DF_NOP,
234
235 // 43 OP_UNUSED_43
236 DF_NOP,
237
238 // 44 OP_AGET vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]239 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]240
241 // 45 OP_AGET_WIDE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]242 DF_DA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]243
244 // 46 OP_AGET_OBJECT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]245 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]246
247 // 47 OP_AGET_BOOLEAN vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]248 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]249
250 // 48 OP_AGET_BYTE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]251 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]252
253 // 49 OP_AGET_CHAR vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]254 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]255
256 // 4A OP_AGET_SHORT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]257 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_IS_GETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]258
259 // 4B OP_APUT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]260 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]261
262 // 4C OP_APUT_WIDE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]263 DF_UA_WIDE | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]264
265 // 4D OP_APUT_OBJECT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]266 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]267
268 // 4E OP_APUT_BOOLEAN vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]269 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]270
271 // 4F OP_APUT_BYTE vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]272 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]273
274 // 50 OP_APUT_CHAR vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]275 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]276
277 // 51 OP_APUT_SHORT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]278 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_IS_SETTER | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]279
280 // 52 OP_IGET vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]281 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]282
283 // 53 OP_IGET_WIDE vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]284 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]285
286 // 54 OP_IGET_OBJECT vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]287 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]288
289 // 55 OP_IGET_BOOLEAN vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]290 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]291
292 // 56 OP_IGET_BYTE vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]293 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]294
295 // 57 OP_IGET_CHAR vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]296 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]297
298 // 58 OP_IGET_SHORT vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]299 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]300
301 // 59 OP_IPUT vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]302 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]303
304 // 5A OP_IPUT_WIDE vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]305 DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]306
307 // 5B OP_IPUT_OBJECT vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]308 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]309
310 // 5C OP_IPUT_BOOLEAN vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]311 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]312
313 // 5D OP_IPUT_BYTE vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]314 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]315
316 // 5E OP_IPUT_CHAR vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]317 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]318
319 // 5F OP_IPUT_SHORT vA, vB, field@CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]320 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]321
322 // 60 OP_SGET vAA, field@BBBB
323 DF_DA | DF_IS_GETTER,
324
325 // 61 OP_SGET_WIDE vAA, field@BBBB
326 DF_DA_WIDE | DF_IS_GETTER,
327
328 // 62 OP_SGET_OBJECT vAA, field@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]329 DF_DA | DF_IS_GETTER | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]330
331 // 63 OP_SGET_BOOLEAN vAA, field@BBBB
332 DF_DA | DF_IS_GETTER,
333
334 // 64 OP_SGET_BYTE vAA, field@BBBB
335 DF_DA | DF_IS_GETTER,
336
337 // 65 OP_SGET_CHAR vAA, field@BBBB
338 DF_DA | DF_IS_GETTER,
339
340 // 66 OP_SGET_SHORT vAA, field@BBBB
341 DF_DA | DF_IS_GETTER,
342
343 // 67 OP_SPUT vAA, field@BBBB
344 DF_UA | DF_IS_SETTER,
345
346 // 68 OP_SPUT_WIDE vAA, field@BBBB
347 DF_UA_WIDE | DF_IS_SETTER,
348
349 // 69 OP_SPUT_OBJECT vAA, field@BBBB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]350 DF_UA | DF_IS_SETTER | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]351
352 // 6A OP_SPUT_BOOLEAN vAA, field@BBBB
353 DF_UA | DF_IS_SETTER,
354
355 // 6B OP_SPUT_BYTE vAA, field@BBBB
356 DF_UA | DF_IS_SETTER,
357
358 // 6C OP_SPUT_CHAR vAA, field@BBBB
359 DF_UA | DF_IS_SETTER,
360
361 // 6D OP_SPUT_SHORT vAA, field@BBBB
362 DF_UA | DF_IS_SETTER,
363
364 // 6E OP_INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]365 DF_FORMAT_35C | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]366
367 // 6F OP_INVOKE_SUPER {vD, vE, vF, vG, vA}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]368 DF_FORMAT_35C | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]369
370 // 70 OP_INVOKE_DIRECT {vD, vE, vF, vG, vA}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]371 DF_FORMAT_35C | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]372
373 // 71 OP_INVOKE_STATIC {vD, vE, vF, vG, vA}
374 DF_FORMAT_35C,
375
376 // 72 OP_INVOKE_INTERFACE {vD, vE, vF, vG, vA}
377 DF_FORMAT_35C,
378
379 // 73 OP_UNUSED_73
380 DF_NOP,
381
382 // 74 OP_INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]383 DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]384
385 // 75 OP_INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]386 DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]387
388 // 76 OP_INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]389 DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]390
391 // 77 OP_INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
392 DF_FORMAT_3RC,
393
394 // 78 OP_INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
395 DF_FORMAT_3RC,
396
397 // 79 OP_UNUSED_79
398 DF_NOP,
399
400 // 7A OP_UNUSED_7A
401 DF_NOP,
402
403 // 7B OP_NEG_INT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]404 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]405
406 // 7C OP_NOT_INT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]407 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]408
409 // 7D OP_NEG_LONG vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]410 DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]411
412 // 7E OP_NOT_LONG vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]413 DF_DA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]414
415 // 7F OP_NEG_FLOAT vA, vB
416 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
417
418 // 80 OP_NEG_DOUBLE vA, vB
419 DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
420
421 // 81 OP_INT_TO_LONG vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]422 DF_DA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]423
424 // 82 OP_INT_TO_FLOAT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]425 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]426
427 // 83 OP_INT_TO_DOUBLE vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]428 DF_DA_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]429
430 // 84 OP_LONG_TO_INT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]431 DF_DA | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]432
433 // 85 OP_LONG_TO_FLOAT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]434 DF_DA | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]435
436 // 86 OP_LONG_TO_DOUBLE vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]437 DF_DA_WIDE | DF_UB_WIDE | DF_FP_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]438
439 // 87 OP_FLOAT_TO_INT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]440 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]441
442 // 88 OP_FLOAT_TO_LONG vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]443 DF_DA_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]444
445 // 89 OP_FLOAT_TO_DOUBLE vA, vB
446 DF_DA_WIDE | DF_UB | DF_FP_A | DF_FP_B,
447
448 // 8A OP_DOUBLE_TO_INT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]449 DF_DA | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]450
451 // 8B OP_DOUBLE_TO_LONG vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]452 DF_DA_WIDE | DF_UB_WIDE | DF_FP_B | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]453
454 // 8C OP_DOUBLE_TO_FLOAT vA, vB
455 DF_DA | DF_UB_WIDE | DF_FP_A | DF_FP_B,
456
457 // 8D OP_INT_TO_BYTE vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]458 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]459
460 // 8E OP_INT_TO_CHAR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]461 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]462
463 // 8F OP_INT_TO_SHORT vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]464 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]465
466 // 90 OP_ADD_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]467 DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]468
469 // 91 OP_SUB_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]470 DF_DA | DF_UB | DF_UC | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]471
472 // 92 OP_MUL_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]473 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]474
475 // 93 OP_DIV_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]476 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]477
478 // 94 OP_REM_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]479 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]480
481 // 95 OP_AND_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]482 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]483
484 // 96 OP_OR_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]485 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]486
487 // 97 OP_XOR_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]488 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]489
490 // 98 OP_SHL_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]491 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]492
493 // 99 OP_SHR_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]494 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]495
496 // 9A OP_USHR_INT vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]497 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]498
499 // 9B OP_ADD_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]500 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]501
502 // 9C OP_SUB_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]503 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]504
505 // 9D OP_MUL_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]506 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]507
508 // 9E OP_DIV_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]509 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]510
511 // 9F OP_REM_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]512 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]513
514 // A0 OP_AND_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]515 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]516
517 // A1 OP_OR_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]518 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]519
520 // A2 OP_XOR_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]521 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]522
523 // A3 OP_SHL_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]524 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]525
526 // A4 OP_SHR_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]527 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]528
529 // A5 OP_USHR_LONG vAA, vBB, vCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]530 DF_DA_WIDE | DF_UB_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]531
532 // A6 OP_ADD_FLOAT vAA, vBB, vCC
533 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
534
535 // A7 OP_SUB_FLOAT vAA, vBB, vCC
536 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
537
538 // A8 OP_MUL_FLOAT vAA, vBB, vCC
539 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
540
541 // A9 OP_DIV_FLOAT vAA, vBB, vCC
542 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
543
544 // AA OP_REM_FLOAT vAA, vBB, vCC
545 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
546
547 // AB OP_ADD_DOUBLE vAA, vBB, vCC
548 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
549
550 // AC OP_SUB_DOUBLE vAA, vBB, vCC
551 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
552
553 // AD OP_MUL_DOUBLE vAA, vBB, vCC
554 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
555
556 // AE OP_DIV_DOUBLE vAA, vBB, vCC
557 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
558
559 // AF OP_REM_DOUBLE vAA, vBB, vCC
560 DF_DA_WIDE | DF_UB_WIDE | DF_UC_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
561
562 // B0 OP_ADD_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]563 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]564
565 // B1 OP_SUB_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]566 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]567
568 // B2 OP_MUL_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]569 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]570
571 // B3 OP_DIV_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]572 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]573
574 // B4 OP_REM_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]575 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]576
577 // B5 OP_AND_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]578 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]579
580 // B6 OP_OR_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]581 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]582
583 // B7 OP_XOR_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]584 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]585
586 // B8 OP_SHL_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]587 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]588
589 // B9 OP_SHR_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]590 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]591
592 // BA OP_USHR_INT_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]593 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]594
595 // BB OP_ADD_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]596 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]597
598 // BC OP_SUB_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]599 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]600
601 // BD OP_MUL_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]602 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]603
604 // BE OP_DIV_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]605 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]606
607 // BF OP_REM_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]608 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]609
610 // C0 OP_AND_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]611 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]612
613 // C1 OP_OR_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]614 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]615
616 // C2 OP_XOR_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]617 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]618
619 // C3 OP_SHL_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]620 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]621
622 // C4 OP_SHR_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]623 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]624
625 // C5 OP_USHR_LONG_2ADDR vA, vB
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]626 DF_DA_WIDE | DF_UA_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]627
628 // C6 OP_ADD_FLOAT_2ADDR vA, vB
629 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
630
631 // C7 OP_SUB_FLOAT_2ADDR vA, vB
632 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
633
634 // C8 OP_MUL_FLOAT_2ADDR vA, vB
635 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
636
637 // C9 OP_DIV_FLOAT_2ADDR vA, vB
638 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
639
640 // CA OP_REM_FLOAT_2ADDR vA, vB
641 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
642
643 // CB OP_ADD_DOUBLE_2ADDR vA, vB
644 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
645
646 // CC OP_SUB_DOUBLE_2ADDR vA, vB
647 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
648
649 // CD OP_MUL_DOUBLE_2ADDR vA, vB
650 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
651
652 // CE OP_DIV_DOUBLE_2ADDR vA, vB
653 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
654
655 // CF OP_REM_DOUBLE_2ADDR vA, vB
656 DF_DA_WIDE | DF_UA_WIDE | DF_UB_WIDE | DF_FP_A | DF_FP_B,
657
658 // D0 OP_ADD_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]659 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]660
661 // D1 OP_RSUB_INT vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]662 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]663
664 // D2 OP_MUL_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]665 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]666
667 // D3 OP_DIV_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]668 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]669
670 // D4 OP_REM_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]671 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]672
673 // D5 OP_AND_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]674 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]675
676 // D6 OP_OR_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]677 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]678
679 // D7 OP_XOR_INT_LIT16 vA, vB, #+CCCC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]680 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]681
682 // D8 OP_ADD_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]683 DF_DA | DF_UB | DF_IS_LINEAR | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]684
685 // D9 OP_RSUB_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]686 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]687
688 // DA OP_MUL_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]689 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]690
691 // DB OP_DIV_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]692 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]693
694 // DC OP_REM_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]695 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]696
697 // DD OP_AND_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]698 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]699
700 // DE OP_OR_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]701 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]702
703 // DF OP_XOR_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]704 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]705
706 // E0 OP_SHL_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]707 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]708
709 // E1 OP_SHR_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]710 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]711
712 // E2 OP_USHR_INT_LIT8 vAA, vBB, #+CC
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]713 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]714
715 // E3 OP_IGET_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]716 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]717
718 // E4 OP_IPUT_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]719 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]720
721 // E5 OP_SGET_VOLATILE
722 DF_DA,
723
724 // E6 OP_SPUT_VOLATILE
725 DF_UA,
726
727 // E7 OP_IGET_OBJECT_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]728 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]729
730 // E8 OP_IGET_WIDE_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]731 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]732
733 // E9 OP_IPUT_WIDE_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]734 DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]735
736 // EA OP_SGET_WIDE_VOLATILE
737 DF_DA_WIDE,
738
739 // EB OP_SPUT_WIDE_VOLATILE
740 DF_UA_WIDE,
741
742 // EC OP_BREAKPOINT
743 DF_NOP,
744
745 // ED OP_THROW_VERIFICATION_ERROR
746 DF_NOP,
747
748 // EE OP_EXECUTE_INLINE
749 DF_FORMAT_35C,
750
751 // EF OP_EXECUTE_INLINE_RANGE
752 DF_FORMAT_3RC,
753
754 // F0 OP_INVOKE_OBJECT_INIT_RANGE
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]755 DF_NOP | DF_NULL_CHK_0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]756
757 // F1 OP_RETURN_VOID_BARRIER
758 DF_NOP,
759
760 // F2 OP_IGET_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]761 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]762
763 // F3 OP_IGET_WIDE_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]764 DF_DA_WIDE | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]765
766 // F4 OP_IGET_OBJECT_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]767 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_IS_GETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]768
769 // F5 OP_IPUT_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]770 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]771
772 // F6 OP_IPUT_WIDE_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]773 DF_UA_WIDE | DF_UB | DF_NULL_CHK_1 |DF_IS_SETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]774
775 // F7 OP_IPUT_OBJECT_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]776 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_IS_SETTER,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]777
778 // F8 OP_INVOKE_VIRTUAL_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]779 DF_FORMAT_35C | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]780
781 // F9 OP_INVOKE_VIRTUAL_QUICK_RANGE
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]782 DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]783
784 // FA OP_INVOKE_SUPER_QUICK
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]785 DF_FORMAT_35C | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]786
787 // FB OP_INVOKE_SUPER_QUICK_RANGE
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]788 DF_FORMAT_3RC | DF_NULL_CHK_OUT0,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]789
790 // FC OP_IPUT_OBJECT_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]791 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_CORE_A | DF_CORE_B,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]792
793 // FD OP_SGET_OBJECT_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]794 DF_DA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]795
796 // FE OP_SPUT_OBJECT_VOLATILE
buzbee67bc2362011-10-11 18:08:40 -0700[diff] [blame]797 DF_UA | DF_CORE_A,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]798
Elliott Hughes8e5944b2012-01-05 13:44:44 -0800[diff] [blame]799 // FF OP_UNUSED_FF
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]800 DF_NOP,
801
802 // Beginning of extended MIR opcodes
Elliott Hughes8e5944b2012-01-05 13:44:44 -0800[diff] [blame]803 // 100 OP_MIR_PHI
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]804 DF_PHI | DF_DA | DF_NULL_TRANSFER_N,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]805 /*
806 * For extended MIR inserted at the MIR2LIR stage, it is okay to have
807 * undefined values here.
808 */
809};
810
811/* Return the Dalvik register/subscript pair of a given SSA register */
812int oatConvertSSARegToDalvik(const CompilationUnit* cUnit, int ssaReg)
813{
814 return GET_ELEM_N(cUnit->ssaToDalvikMap, int, ssaReg);
815}
816
817/*
818 * Utility function to convert encoded SSA register value into Dalvik register
819 * and subscript pair. Each SSA register can be used to index the
820 * ssaToDalvikMap list to get the subscript[31..16]/dalvik_reg[15..0] mapping.
821 */
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]822char* oatGetDalvikDisassembly(const DecodedInstruction* insn,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]823 const char* note)
824{
825 char buffer[256];
826 Opcode opcode = insn->opcode;
827 int dfAttributes = oatDataFlowAttributes[opcode];
828 int flags;
829 char* ret;
830
831 buffer[0] = 0;
832 if ((int)opcode >= (int)kMirOpFirst) {
833 if ((int)opcode == (int)kMirOpPhi) {
834 strcpy(buffer, "PHI");
835 }
836 else {
837 sprintf(buffer, "Opcode %#x", opcode);
838 }
839 flags = 0;
840 } else {
841 strcpy(buffer, dexGetOpcodeName(opcode));
842 flags = dexGetFlagsFromOpcode(insn->opcode);
843 }
844
845 if (note)
846 strcat(buffer, note);
847
848 /* For branches, decode the instructions to print out the branch targets */
849 if (flags & kInstrCanBranch) {
850 InstructionFormat dalvikFormat = dexGetFormatFromOpcode(insn->opcode);
851 int offset = 0;
852 switch (dalvikFormat) {
853 case kFmt21t:
854 snprintf(buffer + strlen(buffer), 256, " v%d,", insn->vA);
855 offset = (int) insn->vB;
856 break;
857 case kFmt22t:
858 snprintf(buffer + strlen(buffer), 256, " v%d, v%d,",
859 insn->vA, insn->vB);
860 offset = (int) insn->vC;
861 break;
862 case kFmt10t:
863 case kFmt20t:
864 case kFmt30t:
865 offset = (int) insn->vA;
866 break;
867 default:
868 LOG(FATAL) << "Unexpected branch format " << (int)dalvikFormat
869 << " / opcode " << (int)opcode;
870 }
871 snprintf(buffer + strlen(buffer), 256, " (%c%x)",
872 offset > 0 ? '+' : '-',
873 offset > 0 ? offset : -offset);
874 } else if (dfAttributes & DF_FORMAT_35C) {
875 unsigned int i;
876 for (i = 0; i < insn->vA; i++) {
877 if (i != 0) strcat(buffer, ",");
878 snprintf(buffer + strlen(buffer), 256, " v%d", insn->arg[i]);
879 }
880 }
881 else if (dfAttributes & DF_FORMAT_3RC) {
882 snprintf(buffer + strlen(buffer), 256,
883 " v%d..v%d", insn->vC, insn->vC + insn->vA - 1);
884 }
885 else {
886 if (dfAttributes & DF_A_IS_REG) {
887 snprintf(buffer + strlen(buffer), 256, " v%d", insn->vA);
888 }
889 if (dfAttributes & DF_B_IS_REG) {
890 snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vB);
891 }
892 else if ((int)opcode < (int)kMirOpFirst) {
893 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vB);
894 }
895 if (dfAttributes & DF_C_IS_REG) {
896 snprintf(buffer + strlen(buffer), 256, ", v%d", insn->vC);
897 }
898 else if ((int)opcode < (int)kMirOpFirst) {
899 snprintf(buffer + strlen(buffer), 256, ", (#%d)", insn->vC);
900 }
901 }
902 int length = strlen(buffer) + 1;
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]903 ret = (char*)oatNew(length, false);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]904 memcpy(ret, buffer, length);
905 return ret;
906}
907
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]908char* getSSAName(const CompilationUnit* cUnit, int ssaReg, char* name)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]909{
910 int ssa2DalvikValue = oatConvertSSARegToDalvik(cUnit, ssaReg);
911
912 sprintf(name, "v%d_%d",
913 DECODE_REG(ssa2DalvikValue), DECODE_SUB(ssa2DalvikValue));
914 return name;
915}
916
917/*
918 * Dalvik instruction disassembler with optional SSA printing.
919 */
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]920char* oatFullDisassembler(const CompilationUnit* cUnit,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]921 const MIR* mir)
922{
923 char buffer[256];
Elliott Hughes3b6baaa2011-10-14 19:13:56 -0700[diff] [blame]924 char operand0[32], operand1[32];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]925 const DecodedInstruction *insn = &mir->dalvikInsn;
926 int opcode = insn->opcode;
927 int dfAttributes = oatDataFlowAttributes[opcode];
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]928 char* ret;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]929 int length;
930 OpcodeFlags flags;
931
932 buffer[0] = 0;
933 if (opcode >= kMirOpFirst) {
934 if (opcode == kMirOpPhi) {
935 snprintf(buffer, 256, "PHI %s = (%s",
936 getSSAName(cUnit, mir->ssaRep->defs[0], operand0),
937 getSSAName(cUnit, mir->ssaRep->uses[0], operand1));
938 int i;
939 for (i = 1; i < mir->ssaRep->numUses; i++) {
940 snprintf(buffer + strlen(buffer), 256, ", %s",
941 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
942 }
943 snprintf(buffer + strlen(buffer), 256, ")");
944 }
945 else {
946 sprintf(buffer, "Opcode %#x", opcode);
947 }
948 goto done;
949 } else {
950 strcpy(buffer, dexGetOpcodeName((Opcode)opcode));
951 }
952
953 flags = dexGetFlagsFromOpcode((Opcode)opcode);
954 /* For branches, decode the instructions to print out the branch targets */
955 if (flags & kInstrCanBranch) {
956 InstructionFormat dalvikFormat = dexGetFormatFromOpcode(insn->opcode);
957 int delta = 0;
958 switch (dalvikFormat) {
959 case kFmt21t:
960 snprintf(buffer + strlen(buffer), 256, " %s, ",
961 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
962 delta = (int) insn->vB;
963 break;
964 case kFmt22t:
965 snprintf(buffer + strlen(buffer), 256, " %s, %s, ",
966 getSSAName(cUnit, mir->ssaRep->uses[0], operand0),
967 getSSAName(cUnit, mir->ssaRep->uses[1], operand1));
968 delta = (int) insn->vC;
969 break;
970 case kFmt10t:
971 case kFmt20t:
972 case kFmt30t:
973 delta = (int) insn->vA;
974 break;
975 default:
976 LOG(FATAL) << "Unexpected branch format: " <<
977 (int)dalvikFormat;
978 }
979 snprintf(buffer + strlen(buffer), 256, " %04x",
980 mir->offset + delta);
981 } else if (dfAttributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) {
982 unsigned int i;
983 for (i = 0; i < insn->vA; i++) {
984 if (i != 0) strcat(buffer, ",");
985 snprintf(buffer + strlen(buffer), 256, " %s",
986 getSSAName(cUnit, mir->ssaRep->uses[i], operand0));
987 }
988 } else {
989 int udIdx;
990 if (mir->ssaRep->numDefs) {
991
992 for (udIdx = 0; udIdx < mir->ssaRep->numDefs; udIdx++) {
993 snprintf(buffer + strlen(buffer), 256, " %s",
994 getSSAName(cUnit, mir->ssaRep->defs[udIdx], operand0));
995 }
996 strcat(buffer, ",");
997 }
998 if (mir->ssaRep->numUses) {
999 /* No leading ',' for the first use */
1000 snprintf(buffer + strlen(buffer), 256, " %s",
1001 getSSAName(cUnit, mir->ssaRep->uses[0], operand0));
1002 for (udIdx = 1; udIdx < mir->ssaRep->numUses; udIdx++) {
1003 snprintf(buffer + strlen(buffer), 256, ", %s",
1004 getSSAName(cUnit, mir->ssaRep->uses[udIdx], operand0));
1005 }
1006 }
1007 if (opcode < kMirOpFirst) {
1008 InstructionFormat dalvikFormat =
1009 dexGetFormatFromOpcode((Opcode)opcode);
1010 switch (dalvikFormat) {
1011 case kFmt11n: // op vA, #+B
1012 case kFmt21s: // op vAA, #+BBBB
1013 case kFmt21h: // op vAA, #+BBBB00000[00000000]
1014 case kFmt31i: // op vAA, #+BBBBBBBB
1015 case kFmt51l: // op vAA, #+BBBBBBBBBBBBBBBB
1016 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vB);
1017 break;
1018 case kFmt21c: // op vAA, thing@BBBB
1019 case kFmt31c: // op vAA, thing@BBBBBBBB
1020 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vB);
1021 break;
1022 case kFmt22b: // op vAA, vBB, #+CC
1023 case kFmt22s: // op vA, vB, #+CCCC
1024 snprintf(buffer + strlen(buffer), 256, " #%#x", insn->vC);
1025 break;
1026 case kFmt22c: // op vA, vB, thing@CCCC
1027 case kFmt22cs: // [opt] op vA, vB, field offset CCCC
1028 snprintf(buffer + strlen(buffer), 256, " @%#x", insn->vC);
1029 break;
1030 /* No need for special printing */
1031 default:
1032 break;
1033 }
1034 }
1035 }
1036
1037done:
1038 length = strlen(buffer) + 1;
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]1039 ret = (char*) oatNew(length, false);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1040 memcpy(ret, buffer, length);
1041 return ret;
1042}
1043
1044/*
1045 * Utility function to convert encoded SSA register value into Dalvik register
1046 * and subscript pair. Each SSA register can be used to index the
1047 * ssaToDalvikMap list to get the subscript[31..16]/dalvik_reg[15..0] mapping.
1048 */
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]1049char* oatGetSSAString(CompilationUnit* cUnit, SSARepresentation* ssaRep)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1050{
1051 char buffer[256];
1052 char* ret;
1053 int i;
1054
1055 buffer[0] = 0;
1056 for (i = 0; i < ssaRep->numDefs; i++) {
1057 int ssa2DalvikValue = oatConvertSSARegToDalvik(cUnit, ssaRep->defs[i]);
1058
1059 sprintf(buffer + strlen(buffer), "s%d(v%d_%d) ",
1060 ssaRep->defs[i], DECODE_REG(ssa2DalvikValue),
1061 DECODE_SUB(ssa2DalvikValue));
1062 }
1063
1064 if (ssaRep->numDefs) {
1065 strcat(buffer, "<- ");
1066 }
1067
1068 for (i = 0; i < ssaRep->numUses; i++) {
1069 int ssa2DalvikValue = oatConvertSSARegToDalvik(cUnit, ssaRep->uses[i]);
1070 int len = strlen(buffer);
1071
1072 if (snprintf(buffer + len, 250 - len, "s%d(v%d_%d) ",
1073 ssaRep->uses[i], DECODE_REG(ssa2DalvikValue),
1074 DECODE_SUB(ssa2DalvikValue)) >= (250 - len)) {
1075 strcat(buffer, "...");
1076 break;
1077 }
1078 }
1079
1080 int length = strlen(buffer) + 1;
Elliott Hughesc1f143d2011-12-01 17:31:10 -0800[diff] [blame]1081 ret = (char*)oatNew(length, false);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1082 memcpy(ret, buffer, length);
1083 return ret;
1084}
1085
1086/* Any register that is used before being defined is considered live-in */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1087STATIC inline void handleLiveInUse(ArenaBitVector* useV, ArenaBitVector* defV,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1088 ArenaBitVector* liveInV, int dalvikRegId)
1089{
1090 oatSetBit(useV, dalvikRegId);
1091 if (!oatIsBitSet(defV, dalvikRegId)) {
1092 oatSetBit(liveInV, dalvikRegId);
1093 }
1094}
1095
1096/* Mark a reg as being defined */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1097STATIC inline void handleDef(ArenaBitVector* defV, int dalvikRegId)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1098{
1099 oatSetBit(defV, dalvikRegId);
1100}
1101
1102/*
1103 * Find out live-in variables for natural loops. Variables that are live-in in
1104 * the main loop body are considered to be defined in the entry block.
1105 */
1106bool oatFindLocalLiveIn(CompilationUnit* cUnit, BasicBlock* bb)
1107{
1108 MIR* mir;
1109 ArenaBitVector *useV, *defV, *liveInV;
1110
1111 if (bb->dataFlowInfo == NULL) return false;
1112
1113 useV = bb->dataFlowInfo->useV =
1114 oatAllocBitVector(cUnit->numDalvikRegisters, false);
1115 defV = bb->dataFlowInfo->defV =
1116 oatAllocBitVector(cUnit->numDalvikRegisters, false);
1117 liveInV = bb->dataFlowInfo->liveInV =
1118 oatAllocBitVector(cUnit->numDalvikRegisters, false);
1119
1120 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1121 int dfAttributes =
1122 oatDataFlowAttributes[mir->dalvikInsn.opcode];
1123 DecodedInstruction *dInsn = &mir->dalvikInsn;
1124
1125 if (dfAttributes & DF_HAS_USES) {
1126 if (dfAttributes & DF_UA) {
1127 handleLiveInUse(useV, defV, liveInV, dInsn->vA);
1128 } else if (dfAttributes & DF_UA_WIDE) {
1129 handleLiveInUse(useV, defV, liveInV, dInsn->vA);
1130 handleLiveInUse(useV, defV, liveInV, dInsn->vA+1);
1131 }
1132 if (dfAttributes & DF_UB) {
1133 handleLiveInUse(useV, defV, liveInV, dInsn->vB);
1134 } else if (dfAttributes & DF_UB_WIDE) {
1135 handleLiveInUse(useV, defV, liveInV, dInsn->vB);
1136 handleLiveInUse(useV, defV, liveInV, dInsn->vB+1);
1137 }
1138 if (dfAttributes & DF_UC) {
1139 handleLiveInUse(useV, defV, liveInV, dInsn->vC);
1140 } else if (dfAttributes & DF_UC_WIDE) {
1141 handleLiveInUse(useV, defV, liveInV, dInsn->vC);
1142 handleLiveInUse(useV, defV, liveInV, dInsn->vC+1);
1143 }
1144 }
1145 if (dfAttributes & DF_HAS_DEFS) {
1146 handleDef(defV, dInsn->vA);
1147 if (dfAttributes & DF_DA_WIDE) {
1148 handleDef(defV, dInsn->vA+1);
1149 }
1150 }
1151 }
1152 return true;
1153}
1154
1155/* Find out the latest SSA register for a given Dalvik register */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1156STATIC void handleSSAUse(CompilationUnit* cUnit, int* uses, int dalvikReg,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1157 int regIndex)
1158{
1159 int encodedValue = cUnit->dalvikToSSAMap[dalvikReg];
1160 int ssaReg = DECODE_REG(encodedValue);
1161 uses[regIndex] = ssaReg;
1162}
1163
1164/* Setup a new SSA register for a given Dalvik register */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1165STATIC void handleSSADef(CompilationUnit* cUnit, int* defs, int dalvikReg,
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1166 int regIndex)
1167{
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1168 int ssaReg = cUnit->numSSARegs++;
1169 /* Bump up the subscript */
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1170 int dalvikSub = ++cUnit->SSALastDefs[dalvikReg];
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1171 int newD2SMapping = ENCODE_REG_SUB(ssaReg, dalvikSub);
1172
1173 cUnit->dalvikToSSAMap[dalvikReg] = newD2SMapping;
1174
1175 int newS2DMapping = ENCODE_REG_SUB(dalvikReg, dalvikSub);
1176 oatInsertGrowableList(cUnit->ssaToDalvikMap, newS2DMapping);
1177
1178 defs[regIndex] = ssaReg;
1179}
1180
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1181/* Look up new SSA names for format_35c instructions */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1182STATIC void dataFlowSSAFormat35C(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1183{
1184 DecodedInstruction *dInsn = &mir->dalvikInsn;
1185 int numUses = dInsn->vA;
1186 int i;
1187
1188 mir->ssaRep->numUses = numUses;
buzbeec0ecd652011-09-25 18:11:54 -0700[diff] [blame]1189 mir->ssaRep->uses = (int *)oatNew(sizeof(int) * numUses, true);
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1190 // NOTE: will be filled in during type & size inference pass
buzbeec0ecd652011-09-25 18:11:54 -0700[diff] [blame]1191 mir->ssaRep->fpUse = (bool *)oatNew(sizeof(bool) * numUses, true);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1192
1193 for (i = 0; i < numUses; i++) {
1194 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->arg[i], i);
1195 }
1196}
1197
buzbeeec5adf32011-09-11 15:25:43 -0700[diff] [blame]1198/* Look up new SSA names for format_3rc instructions */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1199STATIC void dataFlowSSAFormat3RC(CompilationUnit* cUnit, MIR* mir)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1200{
1201 DecodedInstruction *dInsn = &mir->dalvikInsn;
1202 int numUses = dInsn->vA;
1203 int i;
1204
1205 mir->ssaRep->numUses = numUses;
buzbeec0ecd652011-09-25 18:11:54 -0700[diff] [blame]1206 mir->ssaRep->uses = (int *)oatNew(sizeof(int) * numUses, true);
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1207 // NOTE: will be filled in during type & size inference pass
buzbeec0ecd652011-09-25 18:11:54 -0700[diff] [blame]1208 mir->ssaRep->fpUse = (bool *)oatNew(sizeof(bool) * numUses, true);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1209
1210 for (i = 0; i < numUses; i++) {
1211 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+i, i);
1212 }
1213}
1214
1215/* Entry function to convert a block into SSA representation */
1216bool oatDoSSAConversion(CompilationUnit* cUnit, BasicBlock* bb)
1217{
1218 MIR* mir;
1219
1220 if (bb->dataFlowInfo == NULL) return false;
1221
1222 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1223 mir->ssaRep = (struct SSARepresentation *)
1224 oatNew(sizeof(SSARepresentation), true);
1225
1226 int dfAttributes =
1227 oatDataFlowAttributes[mir->dalvikInsn.opcode];
1228
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1229 // If not a pseudo-op, note non-leaf or can throw
1230 if (mir->dalvikInsn.opcode < kNumPackedOpcodes) {
1231 int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1232
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1233 if (flags & kInstrCanThrow) {
1234 cUnit->attrs &= ~METHOD_IS_THROW_FREE;
1235 }
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1236
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1237 if (flags & kInstrInvoke) {
1238 cUnit->attrs &= ~METHOD_IS_LEAF;
1239 }
buzbeecefd1872011-09-09 09:59:52 -0700[diff] [blame]1240 }
1241
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1242 int numUses = 0;
1243
1244 if (dfAttributes & DF_FORMAT_35C) {
1245 dataFlowSSAFormat35C(cUnit, mir);
1246 continue;
1247 }
1248
1249 if (dfAttributes & DF_FORMAT_3RC) {
1250 dataFlowSSAFormat3RC(cUnit, mir);
1251 continue;
1252 }
1253
1254 if (dfAttributes & DF_HAS_USES) {
1255 if (dfAttributes & DF_UA) {
1256 numUses++;
1257 } else if (dfAttributes & DF_UA_WIDE) {
1258 numUses += 2;
1259 }
1260 if (dfAttributes & DF_UB) {
1261 numUses++;
1262 } else if (dfAttributes & DF_UB_WIDE) {
1263 numUses += 2;
1264 }
1265 if (dfAttributes & DF_UC) {
1266 numUses++;
1267 } else if (dfAttributes & DF_UC_WIDE) {
1268 numUses += 2;
1269 }
1270 }
1271
1272 if (numUses) {
1273 mir->ssaRep->numUses = numUses;
1274 mir->ssaRep->uses = (int *)oatNew(sizeof(int) * numUses,
1275 false);
1276 mir->ssaRep->fpUse = (bool *)oatNew(sizeof(bool) * numUses,
1277 false);
1278 }
1279
1280 int numDefs = 0;
1281
1282 if (dfAttributes & DF_HAS_DEFS) {
1283 numDefs++;
1284 if (dfAttributes & DF_DA_WIDE) {
1285 numDefs++;
1286 }
1287 }
1288
1289 if (numDefs) {
1290 mir->ssaRep->numDefs = numDefs;
1291 mir->ssaRep->defs = (int *)oatNew(sizeof(int) * numDefs,
1292 false);
1293 mir->ssaRep->fpDef = (bool *)oatNew(sizeof(bool) * numDefs,
1294 false);
1295 }
1296
1297 DecodedInstruction *dInsn = &mir->dalvikInsn;
1298
1299 if (dfAttributes & DF_HAS_USES) {
1300 numUses = 0;
1301 if (dfAttributes & DF_UA) {
1302 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1303 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
1304 } else if (dfAttributes & DF_UA_WIDE) {
1305 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1306 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA, numUses++);
1307 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_A;
1308 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vA+1, numUses++);
1309 }
1310 if (dfAttributes & DF_UB) {
1311 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1312 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
1313 } else if (dfAttributes & DF_UB_WIDE) {
1314 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1315 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB, numUses++);
1316 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_B;
1317 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vB+1, numUses++);
1318 }
1319 if (dfAttributes & DF_UC) {
1320 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1321 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
1322 } else if (dfAttributes & DF_UC_WIDE) {
1323 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1324 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC, numUses++);
1325 mir->ssaRep->fpUse[numUses] = dfAttributes & DF_FP_C;
1326 handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+1, numUses++);
1327 }
1328 }
1329 if (dfAttributes & DF_HAS_DEFS) {
1330 mir->ssaRep->fpDef[0] = dfAttributes & DF_FP_A;
1331 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA, 0);
1332 if (dfAttributes & DF_DA_WIDE) {
1333 mir->ssaRep->fpDef[1] = dfAttributes & DF_FP_A;
1334 handleSSADef(cUnit, mir->ssaRep->defs, dInsn->vA+1, 1);
1335 }
1336 }
1337 }
1338
1339 /*
1340 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1341 * input to PHI nodes can be derived from the snapshot of all predecessor
1342 * blocks.
1343 */
1344 bb->dataFlowInfo->dalvikToSSAMap =
Ian Rogersa3760aa2011-11-14 14:32:37 -0800[diff] [blame]1345 (int *)oatNew(sizeof(int) * cUnit->numDalvikRegisters, false);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1346
1347 memcpy(bb->dataFlowInfo->dalvikToSSAMap, cUnit->dalvikToSSAMap,
Ian Rogersa3760aa2011-11-14 14:32:37 -0800[diff] [blame]1348 sizeof(int) * cUnit->numDalvikRegisters);
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1349 return true;
1350}
1351
1352/* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1353STATIC void setConstant(CompilationUnit* cUnit, int ssaReg, int value)
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1354{
1355 oatSetBit(cUnit->isConstantV, ssaReg);
1356 cUnit->constantValues[ssaReg] = value;
1357}
1358
1359bool oatDoConstantPropagation(CompilationUnit* cUnit, BasicBlock* bb)
1360{
1361 MIR* mir;
1362 ArenaBitVector *isConstantV = cUnit->isConstantV;
1363
1364 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
1365 int dfAttributes =
1366 oatDataFlowAttributes[mir->dalvikInsn.opcode];
1367
1368 DecodedInstruction *dInsn = &mir->dalvikInsn;
1369
1370 if (!(dfAttributes & DF_HAS_DEFS)) continue;
1371
1372 /* Handle instructions that set up constants directly */
1373 if (dfAttributes & DF_SETS_CONST) {
1374 if (dfAttributes & DF_DA) {
1375 switch (dInsn->opcode) {
1376 case OP_CONST_4:
1377 case OP_CONST_16:
1378 case OP_CONST:
1379 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1380 break;
1381 case OP_CONST_HIGH16:
1382 setConstant(cUnit, mir->ssaRep->defs[0],
1383 dInsn->vB << 16);
1384 break;
1385 default:
1386 break;
1387 }
1388 } else if (dfAttributes & DF_DA_WIDE) {
1389 switch (dInsn->opcode) {
1390 case OP_CONST_WIDE_16:
1391 case OP_CONST_WIDE_32:
1392 setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB);
1393 setConstant(cUnit, mir->ssaRep->defs[1], 0);
1394 break;
1395 case OP_CONST_WIDE:
1396 setConstant(cUnit, mir->ssaRep->defs[0],
1397 (int) dInsn->vB_wide);
1398 setConstant(cUnit, mir->ssaRep->defs[1],
1399 (int) (dInsn->vB_wide >> 32));
1400 break;
1401 case OP_CONST_WIDE_HIGH16:
1402 setConstant(cUnit, mir->ssaRep->defs[0], 0);
1403 setConstant(cUnit, mir->ssaRep->defs[1],
1404 dInsn->vB << 16);
1405 break;
1406 default:
1407 break;
1408 }
1409 }
1410 /* Handle instructions that set up constants directly */
1411 } else if (dfAttributes & DF_IS_MOVE) {
1412 int i;
1413
1414 for (i = 0; i < mir->ssaRep->numUses; i++) {
1415 if (!oatIsBitSet(isConstantV, mir->ssaRep->uses[i])) break;
1416 }
1417 /* Move a register holding a constant to another register */
1418 if (i == mir->ssaRep->numUses) {
1419 setConstant(cUnit, mir->ssaRep->defs[0],
1420 cUnit->constantValues[mir->ssaRep->uses[0]]);
1421 if (dfAttributes & DF_DA_WIDE) {
1422 setConstant(cUnit, mir->ssaRep->defs[1],
1423 cUnit->constantValues[mir->ssaRep->uses[1]]);
1424 }
1425 }
1426 }
1427 }
1428 /* TODO: implement code to handle arithmetic operations */
1429 return true;
1430}
1431
1432/* Setup the basic data structures for SSA conversion */
1433void oatInitializeSSAConversion(CompilationUnit* cUnit)
1434{
1435 int i;
Ian Rogersa3760aa2011-11-14 14:32:37 -0800[diff] [blame]1436 int numDalvikReg = cUnit->numDalvikRegisters;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1437
1438 cUnit->ssaToDalvikMap = (GrowableList *)oatNew(sizeof(GrowableList),
1439 false);
1440 oatInitGrowableList(cUnit->ssaToDalvikMap, numDalvikReg);
1441
1442 /*
1443 * Initial number of SSA registers is equal to the number of Dalvik
1444 * registers.
1445 */
1446 cUnit->numSSARegs = numDalvikReg;
1447
1448 /*
1449 * Initialize the SSA2Dalvik map list. For the first numDalvikReg elements,
1450 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1451 * into "(0 << 16) | i"
1452 */
1453 for (i = 0; i < numDalvikReg; i++) {
1454 oatInsertGrowableList(cUnit->ssaToDalvikMap, ENCODE_REG_SUB(i, 0));
1455 }
1456
1457 /*
1458 * Initialize the DalvikToSSAMap map. The low 16 bit is the SSA register id,
1459 * while the high 16 bit is the current subscript. The original Dalvik
1460 * register N is mapped to SSA register N with subscript 0.
1461 */
1462 cUnit->dalvikToSSAMap = (int *)oatNew(sizeof(int) * numDalvikReg,
1463 false);
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1464 /* Keep track of the higest def for each dalvik reg */
1465 cUnit->SSALastDefs = (int *)oatNew(sizeof(int) * numDalvikReg,
1466 false);
1467
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1468 for (i = 0; i < numDalvikReg; i++) {
1469 cUnit->dalvikToSSAMap[i] = i;
buzbeef0cde542011-09-13 14:55:02 -0700[diff] [blame]1470 cUnit->SSALastDefs[i] = 0;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1471 }
1472
1473 /*
1474 * Allocate the BasicBlockDataFlow structure for the entry and code blocks
1475 */
1476 GrowableListIterator iterator;
1477
1478 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
1479
1480 while (true) {
1481 BasicBlock* bb = (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1482 if (bb == NULL) break;
1483 if (bb->hidden == true) continue;
1484 if (bb->blockType == kDalvikByteCode ||
1485 bb->blockType == kEntryBlock ||
1486 bb->blockType == kExitBlock) {
1487 bb->dataFlowInfo = (BasicBlockDataFlow *)
1488 oatNew(sizeof(BasicBlockDataFlow),
1489 true);
1490 }
1491 }
1492}
1493
1494/* Clear the visited flag for each BB */
1495bool oatClearVisitedFlag(struct CompilationUnit* cUnit,
1496 struct BasicBlock* bb)
1497{
1498 bb->visited = false;
1499 return true;
1500}
1501
1502void oatDataFlowAnalysisDispatcher(CompilationUnit* cUnit,
1503 bool (*func)(CompilationUnit*, BasicBlock*),
1504 DataFlowAnalysisMode dfaMode,
1505 bool isIterative)
1506{
1507 bool change = true;
1508
1509 while (change) {
1510 change = false;
1511
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1512 switch (dfaMode) {
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1513 /* Scan all blocks and perform the operations specified in func */
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1514 case kAllNodes:
1515 {
1516 GrowableListIterator iterator;
1517 oatGrowableListIteratorInit(&cUnit->blockList, &iterator);
1518 while (true) {
1519 BasicBlock* bb =
1520 (BasicBlock *) oatGrowableListIteratorNext(&iterator);
1521 if (bb == NULL) break;
1522 if (bb->hidden == true) continue;
1523 change |= (*func)(cUnit, bb);
1524 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1525 }
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1526 break;
1527 /* Scan reachable blocks and perform the ops specified in func. */
1528 case kReachableNodes:
1529 {
1530 int numReachableBlocks = cUnit->numReachableBlocks;
1531 int idx;
1532 const GrowableList *blockList = &cUnit->blockList;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1533
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1534 for (idx = 0; idx < numReachableBlocks; idx++) {
1535 int blockIdx = cUnit->dfsOrder.elemList[idx];
1536 BasicBlock* bb =
1537 (BasicBlock *) oatGrowableListGetElement(blockList,
1538 blockIdx);
1539 change |= (*func)(cUnit, bb);
1540 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1541 }
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1542 break;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1543
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1544 /* Scan reachable blocks by pre-order dfs and invoke func on each. */
1545 case kPreOrderDFSTraversal:
1546 {
1547 int numReachableBlocks = cUnit->numReachableBlocks;
1548 int idx;
1549 const GrowableList *blockList = &cUnit->blockList;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1550
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1551 for (idx = 0; idx < numReachableBlocks; idx++) {
1552 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1553 BasicBlock* bb =
1554 (BasicBlock *) oatGrowableListGetElement(blockList,
1555 dfsIdx);
1556 change |= (*func)(cUnit, bb);
1557 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1558 }
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1559 break;
1560 /* Scan reachable blocks post-order dfs and invoke func on each. */
1561 case kPostOrderDFSTraversal:
1562 {
1563 int numReachableBlocks = cUnit->numReachableBlocks;
1564 int idx;
1565 const GrowableList *blockList = &cUnit->blockList;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1566
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1567 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1568 int dfsIdx = cUnit->dfsOrder.elemList[idx];
1569 BasicBlock* bb =
1570 (BasicBlock *) oatGrowableListGetElement(blockList,
1571 dfsIdx);
1572 change |= (*func)(cUnit, bb);
1573 }
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1574 }
buzbee5b537102012-01-17 17:33:47 -0800[diff] [blame]1575 break;
1576 /* Scan reachable post-order dom tree and invoke func on each. */
1577 case kPostOrderDOMTraversal:
1578 {
1579 int numReachableBlocks = cUnit->numReachableBlocks;
1580 int idx;
1581 const GrowableList *blockList = &cUnit->blockList;
1582
1583 for (idx = 0; idx < numReachableBlocks; idx++) {
1584 int domIdx = cUnit->domPostOrderTraversal.elemList[idx];
1585 BasicBlock* bb =
1586 (BasicBlock *) oatGrowableListGetElement(blockList,
1587 domIdx);
1588 change |= (*func)(cUnit, bb);
1589 }
1590 }
1591 break;
1592 /* Scan reachable blocks reverse post-order dfs, invoke func on each */
1593 case kReversePostOrderTraversal:
1594 {
1595 int numReachableBlocks = cUnit->numReachableBlocks;
1596 int idx;
1597 const GrowableList *blockList = &cUnit->blockList;
1598
1599 for (idx = numReachableBlocks - 1; idx >= 0; idx--) {
1600 int revIdx = cUnit->dfsPostOrder.elemList[idx];
1601 BasicBlock* bb =
1602 (BasicBlock *) oatGrowableListGetElement(blockList,
1603 revIdx);
1604 change |= (*func)(cUnit, bb);
1605 }
1606 }
1607 break;
1608 default:
1609 LOG(FATAL) << "Unknown traversal mode " << (int)dfaMode;
buzbee67bf8852011-08-17 17:51:35 -0700[diff] [blame]1610 }
1611 /* If isIterative is false, exit the loop after the first iteration */
1612 change &= isIterative;
1613 }
1614}
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1615
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1616STATIC bool nullCheckEliminationInit(struct CompilationUnit* cUnit,
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1617 struct BasicBlock* bb)
1618{
1619 if (bb->dataFlowInfo == NULL) return false;
1620 bb->dataFlowInfo->endingNullCheckV =
1621 oatAllocBitVector(cUnit->numSSARegs, false);
1622 oatClearAllBits(bb->dataFlowInfo->endingNullCheckV);
1623 return true;
1624}
1625
1626/* Eliminate unnecessary null checks for a basic block. */
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1627STATIC bool eliminateNullChecks( struct CompilationUnit* cUnit,
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1628 struct BasicBlock* bb)
1629{
1630 if (bb->dataFlowInfo == NULL) return false;
1631 /*
1632 * Set initial state. Be conservative with catch
1633 * blocks and start with no assumptions about null check
1634 * status (except for "this").
1635 */
1636
1637 if ((bb->blockType == kEntryBlock) | bb->catchEntry) {
1638 oatClearAllBits(cUnit->tempSSARegisterV);
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]1639 if ((cUnit->access_flags & kAccStatic) == 0) {
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1640 // If non-static method, mark "this" as non-null
Ian Rogersa3760aa2011-11-14 14:32:37 -0800[diff] [blame]1641 int thisReg = cUnit->numDalvikRegisters - cUnit->numIns;
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1642 oatSetBit(cUnit->tempSSARegisterV, thisReg);
1643 }
1644 } else {
1645 // Starting state is intesection of all incoming arcs
1646 GrowableList* blockList = &cUnit->blockList;
1647 ArenaBitVectorIterator bvIterator;
1648 oatBitVectorIteratorInit(bb->predecessors, &bvIterator);
1649 int predBBIdx = oatBitVectorIteratorNext(&bvIterator);
buzbeeed3e9302011-09-23 17:34:19 -0700[diff] [blame]1650 DCHECK_NE(predBBIdx, -1);
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1651 BasicBlock* predBB = (BasicBlock*)oatGrowableListGetElement(
1652 blockList, predBBIdx);
1653 oatCopyBitVector(cUnit->tempSSARegisterV,
1654 predBB->dataFlowInfo->endingNullCheckV);
1655 while (true) {
1656 predBBIdx = oatBitVectorIteratorNext(&bvIterator);
1657 if (predBBIdx == -1) break;
1658 predBB = (BasicBlock*)oatGrowableListGetElement(
1659 blockList, predBBIdx);
buzbeeaad72012011-09-21 21:52:09 -0700[diff] [blame]1660 if ((predBB->dataFlowInfo == NULL) ||
1661 (predBB->dataFlowInfo->endingNullCheckV == NULL)) {
1662 continue;
1663 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1664 oatIntersectBitVectors(cUnit->tempSSARegisterV,
1665 cUnit->tempSSARegisterV,
1666 predBB->dataFlowInfo->endingNullCheckV);
1667 }
1668 }
1669
1670 // Walk through the instruction in the block, updating as necessary
1671 for (MIR* mir = bb->firstMIRInsn; mir; mir = mir->next) {
1672 if (mir->ssaRep == NULL) {
1673 continue;
1674 }
1675 int dfAttributes =
1676 oatDataFlowAttributes[mir->dalvikInsn.opcode];
1677
1678 // Mark target of NEW* as non-null
1679 if (dfAttributes & DF_NON_NULL_DST) {
1680 oatSetBit(cUnit->tempSSARegisterV, mir->ssaRep->defs[0]);
1681 }
1682
1683 // Mark non-null returns from invoke-style NEW*
1684 if (dfAttributes & DF_NON_NULL_RET) {
1685 MIR* nextMir = mir->next;
1686 // Next should be an OP_MOVE_RESULT_OBJECT
1687 if (nextMir && nextMir->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT) {
1688 // Mark as null checked
buzbee949f56e2011-10-06 11:05:45 -0700[diff] [blame]1689 oatSetBit(cUnit->tempSSARegisterV, nextMir->ssaRep->defs[0]);
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1690 } else {
1691 if (nextMir) {
1692 LOG(WARNING) << "Unexpected opcode following new: " <<
1693 (int)nextMir->dalvikInsn.opcode;
buzbee949f56e2011-10-06 11:05:45 -0700[diff] [blame]1694 } else if (bb->fallThrough) {
1695 // Look in next basic block
1696 struct BasicBlock* nextBB = bb->fallThrough;
1697 for (MIR* tmir = nextBB->firstMIRInsn; tmir;
1698 tmir =tmir->next){
1699 if ((int)tmir->dalvikInsn.opcode >= (int)kMirOpFirst) {
1700 continue;
1701 }
1702 // First non-pseudo should be OP_MOVE_RESULT_OBJECT
1703 if (tmir->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT) {
1704 // Mark as null checked
1705 oatSetBit(cUnit->tempSSARegisterV,
1706 tmir->ssaRep->defs[0]);
1707 } else {
1708 LOG(WARNING) << "Unexpected op after new: " <<
1709 (int)tmir->dalvikInsn.opcode;
1710 }
1711 break;
1712 }
buzbee43a36422011-09-14 14:00:13 -0700[diff] [blame]1713 }
1714 }
1715 }
1716
1717 /*
1718 * Propagate nullcheck state on register copies (including
1719 * Phi pseudo copies. For the latter, nullcheck state is
1720 * the "and" of all the Phi's operands.
1721 */
1722 if (dfAttributes & (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N)) {
1723 int tgtSreg = mir->ssaRep->defs[0];
1724 int operands = (dfAttributes & DF_NULL_TRANSFER_0) ? 1 :
1725 mir->ssaRep->numUses;
1726 bool nullChecked = true;
1727 for (int i = 0; i < operands; i++) {
1728 nullChecked &= oatIsBitSet(cUnit->tempSSARegisterV,
1729 mir->ssaRep->uses[i]);
1730 }
1731 if (nullChecked) {
1732 oatSetBit(cUnit->tempSSARegisterV, tgtSreg);
1733 }
1734 }
1735
1736 // Already nullchecked?
1737 if (dfAttributes & DF_HAS_NULL_CHKS) {
1738 int srcSreg = (dfAttributes & DF_NULL_CHK_1) ?
1739 mir->ssaRep->uses[1] : mir->ssaRep->uses[0];
1740 if (oatIsBitSet(cUnit->tempSSARegisterV, srcSreg)) {
1741 // Eliminate the null check
1742 mir->optimizationFlags |= MIR_IGNORE_NULL_CHECK;
1743 } else {
1744 // Mark sReg as null-checked
1745 oatSetBit(cUnit->tempSSARegisterV, srcSreg);
1746 }
1747 }
1748 }
1749
1750 // Did anything change?
1751 bool res = oatCompareBitVectors(bb->dataFlowInfo->endingNullCheckV,
1752 cUnit->tempSSARegisterV);
1753 if (res) {
1754 oatCopyBitVector(bb->dataFlowInfo->endingNullCheckV,
1755 cUnit->tempSSARegisterV);
1756 }
1757 return res;
1758}
1759
1760void oatMethodNullCheckElimination(CompilationUnit *cUnit)
1761{
1762 if (!(cUnit->disableOpt & (1 << kNullCheckElimination))) {
1763 DCHECK(cUnit->tempSSARegisterV != NULL);
1764 oatDataFlowAnalysisDispatcher(cUnit, nullCheckEliminationInit,
1765 kAllNodes,
1766 false /* isIterative */);
1767 oatDataFlowAnalysisDispatcher(cUnit, eliminateNullChecks,
1768 kPreOrderDFSTraversal,
1769 true /* isIterative */);
1770 }
1771}
Elliott Hughes11d1b0c2012-01-23 16:57:47 -0800[diff] [blame]1772
1773} // namespace art