blob: bdd105fce75f3644488321bc059818403f500255 [file] [log] [blame]
Alexandre Rames22aa54b2016-10-18 09:32:29 +01001/*
2 * Copyright (C) 2016 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_OPTIMIZING_CODEGEN_TEST_UTILS_H_
18#define ART_COMPILER_OPTIMIZING_CODEGEN_TEST_UTILS_H_
19
20#include "arch/arm/instruction_set_features_arm.h"
21#include "arch/arm/registers_arm.h"
22#include "arch/arm64/instruction_set_features_arm64.h"
23#include "arch/instruction_set.h"
24#include "arch/mips/instruction_set_features_mips.h"
25#include "arch/mips/registers_mips.h"
26#include "arch/mips64/instruction_set_features_mips64.h"
27#include "arch/mips64/registers_mips64.h"
28#include "arch/x86/instruction_set_features_x86.h"
29#include "arch/x86/registers_x86.h"
30#include "arch/x86_64/instruction_set_features_x86_64.h"
Andreas Gampe71da4872017-07-26 10:02:07 -070031#include "code_simulator.h"
Alexandre Rames22aa54b2016-10-18 09:32:29 +010032#include "code_simulator_container.h"
33#include "common_compiler_test.h"
34#include "graph_checker.h"
35#include "prepare_for_register_allocation.h"
36#include "ssa_liveness_analysis.h"
37
38#ifdef ART_ENABLE_CODEGEN_arm
Alexandre Rames22aa54b2016-10-18 09:32:29 +010039#include "code_generator_arm_vixl.h"
40#endif
41
42#ifdef ART_ENABLE_CODEGEN_arm64
43#include "code_generator_arm64.h"
44#endif
45
46#ifdef ART_ENABLE_CODEGEN_x86
47#include "code_generator_x86.h"
48#endif
49
50#ifdef ART_ENABLE_CODEGEN_x86_64
51#include "code_generator_x86_64.h"
52#endif
53
54#ifdef ART_ENABLE_CODEGEN_mips
55#include "code_generator_mips.h"
56#endif
57
58#ifdef ART_ENABLE_CODEGEN_mips64
59#include "code_generator_mips64.h"
60#endif
61
62namespace art {
63
64typedef CodeGenerator* (*CreateCodegenFn)(HGraph*, const CompilerOptions&);
65
66class CodegenTargetConfig {
67 public:
68 CodegenTargetConfig(InstructionSet isa, CreateCodegenFn create_codegen)
69 : isa_(isa), create_codegen_(create_codegen) {
70 }
71 InstructionSet GetInstructionSet() const { return isa_; }
72 CodeGenerator* CreateCodeGenerator(HGraph* graph, const CompilerOptions& compiler_options) {
73 return create_codegen_(graph, compiler_options);
74 }
75
76 private:
Alexandre Rames22aa54b2016-10-18 09:32:29 +010077 InstructionSet isa_;
78 CreateCodegenFn create_codegen_;
79};
80
81#ifdef ART_ENABLE_CODEGEN_arm
82// Provide our own codegen, that ensures the C calling conventions
83// are preserved. Currently, ART and C do not match as R4 is caller-save
84// in ART, and callee-save in C. Alternatively, we could use or write
85// the stub that saves and restores all registers, but it is easier
86// to just overwrite the code generator.
Alexandre Rames22aa54b2016-10-18 09:32:29 +010087class TestCodeGeneratorARMVIXL : public arm::CodeGeneratorARMVIXL {
88 public:
89 TestCodeGeneratorARMVIXL(HGraph* graph,
90 const ArmInstructionSetFeatures& isa_features,
91 const CompilerOptions& compiler_options)
92 : arm::CodeGeneratorARMVIXL(graph, isa_features, compiler_options) {
93 AddAllocatedRegister(Location::RegisterLocation(arm::R6));
94 AddAllocatedRegister(Location::RegisterLocation(arm::R7));
95 }
96
97 void SetupBlockedRegisters() const OVERRIDE {
98 arm::CodeGeneratorARMVIXL::SetupBlockedRegisters();
99 blocked_core_registers_[arm::R4] = true;
100 blocked_core_registers_[arm::R6] = false;
101 blocked_core_registers_[arm::R7] = false;
102 }
103};
104#endif
105
Roland Levillain2b03a1f2017-06-06 16:09:59 +0100106#ifdef ART_ENABLE_CODEGEN_arm64
107// Special ARM64 code generator for codegen testing in a limited code
108// generation environment (i.e. with no runtime support).
109//
110// Note: If we want to exercise certains HIR constructions
111// (e.g. reference field load in Baker read barrier configuration) in
112// codegen tests in the future, we should also:
113// - save the Thread Register (X19) and possibly the Marking Register
114// (X20) before entering the generated function (both registers are
115// callee-save in AAPCS64);
116// - set these registers to meaningful values before or upon entering
117// the generated function (so that generated code using them is
118// correct);
119// - restore their original values before leaving the generated
120// function.
121class TestCodeGeneratorARM64 : public arm64::CodeGeneratorARM64 {
122 public:
123 TestCodeGeneratorARM64(HGraph* graph,
124 const Arm64InstructionSetFeatures& isa_features,
125 const CompilerOptions& compiler_options)
126 : arm64::CodeGeneratorARM64(graph, isa_features, compiler_options) {}
127
128 void MaybeGenerateMarkingRegisterCheck(int codem ATTRIBUTE_UNUSED,
129 Location temp_loc ATTRIBUTE_UNUSED) OVERRIDE {
130 // When turned on, the marking register checks in
131 // CodeGeneratorARM64::MaybeGenerateMarkingRegisterCheck expect the
132 // Thread Register and the Marking Register to be set to
133 // meaningful values. This is not the case in codegen testing, so
134 // just disable them entirely here (by doing nothing in this
135 // method).
136 }
137};
138#endif
139
Alexandre Rames22aa54b2016-10-18 09:32:29 +0100140#ifdef ART_ENABLE_CODEGEN_x86
141class TestCodeGeneratorX86 : public x86::CodeGeneratorX86 {
142 public:
143 TestCodeGeneratorX86(HGraph* graph,
144 const X86InstructionSetFeatures& isa_features,
145 const CompilerOptions& compiler_options)
146 : x86::CodeGeneratorX86(graph, isa_features, compiler_options) {
147 // Save edi, we need it for getting enough registers for long multiplication.
148 AddAllocatedRegister(Location::RegisterLocation(x86::EDI));
149 }
150
151 void SetupBlockedRegisters() const OVERRIDE {
152 x86::CodeGeneratorX86::SetupBlockedRegisters();
153 // ebx is a callee-save register in C, but caller-save for ART.
154 blocked_core_registers_[x86::EBX] = true;
155
156 // Make edi available.
157 blocked_core_registers_[x86::EDI] = false;
158 }
159};
160#endif
161
162class InternalCodeAllocator : public CodeAllocator {
163 public:
164 InternalCodeAllocator() : size_(0) { }
165
166 virtual uint8_t* Allocate(size_t size) {
167 size_ = size;
168 memory_.reset(new uint8_t[size]);
169 return memory_.get();
170 }
171
172 size_t GetSize() const { return size_; }
173 uint8_t* GetMemory() const { return memory_.get(); }
174
175 private:
176 size_t size_;
177 std::unique_ptr<uint8_t[]> memory_;
178
179 DISALLOW_COPY_AND_ASSIGN(InternalCodeAllocator);
180};
181
182static bool CanExecuteOnHardware(InstructionSet target_isa) {
183 return (target_isa == kRuntimeISA)
184 // Handle the special case of ARM, with two instructions sets (ARM32 and Thumb-2).
185 || (kRuntimeISA == kArm && target_isa == kThumb2);
186}
187
188static bool CanExecute(InstructionSet target_isa) {
189 CodeSimulatorContainer simulator(target_isa);
190 return CanExecuteOnHardware(target_isa) || simulator.CanSimulate();
191}
192
193template <typename Expected>
194inline static Expected SimulatorExecute(CodeSimulator* simulator, Expected (*f)());
195
196template <>
197inline bool SimulatorExecute<bool>(CodeSimulator* simulator, bool (*f)()) {
198 simulator->RunFrom(reinterpret_cast<intptr_t>(f));
199 return simulator->GetCReturnBool();
200}
201
202template <>
203inline int32_t SimulatorExecute<int32_t>(CodeSimulator* simulator, int32_t (*f)()) {
204 simulator->RunFrom(reinterpret_cast<intptr_t>(f));
205 return simulator->GetCReturnInt32();
206}
207
208template <>
209inline int64_t SimulatorExecute<int64_t>(CodeSimulator* simulator, int64_t (*f)()) {
210 simulator->RunFrom(reinterpret_cast<intptr_t>(f));
211 return simulator->GetCReturnInt64();
212}
213
214template <typename Expected>
215static void VerifyGeneratedCode(InstructionSet target_isa,
216 Expected (*f)(),
217 bool has_result,
218 Expected expected) {
219 ASSERT_TRUE(CanExecute(target_isa)) << "Target isa is not executable.";
220
221 // Verify on simulator.
222 CodeSimulatorContainer simulator(target_isa);
223 if (simulator.CanSimulate()) {
224 Expected result = SimulatorExecute<Expected>(simulator.Get(), f);
225 if (has_result) {
226 ASSERT_EQ(expected, result);
227 }
228 }
229
230 // Verify on hardware.
231 if (CanExecuteOnHardware(target_isa)) {
232 Expected result = f();
233 if (has_result) {
234 ASSERT_EQ(expected, result);
235 }
236 }
237}
238
239template <typename Expected>
240static void Run(const InternalCodeAllocator& allocator,
241 const CodeGenerator& codegen,
242 bool has_result,
243 Expected expected) {
244 InstructionSet target_isa = codegen.GetInstructionSet();
245
246 typedef Expected (*fptr)();
247 CommonCompilerTest::MakeExecutable(allocator.GetMemory(), allocator.GetSize());
248 fptr f = reinterpret_cast<fptr>(allocator.GetMemory());
249 if (target_isa == kThumb2) {
250 // For thumb we need the bottom bit set.
251 f = reinterpret_cast<fptr>(reinterpret_cast<uintptr_t>(f) + 1);
252 }
253 VerifyGeneratedCode(target_isa, f, has_result, expected);
254}
255
256static void ValidateGraph(HGraph* graph) {
257 GraphChecker graph_checker(graph);
258 graph_checker.Run();
259 if (!graph_checker.IsValid()) {
Vladimir Marko7d157fc2017-05-10 16:29:23 +0100260 for (const std::string& error : graph_checker.GetErrors()) {
Alexandre Rames22aa54b2016-10-18 09:32:29 +0100261 std::cout << error << std::endl;
262 }
263 }
264 ASSERT_TRUE(graph_checker.IsValid());
265}
266
267template <typename Expected>
268static void RunCodeNoCheck(CodeGenerator* codegen,
269 HGraph* graph,
270 const std::function<void(HGraph*)>& hook_before_codegen,
271 bool has_result,
272 Expected expected) {
273 SsaLivenessAnalysis liveness(graph, codegen);
274 PrepareForRegisterAllocation(graph).Run();
275 liveness.Analyze();
276 RegisterAllocator::Create(graph->GetArena(), codegen, liveness)->AllocateRegisters();
277 hook_before_codegen(graph);
278 InternalCodeAllocator allocator;
279 codegen->Compile(&allocator);
280 Run(allocator, *codegen, has_result, expected);
281}
282
283template <typename Expected>
284static void RunCode(CodeGenerator* codegen,
285 HGraph* graph,
286 std::function<void(HGraph*)> hook_before_codegen,
287 bool has_result,
288 Expected expected) {
289 ValidateGraph(graph);
290 RunCodeNoCheck(codegen, graph, hook_before_codegen, has_result, expected);
291}
292
293template <typename Expected>
294static void RunCode(CodegenTargetConfig target_config,
295 HGraph* graph,
296 std::function<void(HGraph*)> hook_before_codegen,
297 bool has_result,
298 Expected expected) {
299 CompilerOptions compiler_options;
Roland Levillain2b03a1f2017-06-06 16:09:59 +0100300 std::unique_ptr<CodeGenerator> codegen(target_config.CreateCodeGenerator(graph,
301 compiler_options));
Alexandre Rames22aa54b2016-10-18 09:32:29 +0100302 RunCode(codegen.get(), graph, hook_before_codegen, has_result, expected);
303}
304
305#ifdef ART_ENABLE_CODEGEN_arm
Alexandre Rames22aa54b2016-10-18 09:32:29 +0100306CodeGenerator* create_codegen_arm_vixl32(HGraph* graph, const CompilerOptions& compiler_options) {
307 std::unique_ptr<const ArmInstructionSetFeatures> features_arm(
308 ArmInstructionSetFeatures::FromCppDefines());
309 return new (graph->GetArena())
310 TestCodeGeneratorARMVIXL(graph, *features_arm.get(), compiler_options);
311}
312#endif
313
314#ifdef ART_ENABLE_CODEGEN_arm64
315CodeGenerator* create_codegen_arm64(HGraph* graph, const CompilerOptions& compiler_options) {
316 std::unique_ptr<const Arm64InstructionSetFeatures> features_arm64(
317 Arm64InstructionSetFeatures::FromCppDefines());
Roland Levillain2b03a1f2017-06-06 16:09:59 +0100318 return new (graph->GetArena())
319 TestCodeGeneratorARM64(graph, *features_arm64.get(), compiler_options);
Alexandre Rames22aa54b2016-10-18 09:32:29 +0100320}
321#endif
322
323#ifdef ART_ENABLE_CODEGEN_x86
324CodeGenerator* create_codegen_x86(HGraph* graph, const CompilerOptions& compiler_options) {
325 std::unique_ptr<const X86InstructionSetFeatures> features_x86(
326 X86InstructionSetFeatures::FromCppDefines());
327 return new (graph->GetArena()) TestCodeGeneratorX86(graph, *features_x86.get(), compiler_options);
328}
329#endif
330
331#ifdef ART_ENABLE_CODEGEN_x86_64
332CodeGenerator* create_codegen_x86_64(HGraph* graph, const CompilerOptions& compiler_options) {
333 std::unique_ptr<const X86_64InstructionSetFeatures> features_x86_64(
334 X86_64InstructionSetFeatures::FromCppDefines());
335 return new (graph->GetArena())
336 x86_64::CodeGeneratorX86_64(graph, *features_x86_64.get(), compiler_options);
337}
338#endif
339
340#ifdef ART_ENABLE_CODEGEN_mips
341CodeGenerator* create_codegen_mips(HGraph* graph, const CompilerOptions& compiler_options) {
342 std::unique_ptr<const MipsInstructionSetFeatures> features_mips(
343 MipsInstructionSetFeatures::FromCppDefines());
344 return new (graph->GetArena())
345 mips::CodeGeneratorMIPS(graph, *features_mips.get(), compiler_options);
346}
347#endif
348
349#ifdef ART_ENABLE_CODEGEN_mips64
350CodeGenerator* create_codegen_mips64(HGraph* graph, const CompilerOptions& compiler_options) {
351 std::unique_ptr<const Mips64InstructionSetFeatures> features_mips64(
352 Mips64InstructionSetFeatures::FromCppDefines());
353 return new (graph->GetArena())
354 mips64::CodeGeneratorMIPS64(graph, *features_mips64.get(), compiler_options);
355}
356#endif
357
358} // namespace art
359
360#endif // ART_COMPILER_OPTIMIZING_CODEGEN_TEST_UTILS_H_