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review.blissroms.org / platform_art / e8fc5df5d4bc4f11095e8640892c43c76128fa0b / . / src / compiler / dex / mir_dataflow.cc
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buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "compiler_internals.h"
18#include "local_value_numbering.h"
19#include "dataflow_iterator.h"
20
21namespace art {
22
23/*
24 * Main table containing data flow attributes for each bytecode. The
25 * first kNumPackedOpcodes entries are for Dalvik bytecode
26 * instructions, where extended opcode at the MIR level are appended
27 * afterwards.
28 *
29 * TODO - many optimization flags are incomplete - they will only limit the
30 * scope of optimizations but will not cause mis-optimizations.
31 */
32const int oat_data_flow_attributes[kMirOpLast] = {
33 // 00 NOP
34 DF_NOP,
35
36 // 01 MOVE vA, vB
37 DF_DA | DF_UB | DF_IS_MOVE,
38
39 // 02 MOVE_FROM16 vAA, vBBBB
40 DF_DA | DF_UB | DF_IS_MOVE,
41
42 // 03 MOVE_16 vAAAA, vBBBB
43 DF_DA | DF_UB | DF_IS_MOVE,
44
45 // 04 MOVE_WIDE vA, vB
46 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
47
48 // 05 MOVE_WIDE_FROM16 vAA, vBBBB
49 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
50
51 // 06 MOVE_WIDE_16 vAAAA, vBBBB
52 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
53
54 // 07 MOVE_OBJECT vA, vB
55 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
56
57 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
58 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
59
60 // 09 MOVE_OBJECT_16 vAAAA, vBBBB
61 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
62
63 // 0A MOVE_RESULT vAA
64 DF_DA,
65
66 // 0B MOVE_RESULT_WIDE vAA
67 DF_DA | DF_A_WIDE,
68
69 // 0C MOVE_RESULT_OBJECT vAA
70 DF_DA | DF_REF_A,
71
72 // 0D MOVE_EXCEPTION vAA
73 DF_DA | DF_REF_A,
74
75 // 0E RETURN_VOID
76 DF_NOP,
77
78 // 0F RETURN vAA
79 DF_UA,
80
81 // 10 RETURN_WIDE vAA
82 DF_UA | DF_A_WIDE,
83
84 // 11 RETURN_OBJECT vAA
85 DF_UA | DF_REF_A,
86
87 // 12 CONST_4 vA, #+B
88 DF_DA | DF_SETS_CONST,
89
90 // 13 CONST_16 vAA, #+BBBB
91 DF_DA | DF_SETS_CONST,
92
93 // 14 CONST vAA, #+BBBBBBBB
94 DF_DA | DF_SETS_CONST,
95
96 // 15 CONST_HIGH16 VAA, #+BBBB0000
97 DF_DA | DF_SETS_CONST,
98
99 // 16 CONST_WIDE_16 vAA, #+BBBB
100 DF_DA | DF_A_WIDE | DF_SETS_CONST,
101
102 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
103 DF_DA | DF_A_WIDE | DF_SETS_CONST,
104
105 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
106 DF_DA | DF_A_WIDE | DF_SETS_CONST,
107
108 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
109 DF_DA | DF_A_WIDE | DF_SETS_CONST,
110
111 // 1A CONST_STRING vAA, string@BBBB
112 DF_DA | DF_REF_A,
113
114 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
115 DF_DA | DF_REF_A,
116
117 // 1C CONST_CLASS vAA, type@BBBB
118 DF_DA | DF_REF_A,
119
120 // 1D MONITOR_ENTER vAA
121 DF_UA | DF_NULL_CHK_0 | DF_REF_A,
122
123 // 1E MONITOR_EXIT vAA
124 DF_UA | DF_NULL_CHK_0 | DF_REF_A,
125
126 // 1F CHK_CAST vAA, type@BBBB
127 DF_UA | DF_REF_A | DF_UMS,
128
129 // 20 INSTANCE_OF vA, vB, type@CCCC
130 DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS,
131
132 // 21 ARRAY_LENGTH vA, vB
133 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_REF_B,
134
135 // 22 NEW_INSTANCE vAA, type@BBBB
136 DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS,
137
138 // 23 NEW_ARRAY vA, vB, type@CCCC
139 DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS,
140
141 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
142 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
143
144 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
145 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
146
147 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
148 DF_UA | DF_REF_A | DF_UMS,
149
150 // 27 THROW vAA
151 DF_UA | DF_REF_A | DF_UMS,
152
153 // 28 GOTO
154 DF_NOP,
155
156 // 29 GOTO_16
157 DF_NOP,
158
159 // 2A GOTO_32
160 DF_NOP,
161
162 // 2B PACKED_SWITCH vAA, +BBBBBBBB
163 DF_UA,
164
165 // 2C SPARSE_SWITCH vAA, +BBBBBBBB
166 DF_UA,
167
168 // 2D CMPL_FLOAT vAA, vBB, vCC
169 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
170
171 // 2E CMPG_FLOAT vAA, vBB, vCC
172 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
173
174 // 2F CMPL_DOUBLE vAA, vBB, vCC
175 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
176
177 // 30 CMPG_DOUBLE vAA, vBB, vCC
178 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
179
180 // 31 CMP_LONG vAA, vBB, vCC
181 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
182
183 // 32 IF_EQ vA, vB, +CCCC
184 DF_UA | DF_UB,
185
186 // 33 IF_NE vA, vB, +CCCC
187 DF_UA | DF_UB,
188
189 // 34 IF_LT vA, vB, +CCCC
190 DF_UA | DF_UB,
191
192 // 35 IF_GE vA, vB, +CCCC
193 DF_UA | DF_UB,
194
195 // 36 IF_GT vA, vB, +CCCC
196 DF_UA | DF_UB,
197
198 // 37 IF_LE vA, vB, +CCCC
199 DF_UA | DF_UB,
200
201 // 38 IF_EQZ vAA, +BBBB
202 DF_UA,
203
204 // 39 IF_NEZ vAA, +BBBB
205 DF_UA,
206
207 // 3A IF_LTZ vAA, +BBBB
208 DF_UA,
209
210 // 3B IF_GEZ vAA, +BBBB
211 DF_UA,
212
213 // 3C IF_GTZ vAA, +BBBB
214 DF_UA,
215
216 // 3D IF_LEZ vAA, +BBBB
217 DF_UA,
218
219 // 3E UNUSED_3E
220 DF_NOP,
221
222 // 3F UNUSED_3F
223 DF_NOP,
224
225 // 40 UNUSED_40
226 DF_NOP,
227
228 // 41 UNUSED_41
229 DF_NOP,
230
231 // 42 UNUSED_42
232 DF_NOP,
233
234 // 43 UNUSED_43
235 DF_NOP,
236
237 // 44 AGET vAA, vBB, vCC
238 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
239
240 // 45 AGET_WIDE vAA, vBB, vCC
241 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
242
243 // 46 AGET_OBJECT vAA, vBB, vCC
244 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_A | DF_REF_B | DF_CORE_C,
245
246 // 47 AGET_BOOLEAN vAA, vBB, vCC
247 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
248
249 // 48 AGET_BYTE vAA, vBB, vCC
250 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
251
252 // 49 AGET_CHAR vAA, vBB, vCC
253 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
254
255 // 4A AGET_SHORT vAA, vBB, vCC
256 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C,
257
258 // 4B APUT vAA, vBB, vCC
259 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
260
261 // 4C APUT_WIDE vAA, vBB, vCC
262 DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_REF_B | DF_CORE_C,
263
264 // 4D APUT_OBJECT vAA, vBB, vCC
265 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_A | DF_REF_B | DF_CORE_C,
266
267 // 4E APUT_BOOLEAN vAA, vBB, vCC
268 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
269
270 // 4F APUT_BYTE vAA, vBB, vCC
271 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
272
273 // 50 APUT_CHAR vAA, vBB, vCC
274 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
275
276 // 51 APUT_SHORT vAA, vBB, vCC
277 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C,
278
279 // 52 IGET vA, vB, field@CCCC
280 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
281
282 // 53 IGET_WIDE vA, vB, field@CCCC
283 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
284
285 // 54 IGET_OBJECT vA, vB, field@CCCC
286 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
287
288 // 55 IGET_BOOLEAN vA, vB, field@CCCC
289 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
290
291 // 56 IGET_BYTE vA, vB, field@CCCC
292 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
293
294 // 57 IGET_CHAR vA, vB, field@CCCC
295 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
296
297 // 58 IGET_SHORT vA, vB, field@CCCC
298 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
299
300 // 59 IPUT vA, vB, field@CCCC
301 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
302
303 // 5A IPUT_WIDE vA, vB, field@CCCC
304 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
305
306 // 5B IPUT_OBJECT vA, vB, field@CCCC
307 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
308
309 // 5C IPUT_BOOLEAN vA, vB, field@CCCC
310 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
311
312 // 5D IPUT_BYTE vA, vB, field@CCCC
313 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
314
315 // 5E IPUT_CHAR vA, vB, field@CCCC
316 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
317
318 // 5F IPUT_SHORT vA, vB, field@CCCC
319 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
320
321 // 60 SGET vAA, field@BBBB
322 DF_DA | DF_UMS,
323
324 // 61 SGET_WIDE vAA, field@BBBB
325 DF_DA | DF_A_WIDE | DF_UMS,
326
327 // 62 SGET_OBJECT vAA, field@BBBB
328 DF_DA | DF_REF_A | DF_UMS,
329
330 // 63 SGET_BOOLEAN vAA, field@BBBB
331 DF_DA | DF_UMS,
332
333 // 64 SGET_BYTE vAA, field@BBBB
334 DF_DA | DF_UMS,
335
336 // 65 SGET_CHAR vAA, field@BBBB
337 DF_DA | DF_UMS,
338
339 // 66 SGET_SHORT vAA, field@BBBB
340 DF_DA | DF_UMS,
341
342 // 67 SPUT vAA, field@BBBB
343 DF_UA | DF_UMS,
344
345 // 68 SPUT_WIDE vAA, field@BBBB
346 DF_UA | DF_A_WIDE | DF_UMS,
347
348 // 69 SPUT_OBJECT vAA, field@BBBB
349 DF_UA | DF_REF_A | DF_UMS,
350
351 // 6A SPUT_BOOLEAN vAA, field@BBBB
352 DF_UA | DF_UMS,
353
354 // 6B SPUT_BYTE vAA, field@BBBB
355 DF_UA | DF_UMS,
356
357 // 6C SPUT_CHAR vAA, field@BBBB
358 DF_UA | DF_UMS,
359
360 // 6D SPUT_SHORT vAA, field@BBBB
361 DF_UA | DF_UMS,
362
363 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
364 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
365
366 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
367 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
368
369 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
370 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
371
372 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
373 DF_FORMAT_35C | DF_UMS,
374
375 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
376 DF_FORMAT_35C | DF_UMS,
377
378 // 73 UNUSED_73
379 DF_NOP,
380
381 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
382 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
383
384 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
385 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
386
387 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
388 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
389
390 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
391 DF_FORMAT_3RC | DF_UMS,
392
393 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
394 DF_FORMAT_3RC | DF_UMS,
395
396 // 79 UNUSED_79
397 DF_NOP,
398
399 // 7A UNUSED_7A
400 DF_NOP,
401
402 // 7B NEG_INT vA, vB
403 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
404
405 // 7C NOT_INT vA, vB
406 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
407
408 // 7D NEG_LONG vA, vB
409 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
410
411 // 7E NOT_LONG vA, vB
412 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
413
414 // 7F NEG_FLOAT vA, vB
415 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
416
417 // 80 NEG_DOUBLE vA, vB
418 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
419
420 // 81 INT_TO_LONG vA, vB
421 DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
422
423 // 82 INT_TO_FLOAT vA, vB
424 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
425
426 // 83 INT_TO_DOUBLE vA, vB
427 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
428
429 // 84 LONG_TO_INT vA, vB
430 DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
431
432 // 85 LONG_TO_FLOAT vA, vB
433 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
434
435 // 86 LONG_TO_DOUBLE vA, vB
436 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
437
438 // 87 FLOAT_TO_INT vA, vB
439 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
440
441 // 88 FLOAT_TO_LONG vA, vB
442 DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
443
444 // 89 FLOAT_TO_DOUBLE vA, vB
445 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B,
446
447 // 8A DOUBLE_TO_INT vA, vB
448 DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
449
450 // 8B DOUBLE_TO_LONG vA, vB
451 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
452
453 // 8C DOUBLE_TO_FLOAT vA, vB
454 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
455
456 // 8D INT_TO_BYTE vA, vB
457 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
458
459 // 8E INT_TO_CHAR vA, vB
460 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
461
462 // 8F INT_TO_SHORT vA, vB
463 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
464
465 // 90 ADD_INT vAA, vBB, vCC
466 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
467
468 // 91 SUB_INT vAA, vBB, vCC
469 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
470
471 // 92 MUL_INT vAA, vBB, vCC
472 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
473
474 // 93 DIV_INT vAA, vBB, vCC
475 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
476
477 // 94 REM_INT vAA, vBB, vCC
478 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
479
480 // 95 AND_INT vAA, vBB, vCC
481 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
482
483 // 96 OR_INT vAA, vBB, vCC
484 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
485
486 // 97 XOR_INT vAA, vBB, vCC
487 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
488
489 // 98 SHL_INT vAA, vBB, vCC
490 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
491
492 // 99 SHR_INT vAA, vBB, vCC
493 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
494
495 // 9A USHR_INT vAA, vBB, vCC
496 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
497
498 // 9B ADD_LONG vAA, vBB, vCC
499 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
500
501 // 9C SUB_LONG vAA, vBB, vCC
502 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
503
504 // 9D MUL_LONG vAA, vBB, vCC
505 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
506
507 // 9E DIV_LONG vAA, vBB, vCC
508 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
509
510 // 9F REM_LONG vAA, vBB, vCC
511 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
512
513 // A0 AND_LONG vAA, vBB, vCC
514 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
515
516 // A1 OR_LONG vAA, vBB, vCC
517 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
518
519 // A2 XOR_LONG vAA, vBB, vCC
520 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
521
522 // A3 SHL_LONG vAA, vBB, vCC
523 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
524
525 // A4 SHR_LONG vAA, vBB, vCC
526 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
527
528 // A5 USHR_LONG vAA, vBB, vCC
529 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
530
531 // A6 ADD_FLOAT vAA, vBB, vCC
532 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
533
534 // A7 SUB_FLOAT vAA, vBB, vCC
535 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
536
537 // A8 MUL_FLOAT vAA, vBB, vCC
538 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
539
540 // A9 DIV_FLOAT vAA, vBB, vCC
541 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
542
543 // AA REM_FLOAT vAA, vBB, vCC
544 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
545
546 // AB ADD_DOUBLE vAA, vBB, vCC
547 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
548
549 // AC SUB_DOUBLE vAA, vBB, vCC
550 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
551
552 // AD MUL_DOUBLE vAA, vBB, vCC
553 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
554
555 // AE DIV_DOUBLE vAA, vBB, vCC
556 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
557
558 // AF REM_DOUBLE vAA, vBB, vCC
559 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
560
561 // B0 ADD_INT_2ADDR vA, vB
562 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
563
564 // B1 SUB_INT_2ADDR vA, vB
565 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
566
567 // B2 MUL_INT_2ADDR vA, vB
568 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
569
570 // B3 DIV_INT_2ADDR vA, vB
571 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
572
573 // B4 REM_INT_2ADDR vA, vB
574 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
575
576 // B5 AND_INT_2ADDR vA, vB
577 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
578
579 // B6 OR_INT_2ADDR vA, vB
580 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
581
582 // B7 XOR_INT_2ADDR vA, vB
583 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
584
585 // B8 SHL_INT_2ADDR vA, vB
586 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
587
588 // B9 SHR_INT_2ADDR vA, vB
589 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
590
591 // BA USHR_INT_2ADDR vA, vB
592 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
593
594 // BB ADD_LONG_2ADDR vA, vB
595 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
596
597 // BC SUB_LONG_2ADDR vA, vB
598 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
599
600 // BD MUL_LONG_2ADDR vA, vB
601 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
602
603 // BE DIV_LONG_2ADDR vA, vB
604 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
605
606 // BF REM_LONG_2ADDR vA, vB
607 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
608
609 // C0 AND_LONG_2ADDR vA, vB
610 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
611
612 // C1 OR_LONG_2ADDR vA, vB
613 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
614
615 // C2 XOR_LONG_2ADDR vA, vB
616 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
617
618 // C3 SHL_LONG_2ADDR vA, vB
619 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
620
621 // C4 SHR_LONG_2ADDR vA, vB
622 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
623
624 // C5 USHR_LONG_2ADDR vA, vB
625 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
626
627 // C6 ADD_FLOAT_2ADDR vA, vB
628 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
629
630 // C7 SUB_FLOAT_2ADDR vA, vB
631 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
632
633 // C8 MUL_FLOAT_2ADDR vA, vB
634 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
635
636 // C9 DIV_FLOAT_2ADDR vA, vB
637 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
638
639 // CA REM_FLOAT_2ADDR vA, vB
640 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
641
642 // CB ADD_DOUBLE_2ADDR vA, vB
643 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
644
645 // CC SUB_DOUBLE_2ADDR vA, vB
646 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
647
648 // CD MUL_DOUBLE_2ADDR vA, vB
649 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
650
651 // CE DIV_DOUBLE_2ADDR vA, vB
652 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
653
654 // CF REM_DOUBLE_2ADDR vA, vB
655 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
656
657 // D0 ADD_INT_LIT16 vA, vB, #+CCCC
658 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
659
660 // D1 RSUB_INT vA, vB, #+CCCC
661 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
662
663 // D2 MUL_INT_LIT16 vA, vB, #+CCCC
664 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
665
666 // D3 DIV_INT_LIT16 vA, vB, #+CCCC
667 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
668
669 // D4 REM_INT_LIT16 vA, vB, #+CCCC
670 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
671
672 // D5 AND_INT_LIT16 vA, vB, #+CCCC
673 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
674
675 // D6 OR_INT_LIT16 vA, vB, #+CCCC
676 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
677
678 // D7 XOR_INT_LIT16 vA, vB, #+CCCC
679 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
680
681 // D8 ADD_INT_LIT8 vAA, vBB, #+CC
682 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
683
684 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
685 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
686
687 // DA MUL_INT_LIT8 vAA, vBB, #+CC
688 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
689
690 // DB DIV_INT_LIT8 vAA, vBB, #+CC
691 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
692
693 // DC REM_INT_LIT8 vAA, vBB, #+CC
694 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
695
696 // DD AND_INT_LIT8 vAA, vBB, #+CC
697 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
698
699 // DE OR_INT_LIT8 vAA, vBB, #+CC
700 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
701
702 // DF XOR_INT_LIT8 vAA, vBB, #+CC
703 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
704
705 // E0 SHL_INT_LIT8 vAA, vBB, #+CC
706 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
707
708 // E1 SHR_INT_LIT8 vAA, vBB, #+CC
709 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
710
711 // E2 USHR_INT_LIT8 vAA, vBB, #+CC
712 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
713
714 // E3 IGET_VOLATILE
715 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
716
717 // E4 IPUT_VOLATILE
718 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B,
719
720 // E5 SGET_VOLATILE
721 DF_DA | DF_UMS,
722
723 // E6 SPUT_VOLATILE
724 DF_UA | DF_UMS,
725
726 // E7 IGET_OBJECT_VOLATILE
727 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B,
728
729 // E8 IGET_WIDE_VOLATILE
730 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B,
731
732 // E9 IPUT_WIDE_VOLATILE
733 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B,
734
735 // EA SGET_WIDE_VOLATILE
736 DF_DA | DF_A_WIDE | DF_UMS,
737
738 // EB SPUT_WIDE_VOLATILE
739 DF_UA | DF_A_WIDE | DF_UMS,
740
741 // EC BREAKPOINT
742 DF_NOP,
743
744 // ED THROW_VERIFICATION_ERROR
745 DF_NOP | DF_UMS,
746
747 // EE EXECUTE_INLINE
748 DF_FORMAT_35C,
749
750 // EF EXECUTE_INLINE_RANGE
751 DF_FORMAT_3RC,
752
753 // F0 INVOKE_OBJECT_INIT_RANGE
754 DF_NOP | DF_NULL_CHK_0,
755
756 // F1 RETURN_VOID_BARRIER
757 DF_NOP,
758
759 // F2 IGET_QUICK
760 DF_DA | DF_UB | DF_NULL_CHK_0,
761
762 // F3 IGET_WIDE_QUICK
763 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0,
764
765 // F4 IGET_OBJECT_QUICK
766 DF_DA | DF_UB | DF_NULL_CHK_0,
767
768 // F5 IPUT_QUICK
769 DF_UA | DF_UB | DF_NULL_CHK_1,
770
771 // F6 IPUT_WIDE_QUICK
772 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2,
773
774 // F7 IPUT_OBJECT_QUICK
775 DF_UA | DF_UB | DF_NULL_CHK_1,
776
777 // F8 INVOKE_VIRTUAL_QUICK
778 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
779
780 // F9 INVOKE_VIRTUAL_QUICK_RANGE
781 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
782
783 // FA INVOKE_SUPER_QUICK
784 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
785
786 // FB INVOKE_SUPER_QUICK_RANGE
787 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
788
789 // FC IPUT_OBJECT_VOLATILE
790 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B,
791
792 // FD SGET_OBJECT_VOLATILE
793 DF_DA | DF_REF_A | DF_UMS,
794
795 // FE SPUT_OBJECT_VOLATILE
796 DF_UA | DF_REF_A | DF_UMS,
797
798 // FF UNUSED_FF
799 DF_NOP,
800
801 // Beginning of extended MIR opcodes
802 // 100 MIR_PHI
803 DF_DA | DF_NULL_TRANSFER_N,
804
805 // 101 MIR_COPY
806 DF_DA | DF_UB | DF_IS_MOVE,
807
808 // 102 MIR_FUSED_CMPL_FLOAT
809 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
810
811 // 103 MIR_FUSED_CMPG_FLOAT
812 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
813
814 // 104 MIR_FUSED_CMPL_DOUBLE
815 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
816
817 // 105 MIR_FUSED_CMPG_DOUBLE
818 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
819
820 // 106 MIR_FUSED_CMP_LONG
821 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
822
823 // 107 MIR_NOP
824 DF_NOP,
825
826 // 108 MIR_NULL_CHECK
827 0,
828
829 // 109 MIR_RANGE_CHECK
830 0,
831
832 // 110 MIR_DIV_ZERO_CHECK
833 0,
834
835 // 111 MIR_CHECK
836 0,
837
838 // 112 MIR_CHECKPART2
839 0,
840
841 // 113 MIR_SELECT
842 DF_DA | DF_UB,
843};
844
845/* Return the base virtual register for a SSA name */
846int MIRGraph::SRegToVReg(int ssa_reg)
847{
848 DCHECK_LT(ssa_reg, static_cast<int>(ssa_base_vregs_->num_used));
849 return GET_ELEM_N(ssa_base_vregs_, int, ssa_reg);
850}
851
852/* Any register that is used before being defined is considered live-in */
853void MIRGraph::HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
854 ArenaBitVector* live_in_v, int dalvik_reg_id)
855{
856 SetBit(cu_, use_v, dalvik_reg_id);
857 if (!IsBitSet(def_v, dalvik_reg_id)) {
858 SetBit(cu_, live_in_v, dalvik_reg_id);
859 }
860}
861
862/* Mark a reg as being defined */
863void MIRGraph::HandleDef(ArenaBitVector* def_v, int dalvik_reg_id)
864{
865 SetBit(cu_, def_v, dalvik_reg_id);
866}
867
868/*
869 * Find out live-in variables for natural loops. Variables that are live-in in
870 * the main loop body are considered to be defined in the entry block.
871 */
872bool MIRGraph::FindLocalLiveIn(BasicBlock* bb)
873{
874 MIR* mir;
875 ArenaBitVector *use_v, *def_v, *live_in_v;
876
877 if (bb->data_flow_info == NULL) return false;
878
879 use_v = bb->data_flow_info->use_v =
880 AllocBitVector(cu_, cu_->num_dalvik_registers, false, kBitMapUse);
881 def_v = bb->data_flow_info->def_v =
882 AllocBitVector(cu_, cu_->num_dalvik_registers, false, kBitMapDef);
883 live_in_v = bb->data_flow_info->live_in_v =
884 AllocBitVector(cu_, cu_->num_dalvik_registers, false, kBitMapLiveIn);
885
886 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
887 int df_attributes = oat_data_flow_attributes[mir->dalvikInsn.opcode];
888 DecodedInstruction *d_insn = &mir->dalvikInsn;
889
890 if (df_attributes & DF_HAS_USES) {
891 if (df_attributes & DF_UA) {
892 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA);
893 if (df_attributes & DF_A_WIDE) {
894 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA+1);
895 }
896 }
897 if (df_attributes & DF_UB) {
898 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB);
899 if (df_attributes & DF_B_WIDE) {
900 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB+1);
901 }
902 }
903 if (df_attributes & DF_UC) {
904 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC);
905 if (df_attributes & DF_C_WIDE) {
906 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+1);
907 }
908 }
909 }
910 if (df_attributes & DF_FORMAT_35C) {
911 for (unsigned int i = 0; i < d_insn->vA; i++) {
912 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->arg[i]);
913 }
914 }
915 if (df_attributes & DF_FORMAT_3RC) {
916 for (unsigned int i = 0; i < d_insn->vA; i++) {
917 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+i);
918 }
919 }
920 if (df_attributes & DF_HAS_DEFS) {
921 HandleDef(def_v, d_insn->vA);
922 if (df_attributes & DF_A_WIDE) {
923 HandleDef(def_v, d_insn->vA+1);
924 }
925 }
926 }
927 return true;
928}
929
930int MIRGraph::AddNewSReg(int v_reg)
931{
932 // Compiler temps always have a subscript of 0
933 int subscript = (v_reg < 0) ? 0 : ++ssa_last_defs_[v_reg];
934 int ssa_reg = GetNumSSARegs();
935 SetNumSSARegs(ssa_reg + 1);
936 InsertGrowableList(cu_, ssa_base_vregs_, v_reg);
937 InsertGrowableList(cu_, ssa_subscripts_, subscript);
938 std::string ssa_name = GetSSAName(cu_, ssa_reg);
939 char* name = static_cast<char*>(NewMem(cu_, ssa_name.length() + 1, false, kAllocDFInfo));
940 strncpy(name, ssa_name.c_str(), ssa_name.length() + 1);
941 InsertGrowableList(cu_, ssa_strings_, reinterpret_cast<uintptr_t>(name));
942 DCHECK_EQ(ssa_base_vregs_->num_used, ssa_subscripts_->num_used);
943 return ssa_reg;
944}
945
946/* Find out the latest SSA register for a given Dalvik register */
947void MIRGraph::HandleSSAUse(int* uses, int dalvik_reg, int reg_index)
948{
949 DCHECK((dalvik_reg >= 0) && (dalvik_reg < cu_->num_dalvik_registers));
950 uses[reg_index] = vreg_to_ssa_map_[dalvik_reg];
951}
952
953/* Setup a new SSA register for a given Dalvik register */
954void MIRGraph::HandleSSADef(int* defs, int dalvik_reg, int reg_index)
955{
956 DCHECK((dalvik_reg >= 0) && (dalvik_reg < cu_->num_dalvik_registers));
957 int ssa_reg = AddNewSReg(dalvik_reg);
958 vreg_to_ssa_map_[dalvik_reg] = ssa_reg;
959 defs[reg_index] = ssa_reg;
960}
961
962/* Look up new SSA names for format_35c instructions */
963void MIRGraph::DataFlowSSAFormat35C(MIR* mir)
964{
965 DecodedInstruction *d_insn = &mir->dalvikInsn;
966 int num_uses = d_insn->vA;
967 int i;
968
969 mir->ssa_rep->num_uses = num_uses;
970 mir->ssa_rep->uses = static_cast<int*>(NewMem(cu_, sizeof(int) * num_uses, true, kAllocDFInfo));
971 // NOTE: will be filled in during type & size inference pass
972 mir->ssa_rep->fp_use = static_cast<bool*>(NewMem(cu_, sizeof(bool) * num_uses, true,
973 kAllocDFInfo));
974
975 for (i = 0; i < num_uses; i++) {
976 HandleSSAUse(mir->ssa_rep->uses, d_insn->arg[i], i);
977 }
978}
979
980/* Look up new SSA names for format_3rc instructions */
981void MIRGraph::DataFlowSSAFormat3RC(MIR* mir)
982{
983 DecodedInstruction *d_insn = &mir->dalvikInsn;
984 int num_uses = d_insn->vA;
985 int i;
986
987 mir->ssa_rep->num_uses = num_uses;
988 mir->ssa_rep->uses = static_cast<int*>(NewMem(cu_, sizeof(int) * num_uses, true, kAllocDFInfo));
989 // NOTE: will be filled in during type & size inference pass
990 mir->ssa_rep->fp_use = static_cast<bool*>(NewMem(cu_, sizeof(bool) * num_uses, true,
991 kAllocDFInfo));
992
993 for (i = 0; i < num_uses; i++) {
994 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+i, i);
995 }
996}
997
998/* Entry function to convert a block into SSA representation */
999bool MIRGraph::DoSSAConversion(BasicBlock* bb)
1000{
1001 MIR* mir;
1002
1003 if (bb->data_flow_info == NULL) return false;
1004
1005 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
1006 mir->ssa_rep = static_cast<struct SSARepresentation *>(NewMem(cu_, sizeof(SSARepresentation),
1007 true, kAllocDFInfo));
1008
1009 int df_attributes = oat_data_flow_attributes[mir->dalvikInsn.opcode];
1010
1011 // If not a pseudo-op, note non-leaf or can throw
1012 if (static_cast<int>(mir->dalvikInsn.opcode) <
1013 static_cast<int>(kNumPackedOpcodes)) {
1014 int flags = Instruction::FlagsOf(mir->dalvikInsn.opcode);
1015
1016 if (flags & Instruction::kInvoke) {
1017 cu_->attributes &= ~METHOD_IS_LEAF;
1018 }
1019 }
1020
1021 int num_uses = 0;
1022
1023 if (df_attributes & DF_FORMAT_35C) {
1024 DataFlowSSAFormat35C(mir);
1025 continue;
1026 }
1027
1028 if (df_attributes & DF_FORMAT_3RC) {
1029 DataFlowSSAFormat3RC(mir);
1030 continue;
1031 }
1032
1033 if (df_attributes & DF_HAS_USES) {
1034 if (df_attributes & DF_UA) {
1035 num_uses++;
1036 if (df_attributes & DF_A_WIDE) {
1037 num_uses ++;
1038 }
1039 }
1040 if (df_attributes & DF_UB) {
1041 num_uses++;
1042 if (df_attributes & DF_B_WIDE) {
1043 num_uses ++;
1044 }
1045 }
1046 if (df_attributes & DF_UC) {
1047 num_uses++;
1048 if (df_attributes & DF_C_WIDE) {
1049 num_uses ++;
1050 }
1051 }
1052 }
1053
1054 if (num_uses) {
1055 mir->ssa_rep->num_uses = num_uses;
1056 mir->ssa_rep->uses = static_cast<int*>(NewMem(cu_, sizeof(int) * num_uses, false,
1057 kAllocDFInfo));
1058 mir->ssa_rep->fp_use = static_cast<bool*>(NewMem(cu_, sizeof(bool) * num_uses, false,
1059 kAllocDFInfo));
1060 }
1061
1062 int num_defs = 0;
1063
1064 if (df_attributes & DF_HAS_DEFS) {
1065 num_defs++;
1066 if (df_attributes & DF_A_WIDE) {
1067 num_defs++;
1068 }
1069 }
1070
1071 if (num_defs) {
1072 mir->ssa_rep->num_defs = num_defs;
1073 mir->ssa_rep->defs = static_cast<int*>(NewMem(cu_, sizeof(int) * num_defs, false,
1074 kAllocDFInfo));
1075 mir->ssa_rep->fp_def = static_cast<bool*>(NewMem(cu_, sizeof(bool) * num_defs, false,
1076 kAllocDFInfo));
1077 }
1078
1079 DecodedInstruction *d_insn = &mir->dalvikInsn;
1080
1081 if (df_attributes & DF_HAS_USES) {
1082 num_uses = 0;
1083 if (df_attributes & DF_UA) {
1084 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_A;
1085 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA, num_uses++);
1086 if (df_attributes & DF_A_WIDE) {
1087 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_A;
1088 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA+1, num_uses++);
1089 }
1090 }
1091 if (df_attributes & DF_UB) {
1092 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_B;
1093 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB, num_uses++);
1094 if (df_attributes & DF_B_WIDE) {
1095 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_B;
1096 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB+1, num_uses++);
1097 }
1098 }
1099 if (df_attributes & DF_UC) {
1100 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_C;
1101 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC, num_uses++);
1102 if (df_attributes & DF_C_WIDE) {
1103 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_C;
1104 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+1, num_uses++);
1105 }
1106 }
1107 }
1108 if (df_attributes & DF_HAS_DEFS) {
1109 mir->ssa_rep->fp_def[0] = df_attributes & DF_FP_A;
1110 HandleSSADef(mir->ssa_rep->defs, d_insn->vA, 0);
1111 if (df_attributes & DF_A_WIDE) {
1112 mir->ssa_rep->fp_def[1] = df_attributes & DF_FP_A;
1113 HandleSSADef(mir->ssa_rep->defs, d_insn->vA+1, 1);
1114 }
1115 }
1116 }
1117
1118 if (!cu_->disable_dataflow) {
1119 /*
1120 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1121 * input to PHI nodes can be derived from the snapshot of all
1122 * predecessor blocks.
1123 */
1124 bb->data_flow_info->vreg_to_ssa_map =
1125 static_cast<int*>(NewMem(cu_, sizeof(int) * cu_->num_dalvik_registers, false,
1126 kAllocDFInfo));
1127
1128 memcpy(bb->data_flow_info->vreg_to_ssa_map, vreg_to_ssa_map_,
1129 sizeof(int) * cu_->num_dalvik_registers);
1130 }
1131 return true;
1132}
1133
1134/* Setup the basic data structures for SSA conversion */
1135void MIRGraph::CompilerInitializeSSAConversion()
1136{
1137 int i;
1138 int num_dalvik_reg = cu_->num_dalvik_registers;
1139
1140 ssa_base_vregs_ =
1141 static_cast<GrowableList*>(NewMem(cu_, sizeof(GrowableList), false, kAllocDFInfo));
1142 ssa_subscripts_ =
1143 static_cast<GrowableList*>(NewMem(cu_, sizeof(GrowableList), false, kAllocDFInfo));
1144 ssa_strings_ =
1145 static_cast<GrowableList*>(NewMem(cu_, sizeof(GrowableList), false, kAllocDFInfo));
1146 // Create the ssa mappings, estimating the max size
1147 CompilerInitGrowableList(cu_, ssa_base_vregs_, num_dalvik_reg + GetDefCount() + 128,
1148 kListSSAtoDalvikMap);
1149 CompilerInitGrowableList(cu_, ssa_subscripts_, num_dalvik_reg + GetDefCount() + 128,
1150 kListSSAtoDalvikMap);
1151 CompilerInitGrowableList(cu_, ssa_strings_, num_dalvik_reg + GetDefCount() + 128,
1152 kListSSAtoDalvikMap);
1153 /*
1154 * Initial number of SSA registers is equal to the number of Dalvik
1155 * registers.
1156 */
1157 SetNumSSARegs(num_dalvik_reg);
1158
1159 /*
1160 * Initialize the SSA2Dalvik map list. For the first num_dalvik_reg elements,
1161 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1162 * into "(0 << 16) | i"
1163 */
1164 for (i = 0; i < num_dalvik_reg; i++) {
1165 InsertGrowableList(cu_, ssa_base_vregs_, i);
1166 InsertGrowableList(cu_, ssa_subscripts_, 0);
1167 std::string ssa_name = GetSSAName(cu_, i);
1168 char* name = static_cast<char*>(NewMem(cu_, ssa_name.length() + 1, true, kAllocDFInfo));
1169 strncpy(name, ssa_name.c_str(), ssa_name.length() + 1);
1170 InsertGrowableList(cu_, ssa_strings_, reinterpret_cast<uintptr_t>(name));
1171 }
1172
1173 /*
1174 * Initialize the DalvikToSSAMap map. There is one entry for each
1175 * Dalvik register, and the SSA names for those are the same.
1176 */
1177 vreg_to_ssa_map_ =
1178 static_cast<int*>(NewMem(cu_, sizeof(int) * num_dalvik_reg, false, kAllocDFInfo));
1179 /* Keep track of the higest def for each dalvik reg */
1180 ssa_last_defs_ =
1181 static_cast<int*>(NewMem(cu_, sizeof(int) * num_dalvik_reg, false, kAllocDFInfo));
1182
1183 for (i = 0; i < num_dalvik_reg; i++) {
1184 vreg_to_ssa_map_[i] = i;
1185 ssa_last_defs_[i] = 0;
1186 }
1187
1188 /* Add ssa reg for Method* */
1189 cu_->method_sreg = AddNewSReg(SSA_METHOD_BASEREG);
1190
1191 /*
1192 * Allocate the BasicBlockDataFlow structure for the entry and code blocks
1193 */
1194 GrowableListIterator iterator = GetBasicBlockIterator();
1195
1196 while (true) {
1197 BasicBlock* bb = reinterpret_cast<BasicBlock*>(GrowableListIteratorNext(&iterator));
1198 if (bb == NULL) break;
1199 if (bb->hidden == true) continue;
1200 if (bb->block_type == kDalvikByteCode ||
1201 bb->block_type == kEntryBlock ||
1202 bb->block_type == kExitBlock) {
1203 bb->data_flow_info = static_cast<BasicBlockDataFlow*>(NewMem(cu_, sizeof(BasicBlockDataFlow),
1204 true, kAllocDFInfo));
1205 }
1206 }
1207}
1208
1209/* Clear the visited flag for each BB */
1210bool MIRGraph::ClearVisitedFlag(struct BasicBlock* bb)
1211{
1212 bb->visited = false;
1213 return true;
1214}
1215
1216/*
1217 * This function will make a best guess at whether the invoke will
1218 * end up using Method*. It isn't critical to get it exactly right,
1219 * and attempting to do would involve more complexity than it's
1220 * worth.
1221 */
1222bool MIRGraph::InvokeUsesMethodStar(MIR* mir)
1223{
1224 InvokeType type;
1225 Instruction::Code opcode = mir->dalvikInsn.opcode;
1226 switch (opcode) {
1227 case Instruction::INVOKE_STATIC:
1228 case Instruction::INVOKE_STATIC_RANGE:
1229 type = kStatic;
1230 break;
1231 case Instruction::INVOKE_DIRECT:
1232 case Instruction::INVOKE_DIRECT_RANGE:
1233 type = kDirect;
1234 break;
1235 case Instruction::INVOKE_VIRTUAL:
1236 case Instruction::INVOKE_VIRTUAL_RANGE:
1237 type = kVirtual;
1238 break;
1239 case Instruction::INVOKE_INTERFACE:
1240 case Instruction::INVOKE_INTERFACE_RANGE:
1241 return false;
1242 case Instruction::INVOKE_SUPER_RANGE:
1243 case Instruction::INVOKE_SUPER:
1244 type = kSuper;
1245 break;
1246 default:
1247 LOG(WARNING) << "Unexpected invoke op: " << opcode;
1248 return false;
1249 }
1250 DexCompilationUnit m_unit(cu_);
1251 // TODO: add a flag so we don't counts the stats for this twice
1252 uint32_t dex_method_idx = mir->dalvikInsn.vB;
1253 int vtable_idx;
1254 uintptr_t direct_code;
1255 uintptr_t direct_method;
1256 bool fast_path =
1257 cu_->compiler_driver->ComputeInvokeInfo(dex_method_idx, &m_unit, type,
1258 vtable_idx, direct_code,
1259 direct_method) &&
1260 !(cu_->enable_debug & (1 << kDebugSlowInvokePath));
1261 return (((type == kDirect) || (type == kStatic)) &&
1262 fast_path && ((direct_code == 0) || (direct_method == 0)));
1263}
1264
1265/*
1266 * Count uses, weighting by loop nesting depth. This code only
1267 * counts explicitly used s_regs. A later phase will add implicit
1268 * counts for things such as Method*, null-checked references, etc.
1269 */
1270bool MIRGraph::CountUses(struct BasicBlock* bb)
1271{
1272 if (bb->block_type != kDalvikByteCode) {
1273 return false;
1274 }
1275 for (MIR* mir = bb->first_mir_insn; (mir != NULL); mir = mir->next) {
1276 if (mir->ssa_rep == NULL) {
1277 continue;
1278 }
1279 uint32_t weight = std::min(16U, static_cast<uint32_t>(bb->nesting_depth));
1280 for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
1281 int s_reg = mir->ssa_rep->uses[i];
1282 DCHECK_LT(s_reg, static_cast<int>(use_counts_.num_used));
1283 raw_use_counts_.elem_list[s_reg]++;
1284 use_counts_.elem_list[s_reg] += (1 << weight);
1285 }
1286 if (!(cu_->disable_opt & (1 << kPromoteCompilerTemps))) {
1287 int df_attributes = oat_data_flow_attributes[mir->dalvikInsn.opcode];
1288 // Implicit use of Method* ? */
1289 if (df_attributes & DF_UMS) {
1290 /*
1291 * Some invokes will not use Method* - need to perform test similar
1292 * to that found in GenInvoke() to decide whether to count refs
1293 * for Method* on invoke-class opcodes.
1294 * TODO: refactor for common test here, save results for GenInvoke
1295 */
1296 int uses_method_star = true;
1297 if ((df_attributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) &&
1298 !(df_attributes & DF_NON_NULL_RET)) {
1299 uses_method_star &= InvokeUsesMethodStar(mir);
1300 }
1301 if (uses_method_star) {
1302 raw_use_counts_.elem_list[cu_->method_sreg]++;
1303 use_counts_.elem_list[cu_->method_sreg] += (1 << weight);
1304 }
1305 }
1306 }
1307 }
1308 return false;
1309}
1310
1311void MIRGraph::MethodUseCount()
1312{
1313 int num_ssa_regs = GetNumSSARegs();
1314 CompilerInitGrowableList(cu_, &use_counts_, num_ssa_regs + 32, kListMisc);
1315 CompilerInitGrowableList(cu_, &raw_use_counts_, num_ssa_regs + 32, kListMisc);
1316 // Initialize list
1317 for (int i = 0; i < num_ssa_regs; i++) {
1318 InsertGrowableList(cu_, &use_counts_, 0);
1319 InsertGrowableList(cu_, &raw_use_counts_, 0);
1320 }
1321 if (cu_->disable_opt & (1 << kPromoteRegs)) {
1322 return;
1323 }
1324 DataflowIterator iter(this, kAllNodes, false /* not iterative */);
1325 for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) {
1326 CountUses(bb);
1327 }
1328}
1329
1330/* Verify if all the successor is connected with all the claimed predecessors */
1331bool MIRGraph::VerifyPredInfo(BasicBlock* bb)
1332{
1333 GrowableListIterator iter;
1334
1335 GrowableListIteratorInit(bb->predecessors, &iter);
1336 while (true) {
1337 BasicBlock *pred_bb = reinterpret_cast<BasicBlock*>(GrowableListIteratorNext(&iter));
1338 if (!pred_bb) break;
1339 bool found = false;
1340 if (pred_bb->taken == bb) {
1341 found = true;
1342 } else if (pred_bb->fall_through == bb) {
1343 found = true;
1344 } else if (pred_bb->successor_block_list.block_list_type != kNotUsed) {
1345 GrowableListIterator iterator;
1346 GrowableListIteratorInit(&pred_bb->successor_block_list.blocks,
1347 &iterator);
1348 while (true) {
1349 SuccessorBlockInfo *successor_block_info =
1350 reinterpret_cast<SuccessorBlockInfo*>(GrowableListIteratorNext(&iterator));
1351 if (successor_block_info == NULL) break;
1352 BasicBlock *succ_bb = successor_block_info->block;
1353 if (succ_bb == bb) {
1354 found = true;
1355 break;
1356 }
1357 }
1358 }
1359 if (found == false) {
1360 char block_name1[BLOCK_NAME_LEN], block_name2[BLOCK_NAME_LEN];
1361 GetBlockName(bb, block_name1);
1362 GetBlockName(pred_bb, block_name2);
1363 DumpCFG("/sdcard/cfg/", false);
1364 LOG(FATAL) << "Successor " << block_name1 << "not found from "
1365 << block_name2;
1366 }
1367 }
1368 return true;
1369}
1370
1371void MIRGraph::VerifyDataflow()
1372{
1373 /* Verify if all blocks are connected as claimed */
1374 DataflowIterator iter(this, kAllNodes, false /* not iterative */);
1375 for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) {
1376 VerifyPredInfo(bb);
1377 }
1378}
1379
1380} // namespace art