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review.blissroms.org / platform_art / 60e10c8564f47de0b7f29b26d040c591d5a396b5 / . / runtime / interpreter / mterp / out / mterp_mips.S
blob: 7ae1ab110db6e7286b249713dbb0cea24a1a285c [file] [log] [blame]
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]1/*
2 * This file was generated automatically by gen-mterp.py for 'mips'.
3 *
4 * --> DO NOT EDIT <--
5 */
6
7/* File: mips/header.S */
8/*
9 * Copyright (C) 2016 The Android Open Source Project
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 */
23
24/*
25 Art assembly interpreter notes:
26
27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't
28 handle invoke, allows higher-level code to create frame & shadow frame.
29
30 Once that's working, support direct entry code & eliminate shadow frame (and
31 excess locals allocation.
32
33 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the
34 base of the vreg array within the shadow frame. Access the other fields,
35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue
36 the shadow frame mechanism of double-storing object references - via rFP &
37 number_of_vregs_.
38
39 */
40
41#include "asm_support.h"
42
43#if (__mips==32) && (__mips_isa_rev>=2)
44#define MIPS32REVGE2 /* mips32r2 and greater */
45#if (__mips==32) && (__mips_isa_rev>=5)
46#define FPU64 /* 64 bit FPU */
47#if (__mips==32) && (__mips_isa_rev>=6)
48#define MIPS32REVGE6 /* mips32r6 and greater */
49#endif
50#endif
51#endif
52
53/* MIPS definitions and declarations
54
55 reg nick purpose
56 s0 rPC interpreted program counter, used for fetching instructions
57 s1 rFP interpreted frame pointer, used for accessing locals and args
58 s2 rSELF self (Thread) pointer
59 s3 rIBASE interpreted instruction base pointer, used for computed goto
60 s4 rINST first 16-bit code unit of current instruction
61 s6 rREFS base of object references in shadow frame (ideally, we'll get rid of this later).
62*/
63
64/* single-purpose registers, given names for clarity */
65#define rPC s0
66#define rFP s1
67#define rSELF s2
68#define rIBASE s3
69#define rINST s4
70#define rOBJ s5
71#define rREFS s6
72#define rTEMP s7
73
74#define rARG0 a0
75#define rARG1 a1
76#define rARG2 a2
77#define rARG3 a3
78#define rRESULT0 v0
79#define rRESULT1 v1
80
81/* GP register definitions */
82#define zero $0 /* always zero */
83#define AT $at /* assembler temp */
84#define v0 $2 /* return value */
85#define v1 $3
86#define a0 $4 /* argument registers */
87#define a1 $5
88#define a2 $6
89#define a3 $7
90#define t0 $8 /* temp registers (not saved across subroutine calls) */
91#define t1 $9
92#define t2 $10
93#define t3 $11
94#define t4 $12
95#define t5 $13
96#define t6 $14
97#define t7 $15
98#define ta0 $12 /* alias */
99#define ta1 $13
100#define ta2 $14
101#define ta3 $15
102#define s0 $16 /* saved across subroutine calls (callee saved) */
103#define s1 $17
104#define s2 $18
105#define s3 $19
106#define s4 $20
107#define s5 $21
108#define s6 $22
109#define s7 $23
110#define t8 $24 /* two more temp registers */
111#define t9 $25
112#define k0 $26 /* kernel temporary */
113#define k1 $27
114#define gp $28 /* global pointer */
115#define sp $29 /* stack pointer */
116#define s8 $30 /* one more callee saved */
117#define ra $31 /* return address */
118
119/* FP register definitions */
120#define fv0 $f0
121#define fv0f $f1
122#define fv1 $f2
123#define fv1f $f3
124#define fa0 $f12
125#define fa0f $f13
126#define fa1 $f14
127#define fa1f $f15
128#define ft0 $f4
129#define ft0f $f5
130#define ft1 $f6
131#define ft1f $f7
132#define ft2 $f8
133#define ft2f $f9
134#define ft3 $f10
135#define ft3f $f11
136#define ft4 $f16
137#define ft4f $f17
138#define ft5 $f18
139#define ft5f $f19
140#define fs0 $f20
141#define fs0f $f21
142#define fs1 $f22
143#define fs1f $f23
144#define fs2 $f24
145#define fs2f $f25
146#define fs3 $f26
147#define fs3f $f27
148#define fs4 $f28
149#define fs4f $f29
150#define fs5 $f30
151#define fs5f $f31
152
153#ifndef MIPS32REVGE6
154#define fcc0 $fcc0
155#define fcc1 $fcc1
156#endif
157
158/*
159 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So,
160 * to access other shadow frame fields, we need to use a backwards offset. Define those here.
161 */
162#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
163#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
164#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
165#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
166#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
167#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
168#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
169#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
170#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET)
171
172#define MTERP_PROFILE_BRANCHES 1
173#define MTERP_LOGGING 0
174
175/*
176 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must
177 * be done *before* something throws.
178 *
179 * It's okay to do this more than once.
180 *
181 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
182 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction
183 * offset into the code_items_[] array. For effiency, we will "export" the
184 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
185 * to convert to a dex pc when needed.
186 */
187#define EXPORT_PC() \
188 sw rPC, OFF_FP_DEX_PC_PTR(rFP)
189
190#define EXPORT_DEX_PC(tmp) \
191 lw tmp, OFF_FP_CODE_ITEM(rFP) \
192 sw rPC, OFF_FP_DEX_PC_PTR(rFP) \
193 addu tmp, CODEITEM_INSNS_OFFSET \
194 subu tmp, rPC, tmp \
195 sra tmp, tmp, 1 \
196 sw tmp, OFF_FP_DEX_PC(rFP)
197
198/*
199 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
200 */
201#define FETCH_INST() lhu rINST, (rPC)
202
203/*
204 * Fetch the next instruction from the specified offset. Advances rPC
205 * to point to the next instruction. "_count" is in 16-bit code units.
206 *
207 * This must come AFTER anything that can throw an exception, or the
208 * exception catch may miss. (This also implies that it must come after
209 * EXPORT_PC().)
210 */
211#define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \
212 addu rPC, rPC, ((_count) * 2)
213
214/*
215 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
216 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
217 */
218#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
219 lhu _dreg, ((_count)*2)(_sreg) ; \
220 addu _sreg, _sreg, (_count)*2
221
222/*
223 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load
224 * rINST ahead of possible exception point. Be sure to manually advance rPC
225 * later.
226 */
227#define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC)
228
229/* Advance rPC by some number of code units. */
230#define ADVANCE(_count) addu rPC, rPC, ((_count) * 2)
231
232/*
233 * Fetch the next instruction from an offset specified by rd. Updates
234 * rPC to point to the next instruction. "rd" must specify the distance
235 * in bytes, *not* 16-bit code units, and may be a signed value.
236 */
237#define FETCH_ADVANCE_INST_RB(rd) addu rPC, rPC, rd; \
238 lhu rINST, (rPC)
239
240/*
241 * Fetch a half-word code unit from an offset past the current PC. The
242 * "_count" value is in 16-bit code units. Does not advance rPC.
243 *
244 * The "_S" variant works the same but treats the value as signed.
245 */
246#define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC)
247#define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC)
248
249/*
250 * Fetch one byte from an offset past the current PC. Pass in the same
251 * "_count" as you would for FETCH, and an additional 0/1 indicating which
252 * byte of the halfword you want (lo/hi).
253 */
254#define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC)
255
256/*
257 * Put the instruction's opcode field into the specified register.
258 */
259#define GET_INST_OPCODE(rd) and rd, rINST, 0xFF
260
261/*
262 * Put the prefetched instruction's opcode field into the specified register.
263 */
264#define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255
265
266/*
267 * Begin executing the opcode in rd.
268 */
269#define GOTO_OPCODE(rd) sll rd, rd, 7; \
270 addu rd, rIBASE, rd; \
271 jalr zero, rd
272
273#define GOTO_OPCODE_BASE(_base, rd) sll rd, rd, 7; \
274 addu rd, _base, rd; \
275 jalr zero, rd
276
277/*
278 * Get/set the 32-bit value from a Dalvik register.
279 */
280#define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix)
281
282#define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \
283 .set noat; l.s rd, (AT); .set at
284
285#define SET_VREG(rd, rix) .set noat; \
286 sll AT, rix, 2; \
287 addu t8, rFP, AT; \
288 sw rd, 0(t8); \
289 addu t8, rREFS, AT; \
290 .set at; \
291 sw zero, 0(t8)
292
293#define SET_VREG64(rlo, rhi, rix) .set noat; \
294 sll AT, rix, 2; \
295 addu t8, rFP, AT; \
296 sw rlo, 0(t8); \
297 sw rhi, 4(t8); \
298 addu t8, rREFS, AT; \
299 .set at; \
300 sw zero, 0(t8); \
301 sw zero, 4(t8)
302
303#ifdef FPU64
304#define SET_VREG64_F(rlo, rhi, rix) .set noat; \
305 sll AT, rix, 2; \
306 addu t8, rREFS, AT; \
307 sw zero, 0(t8); \
308 sw zero, 4(t8); \
309 addu t8, rFP, AT; \
310 mfhc1 AT, rlo; \
311 sw AT, 4(t8); \
312 .set at; \
313 s.s rlo, 0(t8)
314#else
315#define SET_VREG64_F(rlo, rhi, rix) .set noat; \
316 sll AT, rix, 2; \
317 addu t8, rFP, AT; \
318 s.s rlo, 0(t8); \
319 s.s rhi, 4(t8); \
320 addu t8, rREFS, AT; \
321 .set at; \
322 sw zero, 0(t8); \
323 sw zero, 4(t8)
324#endif
325
326#define SET_VREG_OBJECT(rd, rix) .set noat; \
327 sll AT, rix, 2; \
328 addu t8, rFP, AT; \
329 sw rd, 0(t8); \
330 addu t8, rREFS, AT; \
331 .set at; \
332 sw rd, 0(t8)
333
334/* Combination of the SET_VREG and GOTO_OPCODE functions to save 1 instruction */
335#define SET_VREG_GOTO(rd, rix, dst) .set noreorder; \
336 sll dst, dst, 7; \
337 addu dst, rIBASE, dst; \
338 .set noat; \
339 sll AT, rix, 2; \
340 addu t8, rFP, AT; \
341 sw rd, 0(t8); \
342 addu t8, rREFS, AT; \
343 .set at; \
344 jalr zero, dst; \
345 sw zero, 0(t8); \
346 .set reorder
347
348/* Combination of the SET_VREG64 and GOTO_OPCODE functions to save 1 instruction */
349#define SET_VREG64_GOTO(rlo, rhi, rix, dst) .set noreorder; \
350 sll dst, dst, 7; \
351 addu dst, rIBASE, dst; \
352 .set noat; \
353 sll AT, rix, 2; \
354 addu t8, rFP, AT; \
355 sw rlo, 0(t8); \
356 sw rhi, 4(t8); \
357 addu t8, rREFS, AT; \
358 .set at; \
359 sw zero, 0(t8); \
360 jalr zero, dst; \
361 sw zero, 4(t8); \
362 .set reorder
363
364#define SET_VREG_F(rd, rix) .set noat; \
365 sll AT, rix, 2; \
366 addu t8, rFP, AT; \
367 s.s rd, 0(t8); \
368 addu t8, rREFS, AT; \
369 .set at; \
370 sw zero, 0(t8)
371
372#define GET_OPA(rd) srl rd, rINST, 8
373#ifdef MIPS32REVGE2
374#define GET_OPA4(rd) ext rd, rINST, 8, 4
375#else
376#define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf
377#endif
378#define GET_OPB(rd) srl rd, rINST, 12
379
380/*
381 * Form an Effective Address rd = rbase + roff<<n;
382 * Uses reg AT
383 */
384#define EASN(rd, rbase, roff, rshift) .set noat; \
385 sll AT, roff, rshift; \
386 addu rd, rbase, AT; \
387 .set at
388
389#define EAS1(rd, rbase, roff) EASN(rd, rbase, roff, 1)
390#define EAS2(rd, rbase, roff) EASN(rd, rbase, roff, 2)
391#define EAS3(rd, rbase, roff) EASN(rd, rbase, roff, 3)
392#define EAS4(rd, rbase, roff) EASN(rd, rbase, roff, 4)
393
394/*
395 * Form an Effective Shift Right rd = rbase + roff>>n;
396 * Uses reg AT
397 */
398#define ESRN(rd, rbase, roff, rshift) .set noat; \
399 srl AT, roff, rshift; \
400 addu rd, rbase, AT; \
401 .set at
402
403#define LOAD_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \
404 .set noat; lw rd, 0(AT); .set at
405
406#define STORE_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \
407 .set noat; sw rd, 0(AT); .set at
408
409#define LOAD_RB_OFF(rd, rbase, off) lw rd, off(rbase)
410#define STORE_RB_OFF(rd, rbase, off) sw rd, off(rbase)
411
412#define STORE64_off(rlo, rhi, rbase, off) sw rlo, off(rbase); \
413 sw rhi, (off+4)(rbase)
414#define LOAD64_off(rlo, rhi, rbase, off) lw rlo, off(rbase); \
415 lw rhi, (off+4)(rbase)
416
417#define STORE64(rlo, rhi, rbase) STORE64_off(rlo, rhi, rbase, 0)
418#define LOAD64(rlo, rhi, rbase) LOAD64_off(rlo, rhi, rbase, 0)
419
420#ifdef FPU64
421#define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, off(rbase); \
422 .set noat; \
423 mfhc1 AT, rlo; \
424 sw AT, (off+4)(rbase); \
425 .set at
426#define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, off(rbase); \
427 .set noat; \
428 lw AT, (off+4)(rbase); \
429 mthc1 AT, rlo; \
430 .set at
431#else
432#define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, off(rbase); \
433 s.s rhi, (off+4)(rbase)
434#define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, off(rbase); \
435 l.s rhi, (off+4)(rbase)
436#endif
437
438#define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0)
439#define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0)
440
441
442#define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET)
443
444#define STACK_STORE(rd, off) sw rd, off(sp)
445#define STACK_LOAD(rd, off) lw rd, off(sp)
446#define CREATE_STACK(n) subu sp, sp, n
447#define DELETE_STACK(n) addu sp, sp, n
448
449#define LOAD_ADDR(dest, addr) la dest, addr
450#define LOAD_IMM(dest, imm) li dest, imm
451#define MOVE_REG(dest, src) move dest, src
452#define STACK_SIZE 128
453
454#define STACK_OFFSET_ARG04 16
455#define STACK_OFFSET_ARG05 20
456#define STACK_OFFSET_ARG06 24
457#define STACK_OFFSET_ARG07 28
458#define STACK_OFFSET_GP 84
459
460#define JAL(n) jal n
461#define BAL(n) bal n
462
463/*
464 * FP register usage restrictions:
465 * 1) We don't use the callee save FP registers so we don't have to save them.
466 * 2) We don't use the odd FP registers so we can share code with mips32r6.
467 */
468#define STACK_STORE_FULL() CREATE_STACK(STACK_SIZE); \
469 STACK_STORE(ra, 124); \
470 STACK_STORE(s8, 120); \
471 STACK_STORE(s0, 116); \
472 STACK_STORE(s1, 112); \
473 STACK_STORE(s2, 108); \
474 STACK_STORE(s3, 104); \
475 STACK_STORE(s4, 100); \
476 STACK_STORE(s5, 96); \
477 STACK_STORE(s6, 92); \
478 STACK_STORE(s7, 88);
479
480#define STACK_LOAD_FULL() STACK_LOAD(gp, STACK_OFFSET_GP); \
481 STACK_LOAD(s7, 88); \
482 STACK_LOAD(s6, 92); \
483 STACK_LOAD(s5, 96); \
484 STACK_LOAD(s4, 100); \
485 STACK_LOAD(s3, 104); \
486 STACK_LOAD(s2, 108); \
487 STACK_LOAD(s1, 112); \
488 STACK_LOAD(s0, 116); \
489 STACK_LOAD(s8, 120); \
490 STACK_LOAD(ra, 124); \
491 DELETE_STACK(STACK_SIZE)
492
493/* File: mips/entry.S */
494/*
495 * Copyright (C) 2016 The Android Open Source Project
496 *
497 * Licensed under the Apache License, Version 2.0 (the "License");
498 * you may not use this file except in compliance with the License.
499 * You may obtain a copy of the License at
500 *
501 * http://www.apache.org/licenses/LICENSE-2.0
502 *
503 * Unless required by applicable law or agreed to in writing, software
504 * distributed under the License is distributed on an "AS IS" BASIS,
505 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
506 * See the License for the specific language governing permissions and
507 * limitations under the License.
508 */
509/*
510 * Interpreter entry point.
511 */
512
513 .text
514 .align 2
515 .global ExecuteMterpImpl
516 .ent ExecuteMterpImpl
517 .frame sp, STACK_SIZE, ra
518/*
519 * On entry:
520 * a0 Thread* self
521 * a1 code_item
522 * a2 ShadowFrame
523 * a3 JValue* result_register
524 *
525 */
526
527ExecuteMterpImpl:
528 .set noreorder
529 .cpload t9
530 .set reorder
531/* Save to the stack. Frame size = STACK_SIZE */
532 STACK_STORE_FULL()
533/* This directive will make sure all subsequent jal restore gp at a known offset */
534 .cprestore STACK_OFFSET_GP
535
536 /* Remember the return register */
537 sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
538
539 /* Remember the code_item */
540 sw a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
541
542 /* set up "named" registers */
543 move rSELF, a0
544 lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
545 addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to insns[] (i.e. - the dalivk byte code).
546 EAS2(rREFS, rFP, a0) # point to reference array in shadow frame
547 lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
548 addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[]
549 EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode
550
551 EXPORT_PC()
552
553 /* Starting ibase */
554 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
555
556 /* start executing the instruction at rPC */
557 FETCH_INST() # load rINST from rPC
558 GET_INST_OPCODE(t0) # extract opcode from rINST
559 GOTO_OPCODE(t0) # jump to next instruction
560 /* NOTE: no fallthrough */
561
562
563 .global artMterpAsmInstructionStart
564 .type artMterpAsmInstructionStart, %function
565artMterpAsmInstructionStart = .L_op_nop
566 .text
567
568/* ------------------------------ */
569 .balign 128
570.L_op_nop: /* 0x00 */
571/* File: mips/op_nop.S */
572 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
573 GET_INST_OPCODE(t0) # extract opcode from rINST
574 GOTO_OPCODE(t0) # jump to next instruction
575
576/* ------------------------------ */
577 .balign 128
578.L_op_move: /* 0x01 */
579/* File: mips/op_move.S */
580 /* for move, move-object, long-to-int */
581 /* op vA, vB */
582 GET_OPB(a1) # a1 <- B from 15:12
583 GET_OPA4(a0) # a0 <- A from 11:8
584 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
585 GET_VREG(a2, a1) # a2 <- fp[B]
586 GET_INST_OPCODE(t0) # t0 <- opcode from rINST
587 .if 0
588 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
589 .else
590 SET_VREG(a2, a0) # fp[A] <- a2
591 .endif
592 GOTO_OPCODE(t0) # jump to next instruction
593
594/* ------------------------------ */
595 .balign 128
596.L_op_move_from16: /* 0x02 */
597/* File: mips/op_move_from16.S */
598 /* for: move/from16, move-object/from16 */
599 /* op vAA, vBBBB */
600 FETCH(a1, 1) # a1 <- BBBB
601 GET_OPA(a0) # a0 <- AA
602 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
603 GET_VREG(a2, a1) # a2 <- fp[BBBB]
604 GET_INST_OPCODE(t0) # extract opcode from rINST
605 .if 0
606 SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2
607 .else
608 SET_VREG(a2, a0) # fp[AA] <- a2
609 .endif
610 GOTO_OPCODE(t0) # jump to next instruction
611
612/* ------------------------------ */
613 .balign 128
614.L_op_move_16: /* 0x03 */
615/* File: mips/op_move_16.S */
616 /* for: move/16, move-object/16 */
617 /* op vAAAA, vBBBB */
618 FETCH(a1, 2) # a1 <- BBBB
619 FETCH(a0, 1) # a0 <- AAAA
620 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
621 GET_VREG(a2, a1) # a2 <- fp[BBBB]
622 GET_INST_OPCODE(t0) # extract opcode from rINST
623 .if 0
624 SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2
625 .else
626 SET_VREG(a2, a0) # fp[AAAA] <- a2
627 .endif
628 GOTO_OPCODE(t0) # jump to next instruction
629
630/* ------------------------------ */
631 .balign 128
632.L_op_move_wide: /* 0x04 */
633/* File: mips/op_move_wide.S */
634 /* move-wide vA, vB */
635 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
636 GET_OPA4(a2) # a2 <- A(+)
637 GET_OPB(a3) # a3 <- B
638 EAS2(a3, rFP, a3) # a3 <- &fp[B]
639 LOAD64(a0, a1, a3) # a0/a1 <- fp[B]
640 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
641 SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1
642 GET_INST_OPCODE(t0) # extract opcode from rINST
643 GOTO_OPCODE(t0) # jump to next instruction
644
645/* ------------------------------ */
646 .balign 128
647.L_op_move_wide_from16: /* 0x05 */
648/* File: mips/op_move_wide_from16.S */
649 /* move-wide/from16 vAA, vBBBB */
650 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
651 FETCH(a3, 1) # a3 <- BBBB
652 GET_OPA(a2) # a2 <- AA
653 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB]
654 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
655 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
656 SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1
657 GET_INST_OPCODE(t0) # extract opcode from rINST
658 GOTO_OPCODE(t0) # jump to next instruction
659
660/* ------------------------------ */
661 .balign 128
662.L_op_move_wide_16: /* 0x06 */
663/* File: mips/op_move_wide_16.S */
664 /* move-wide/16 vAAAA, vBBBB */
665 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */
666 FETCH(a3, 2) # a3 <- BBBB
667 FETCH(a2, 1) # a2 <- AAAA
668 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB]
669 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB]
670 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
671 SET_VREG64(a0, a1, a2) # fp[AAAA] <- a0/a1
672 GET_INST_OPCODE(t0) # extract opcode from rINST
673 GOTO_OPCODE(t0) # jump to next instruction
674
675/* ------------------------------ */
676 .balign 128
677.L_op_move_object: /* 0x07 */
678/* File: mips/op_move_object.S */
679/* File: mips/op_move.S */
680 /* for move, move-object, long-to-int */
681 /* op vA, vB */
682 GET_OPB(a1) # a1 <- B from 15:12
683 GET_OPA4(a0) # a0 <- A from 11:8
684 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
685 GET_VREG(a2, a1) # a2 <- fp[B]
686 GET_INST_OPCODE(t0) # t0 <- opcode from rINST
687 .if 1
688 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
689 .else
690 SET_VREG(a2, a0) # fp[A] <- a2
691 .endif
692 GOTO_OPCODE(t0) # jump to next instruction
693
694
695/* ------------------------------ */
696 .balign 128
697.L_op_move_object_from16: /* 0x08 */
698/* File: mips/op_move_object_from16.S */
699/* File: mips/op_move_from16.S */
700 /* for: move/from16, move-object/from16 */
701 /* op vAA, vBBBB */
702 FETCH(a1, 1) # a1 <- BBBB
703 GET_OPA(a0) # a0 <- AA
704 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
705 GET_VREG(a2, a1) # a2 <- fp[BBBB]
706 GET_INST_OPCODE(t0) # extract opcode from rINST
707 .if 1
708 SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2
709 .else
710 SET_VREG(a2, a0) # fp[AA] <- a2
711 .endif
712 GOTO_OPCODE(t0) # jump to next instruction
713
714
715/* ------------------------------ */
716 .balign 128
717.L_op_move_object_16: /* 0x09 */
718/* File: mips/op_move_object_16.S */
719/* File: mips/op_move_16.S */
720 /* for: move/16, move-object/16 */
721 /* op vAAAA, vBBBB */
722 FETCH(a1, 2) # a1 <- BBBB
723 FETCH(a0, 1) # a0 <- AAAA
724 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
725 GET_VREG(a2, a1) # a2 <- fp[BBBB]
726 GET_INST_OPCODE(t0) # extract opcode from rINST
727 .if 1
728 SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2
729 .else
730 SET_VREG(a2, a0) # fp[AAAA] <- a2
731 .endif
732 GOTO_OPCODE(t0) # jump to next instruction
733
734
735/* ------------------------------ */
736 .balign 128
737.L_op_move_result: /* 0x0a */
738/* File: mips/op_move_result.S */
739 /* for: move-result, move-result-object */
740 /* op vAA */
741 GET_OPA(a2) # a2 <- AA
742 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
743 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
744 lw a0, 0(a0) # a0 <- result.i
745 GET_INST_OPCODE(t0) # extract opcode from rINST
746 .if 0
747 SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0
748 .else
749 SET_VREG(a0, a2) # fp[AA] <- a0
750 .endif
751 GOTO_OPCODE(t0) # jump to next instruction
752
753/* ------------------------------ */
754 .balign 128
755.L_op_move_result_wide: /* 0x0b */
756/* File: mips/op_move_result_wide.S */
757 /* move-result-wide vAA */
758 GET_OPA(a2) # a2 <- AA
759 lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
760 LOAD64(a0, a1, a3) # a0/a1 <- retval.j
761 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
762 SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1
763 GET_INST_OPCODE(t0) # extract opcode from rINST
764 GOTO_OPCODE(t0) # jump to next instruction
765
766/* ------------------------------ */
767 .balign 128
768.L_op_move_result_object: /* 0x0c */
769/* File: mips/op_move_result_object.S */
770/* File: mips/op_move_result.S */
771 /* for: move-result, move-result-object */
772 /* op vAA */
773 GET_OPA(a2) # a2 <- AA
774 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
775 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
776 lw a0, 0(a0) # a0 <- result.i
777 GET_INST_OPCODE(t0) # extract opcode from rINST
778 .if 1
779 SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0
780 .else
781 SET_VREG(a0, a2) # fp[AA] <- a0
782 .endif
783 GOTO_OPCODE(t0) # jump to next instruction
784
785
786/* ------------------------------ */
787 .balign 128
788.L_op_move_exception: /* 0x0d */
789/* File: mips/op_move_exception.S */
790 /* move-exception vAA */
791 GET_OPA(a2) # a2 <- AA
792 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj
793 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
794 SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj
795 GET_INST_OPCODE(t0) # extract opcode from rINST
796 sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception
797 GOTO_OPCODE(t0) # jump to next instruction
798
799/* ------------------------------ */
800 .balign 128
801.L_op_return_void: /* 0x0e */
802/* File: mips/op_return_void.S */
803 .extern MterpThreadFenceForConstructor
804 JAL(MterpThreadFenceForConstructor)
805 lw ra, THREAD_FLAGS_OFFSET(rSELF)
806 move a0, rSELF
807 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
808 beqz ra, 1f
809 JAL(MterpSuspendCheck) # (self)
8101:
811 move v0, zero
812 move v1, zero
813 b MterpReturn
814
815/* ------------------------------ */
816 .balign 128
817.L_op_return: /* 0x0f */
818/* File: mips/op_return.S */
819 /*
820 * Return a 32-bit value.
821 *
822 * for: return, return-object
823 */
824 /* op vAA */
825 .extern MterpThreadFenceForConstructor
826 JAL(MterpThreadFenceForConstructor)
827 lw ra, THREAD_FLAGS_OFFSET(rSELF)
828 move a0, rSELF
829 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
830 beqz ra, 1f
831 JAL(MterpSuspendCheck) # (self)
8321:
833 GET_OPA(a2) # a2 <- AA
834 GET_VREG(v0, a2) # v0 <- vAA
835 move v1, zero
836 b MterpReturn
837
838/* ------------------------------ */
839 .balign 128
840.L_op_return_wide: /* 0x10 */
841/* File: mips/op_return_wide.S */
842 /*
843 * Return a 64-bit value.
844 */
845 /* return-wide vAA */
846 .extern MterpThreadFenceForConstructor
847 JAL(MterpThreadFenceForConstructor)
848 lw ra, THREAD_FLAGS_OFFSET(rSELF)
849 move a0, rSELF
850 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
851 beqz ra, 1f
852 JAL(MterpSuspendCheck) # (self)
8531:
854 GET_OPA(a2) # a2 <- AA
855 EAS2(a2, rFP, a2) # a2 <- &fp[AA]
856 LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1
857 b MterpReturn
858
859/* ------------------------------ */
860 .balign 128
861.L_op_return_object: /* 0x11 */
862/* File: mips/op_return_object.S */
863/* File: mips/op_return.S */
864 /*
865 * Return a 32-bit value.
866 *
867 * for: return, return-object
868 */
869 /* op vAA */
870 .extern MterpThreadFenceForConstructor
871 JAL(MterpThreadFenceForConstructor)
872 lw ra, THREAD_FLAGS_OFFSET(rSELF)
873 move a0, rSELF
874 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
875 beqz ra, 1f
876 JAL(MterpSuspendCheck) # (self)
8771:
878 GET_OPA(a2) # a2 <- AA
879 GET_VREG(v0, a2) # v0 <- vAA
880 move v1, zero
881 b MterpReturn
882
883
884/* ------------------------------ */
885 .balign 128
886.L_op_const_4: /* 0x12 */
887/* File: mips/op_const_4.S */
888 # const/4 vA, /* +B */
889 sll a1, rINST, 16 # a1 <- Bxxx0000
890 GET_OPA(a0) # a0 <- A+
891 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
892 sra a1, a1, 28 # a1 <- sssssssB (sign-extended)
893 and a0, a0, 15
894 GET_INST_OPCODE(t0) # extract opcode from rINST
895 SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1
896
897/* ------------------------------ */
898 .balign 128
899.L_op_const_16: /* 0x13 */
900/* File: mips/op_const_16.S */
901 # const/16 vAA, /* +BBBB */
902 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended)
903 GET_OPA(a3) # a3 <- AA
904 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
905 GET_INST_OPCODE(t0) # extract opcode from rINST
906 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
907
908/* ------------------------------ */
909 .balign 128
910.L_op_const: /* 0x14 */
911/* File: mips/op_const.S */
912 # const vAA, /* +BBBBbbbb */
913 GET_OPA(a3) # a3 <- AA
914 FETCH(a0, 1) # a0 <- bbbb (low)
915 FETCH(a1, 2) # a1 <- BBBB (high)
916 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
917 sll a1, a1, 16
918 or a0, a1, a0 # a0 <- BBBBbbbb
919 GET_INST_OPCODE(t0) # extract opcode from rINST
920 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
921
922/* ------------------------------ */
923 .balign 128
924.L_op_const_high16: /* 0x15 */
925/* File: mips/op_const_high16.S */
926 # const/high16 vAA, /* +BBBB0000 */
927 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended)
928 GET_OPA(a3) # a3 <- AA
929 sll a0, a0, 16 # a0 <- BBBB0000
930 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
931 GET_INST_OPCODE(t0) # extract opcode from rINST
932 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
933
934/* ------------------------------ */
935 .balign 128
936.L_op_const_wide_16: /* 0x16 */
937/* File: mips/op_const_wide_16.S */
938 # const-wide/16 vAA, /* +BBBB */
939 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended)
940 GET_OPA(a3) # a3 <- AA
941 sra a1, a0, 31 # a1 <- ssssssss
942 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
943 GET_INST_OPCODE(t0) # extract opcode from rINST
944 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
945 GOTO_OPCODE(t0) # jump to next instruction
946
947/* ------------------------------ */
948 .balign 128
949.L_op_const_wide_32: /* 0x17 */
950/* File: mips/op_const_wide_32.S */
951 # const-wide/32 vAA, /* +BBBBbbbb */
952 FETCH(a0, 1) # a0 <- 0000bbbb (low)
953 GET_OPA(a3) # a3 <- AA
954 FETCH_S(a2, 2) # a2 <- ssssBBBB (high)
955 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
956 sll a2, a2, 16
957 or a0, a0, a2 # a0 <- BBBBbbbb
958 sra a1, a0, 31 # a1 <- ssssssss
959 GET_INST_OPCODE(t0) # extract opcode from rINST
960 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
961 GOTO_OPCODE(t0) # jump to next instruction
962
963/* ------------------------------ */
964 .balign 128
965.L_op_const_wide: /* 0x18 */
966/* File: mips/op_const_wide.S */
967 # const-wide vAA, /* +HHHHhhhhBBBBbbbb */
968 FETCH(a0, 1) # a0 <- bbbb (low)
969 FETCH(a1, 2) # a1 <- BBBB (low middle)
970 FETCH(a2, 3) # a2 <- hhhh (high middle)
971 sll a1, 16 #
972 or a0, a1 # a0 <- BBBBbbbb (low word)
973 FETCH(a3, 4) # a3 <- HHHH (high)
974 GET_OPA(t1) # t1 <- AA
975 sll a3, 16
976 or a1, a3, a2 # a1 <- HHHHhhhh (high word)
977 FETCH_ADVANCE_INST(5) # advance rPC, load rINST
978 GET_INST_OPCODE(t0) # extract opcode from rINST
979 SET_VREG64(a0, a1, t1) # vAA <- a0/a1
980 GOTO_OPCODE(t0) # jump to next instruction
981
982/* ------------------------------ */
983 .balign 128
984.L_op_const_wide_high16: /* 0x19 */
985/* File: mips/op_const_wide_high16.S */
986 # const-wide/high16 vAA, /* +BBBB000000000000 */
987 FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended)
988 GET_OPA(a3) # a3 <- AA
989 li a0, 0 # a0 <- 00000000
990 sll a1, 16 # a1 <- BBBB0000
991 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
992 GET_INST_OPCODE(t0) # extract opcode from rINST
993 SET_VREG64(a0, a1, a3) # vAA <- a0/a1
994 GOTO_OPCODE(t0) # jump to next instruction
995
996/* ------------------------------ */
997 .balign 128
998.L_op_const_string: /* 0x1a */
999/* File: mips/op_const_string.S */
1000 # const/string vAA, String /* BBBB */
1001 EXPORT_PC()
1002 FETCH(a0, 1) # a0 <- BBBB
1003 GET_OPA(a1) # a1 <- AA
1004 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame
1005 move a3, rSELF
1006 JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self)
1007 PREFETCH_INST(2) # load rINST
1008 bnez v0, MterpPossibleException
1009 ADVANCE(2) # advance rPC
1010 GET_INST_OPCODE(t0) # extract opcode from rINST
1011 GOTO_OPCODE(t0) # jump to next instruction
1012
1013/* ------------------------------ */
1014 .balign 128
1015.L_op_const_string_jumbo: /* 0x1b */
1016/* File: mips/op_const_string_jumbo.S */
1017 # const/string vAA, String /* BBBBBBBB */
1018 EXPORT_PC()
1019 FETCH(a0, 1) # a0 <- bbbb (low)
1020 FETCH(a2, 2) # a2 <- BBBB (high)
1021 GET_OPA(a1) # a1 <- AA
1022 sll a2, a2, 16
1023 or a0, a0, a2 # a0 <- BBBBbbbb
1024 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame
1025 move a3, rSELF
1026 JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self)
1027 PREFETCH_INST(3) # load rINST
1028 bnez v0, MterpPossibleException
1029 ADVANCE(3) # advance rPC
1030 GET_INST_OPCODE(t0) # extract opcode from rINST
1031 GOTO_OPCODE(t0) # jump to next instruction
1032
1033/* ------------------------------ */
1034 .balign 128
1035.L_op_const_class: /* 0x1c */
1036/* File: mips/op_const_class.S */
1037 # const/class vAA, Class /* BBBB */
1038 EXPORT_PC()
1039 FETCH(a0, 1) # a0 <- BBBB
1040 GET_OPA(a1) # a1 <- AA
1041 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame
1042 move a3, rSELF
1043 JAL(MterpConstClass)
1044 PREFETCH_INST(2) # load rINST
1045 bnez v0, MterpPossibleException
1046 ADVANCE(2) # advance rPC
1047 GET_INST_OPCODE(t0) # extract opcode from rINST
1048 GOTO_OPCODE(t0) # jump to next instruction
1049
1050/* ------------------------------ */
1051 .balign 128
1052.L_op_monitor_enter: /* 0x1d */
1053/* File: mips/op_monitor_enter.S */
1054 /*
1055 * Synchronize on an object.
1056 */
1057 /* monitor-enter vAA */
1058 EXPORT_PC()
1059 GET_OPA(a2) # a2 <- AA
1060 GET_VREG(a0, a2) # a0 <- vAA (object)
1061 move a1, rSELF # a1 <- self
1062 JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self)
1063 bnez v0, MterpException
1064 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
1065 GET_INST_OPCODE(t0) # extract opcode from rINST
1066 GOTO_OPCODE(t0) # jump to next instruction
1067
1068/* ------------------------------ */
1069 .balign 128
1070.L_op_monitor_exit: /* 0x1e */
1071/* File: mips/op_monitor_exit.S */
1072 /*
1073 * Unlock an object.
1074 *
1075 * Exceptions that occur when unlocking a monitor need to appear as
1076 * if they happened at the following instruction. See the Dalvik
1077 * instruction spec.
1078 */
1079 /* monitor-exit vAA */
1080 EXPORT_PC()
1081 GET_OPA(a2) # a2 <- AA
1082 GET_VREG(a0, a2) # a0 <- vAA (object)
1083 move a1, rSELF # a1 <- self
1084 JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self)
1085 bnez v0, MterpException
1086 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
1087 GET_INST_OPCODE(t0) # extract opcode from rINST
1088 GOTO_OPCODE(t0) # jump to next instruction
1089
1090/* ------------------------------ */
1091 .balign 128
1092.L_op_check_cast: /* 0x1f */
1093/* File: mips/op_check_cast.S */
1094 /*
1095 * Check to see if a cast from one class to another is allowed.
1096 */
1097 # check-cast vAA, class /* BBBB */
1098 EXPORT_PC()
1099 FETCH(a0, 1) # a0 <- BBBB
1100 GET_OPA(a1) # a1 <- AA
1101 EAS2(a1, rFP, a1) # a1 <- &object
1102 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
1103 move a3, rSELF # a3 <- self
1104 JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self)
1105 PREFETCH_INST(2)
1106 bnez v0, MterpPossibleException
1107 ADVANCE(2)
1108 GET_INST_OPCODE(t0) # extract opcode from rINST
1109 GOTO_OPCODE(t0) # jump to next instruction
1110
1111/* ------------------------------ */
1112 .balign 128
1113.L_op_instance_of: /* 0x20 */
1114/* File: mips/op_instance_of.S */
1115 /*
1116 * Check to see if an object reference is an instance of a class.
1117 *
1118 * Most common situation is a non-null object, being compared against
1119 * an already-resolved class.
1120 */
1121 # instance-of vA, vB, class /* CCCC */
1122 EXPORT_PC()
1123 FETCH(a0, 1) # a0 <- CCCC
1124 GET_OPB(a1) # a1 <- B
1125 EAS2(a1, rFP, a1) # a1 <- &object
1126 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
1127 move a3, rSELF # a3 <- self
1128 GET_OPA4(rOBJ) # rOBJ <- A+
1129 JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self)
1130 lw a1, THREAD_EXCEPTION_OFFSET(rSELF)
1131 PREFETCH_INST(2) # load rINST
1132 bnez a1, MterpException
1133 ADVANCE(2) # advance rPC
1134 GET_INST_OPCODE(t0) # extract opcode from rINST
1135 SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0
1136
1137/* ------------------------------ */
1138 .balign 128
1139.L_op_array_length: /* 0x21 */
1140/* File: mips/op_array_length.S */
1141 /*
1142 * Return the length of an array.
1143 */
1144 GET_OPB(a1) # a1 <- B
1145 GET_OPA4(a2) # a2 <- A+
1146 GET_VREG(a0, a1) # a0 <- vB (object ref)
1147 # is object null?
1148 beqz a0, common_errNullObject # yup, fail
1149 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
1150 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length
1151 GET_INST_OPCODE(t0) # extract opcode from rINST
1152 SET_VREG_GOTO(a3, a2, t0) # vA <- length
1153
1154/* ------------------------------ */
1155 .balign 128
1156.L_op_new_instance: /* 0x22 */
1157/* File: mips/op_new_instance.S */
1158 /*
1159 * Create a new instance of a class.
1160 */
1161 # new-instance vAA, class /* BBBB */
1162 EXPORT_PC()
1163 addu a0, rFP, OFF_FP_SHADOWFRAME
1164 move a1, rSELF
1165 move a2, rINST
1166 JAL(MterpNewInstance)
1167 beqz v0, MterpPossibleException
1168 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
1169 GET_INST_OPCODE(t0) # extract opcode from rINST
1170 GOTO_OPCODE(t0) # jump to next instruction
1171
1172/* ------------------------------ */
1173 .balign 128
1174.L_op_new_array: /* 0x23 */
1175/* File: mips/op_new_array.S */
1176 /*
1177 * Allocate an array of objects, specified with the array class
1178 * and a count.
1179 *
1180 * The verifier guarantees that this is an array class, so we don't
1181 * check for it here.
1182 */
1183 /* new-array vA, vB, class@CCCC */
1184 EXPORT_PC()
1185 addu a0, rFP, OFF_FP_SHADOWFRAME
1186 move a1, rPC
1187 move a2, rINST
1188 move a3, rSELF
1189 JAL(MterpNewArray)
1190 beqz v0, MterpPossibleException
1191 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
1192 GET_INST_OPCODE(t0) # extract opcode from rINST
1193 GOTO_OPCODE(t0) # jump to next instruction
1194
1195/* ------------------------------ */
1196 .balign 128
1197.L_op_filled_new_array: /* 0x24 */
1198/* File: mips/op_filled_new_array.S */
1199 /*
1200 * Create a new array with elements filled from registers.
1201 *
1202 * for: filled-new-array, filled-new-array/range
1203 */
1204 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
1205 # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */
1206 .extern MterpFilledNewArray
1207 EXPORT_PC()
1208 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame
1209 move a1, rPC
1210 move a2, rSELF
1211 JAL(MterpFilledNewArray) # v0 <- helper(shadow_frame, pc, self)
1212 beqz v0, MterpPossibleException # has exception
1213 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
1214 GET_INST_OPCODE(t0) # extract opcode from rINST
1215 GOTO_OPCODE(t0) # jump to next instruction
1216
1217/* ------------------------------ */
1218 .balign 128
1219.L_op_filled_new_array_range: /* 0x25 */
1220/* File: mips/op_filled_new_array_range.S */
1221/* File: mips/op_filled_new_array.S */
1222 /*
1223 * Create a new array with elements filled from registers.
1224 *
1225 * for: filled-new-array, filled-new-array/range
1226 */
1227 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
1228 # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */
1229 .extern MterpFilledNewArrayRange
1230 EXPORT_PC()
1231 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame
1232 move a1, rPC
1233 move a2, rSELF
1234 JAL(MterpFilledNewArrayRange) # v0 <- helper(shadow_frame, pc, self)
1235 beqz v0, MterpPossibleException # has exception
1236 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
1237 GET_INST_OPCODE(t0) # extract opcode from rINST
1238 GOTO_OPCODE(t0) # jump to next instruction
1239
1240
1241/* ------------------------------ */
1242 .balign 128
1243.L_op_fill_array_data: /* 0x26 */
1244/* File: mips/op_fill_array_data.S */
1245 /* fill-array-data vAA, +BBBBBBBB */
1246 EXPORT_PC()
1247 FETCH(a0, 1) # a0 <- bbbb (lo)
1248 FETCH(a1, 2) # a1 <- BBBB (hi)
1249 GET_OPA(a3) # a3 <- AA
1250 sll a1, a1, 16 # a1 <- BBBBbbbb
1251 or a1, a0, a1 # a1 <- BBBBbbbb
1252 GET_VREG(a0, a3) # a0 <- vAA (array object)
1253 EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.)
1254 JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload)
1255 beqz v0, MterpPossibleException # has exception
1256 FETCH_ADVANCE_INST(3) # advance rPC, load rINST
1257 GET_INST_OPCODE(t0) # extract opcode from rINST
1258 GOTO_OPCODE(t0) # jump to next instruction
1259
1260/* ------------------------------ */
1261 .balign 128
1262.L_op_throw: /* 0x27 */
1263/* File: mips/op_throw.S */
1264 /*
1265 * Throw an exception object in the current thread.
1266 */
1267 /* throw vAA */
1268 EXPORT_PC() # exception handler can throw
1269 GET_OPA(a2) # a2 <- AA
1270 GET_VREG(a1, a2) # a1 <- vAA (exception object)
1271 # null object?
1272 beqz a1, common_errNullObject # yes, throw an NPE instead
1273 sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj
1274 b MterpException
1275
1276/* ------------------------------ */
1277 .balign 128
1278.L_op_goto: /* 0x28 */
1279/* File: mips/op_goto.S */
1280 /*
1281 * Unconditional branch, 8-bit offset.
1282 *
1283 * The branch distance is a signed code-unit offset, which we need to
1284 * double to get a byte offset.
1285 */
1286 /* goto +AA */
1287#if MTERP_PROFILE_BRANCHES
1288 sll a0, rINST, 16 # a0 <- AAxx0000
1289 sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended)
1290 EXPORT_PC()
1291 move a0, rSELF
1292 addu a1, rFP, OFF_FP_SHADOWFRAME
1293 move a2, rINST
1294 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1295 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1296 addu a2, rINST, rINST # a2 <- byte offset
1297 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1298 /* If backwards branch refresh rIBASE */
1299 bgez a2, 1f
1300 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1301 b MterpCheckSuspendAndContinue
13021:
1303 GET_INST_OPCODE(t0) # extract opcode from rINST
1304 GOTO_OPCODE(t0) # jump to next instruction
1305#else
1306 sll a0, rINST, 16 # a0 <- AAxx0000
1307 sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended)
1308 addu a2, rINST, rINST # a2 <- byte offset
1309 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1310 /* If backwards branch refresh rIBASE */
1311 bgez a1, 1f
1312 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1313 b MterpCheckSuspendAndContinue
13141:
1315 GET_INST_OPCODE(t0) # extract opcode from rINST
1316 GOTO_OPCODE(t0) # jump to next instruction
1317#endif
1318
1319/* ------------------------------ */
1320 .balign 128
1321.L_op_goto_16: /* 0x29 */
1322/* File: mips/op_goto_16.S */
1323 /*
1324 * Unconditional branch, 16-bit offset.
1325 *
1326 * The branch distance is a signed code-unit offset, which we need to
1327 * double to get a byte offset.
1328 */
1329 /* goto/16 +AAAA */
1330#if MTERP_PROFILE_BRANCHES
1331 FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended)
1332 EXPORT_PC()
1333 move a0, rSELF
1334 addu a1, rFP, OFF_FP_SHADOWFRAME
1335 move a2, rINST
1336 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1337 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1338 addu a1, rINST, rINST # a1 <- byte offset, flags set
1339 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1340 bgez a1, 1f
1341 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1342 b MterpCheckSuspendAndContinue
13431:
1344 GET_INST_OPCODE(t0) # extract opcode from rINST
1345 GOTO_OPCODE(t0) # jump to next instruction
1346#else
1347 FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended)
1348 addu a1, rINST, rINST # a1 <- byte offset, flags set
1349 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1350 bgez a1, 1f
1351 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1352 b MterpCheckSuspendAndContinue
13531:
1354 GET_INST_OPCODE(t0) # extract opcode from rINST
1355 GOTO_OPCODE(t0) # jump to next instruction
1356#endif
1357
1358/* ------------------------------ */
1359 .balign 128
1360.L_op_goto_32: /* 0x2a */
1361/* File: mips/op_goto_32.S */
1362 /*
1363 * Unconditional branch, 32-bit offset.
1364 *
1365 * The branch distance is a signed code-unit offset, which we need to
1366 * double to get a byte offset.
1367 *
1368 * Unlike most opcodes, this one is allowed to branch to itself, so
1369 * our "backward branch" test must be "<=0" instead of "<0".
1370 */
1371 /* goto/32 +AAAAAAAA */
1372#if MTERP_PROFILE_BRANCHES
1373 FETCH(a0, 1) # a0 <- aaaa (lo)
1374 FETCH(a1, 2) # a1 <- AAAA (hi)
1375 sll a1, a1, 16
1376 or rINST, a0, a1 # rINST <- AAAAaaaa
1377 EXPORT_PC()
1378 move a0, rSELF
1379 addu a1, rFP, OFF_FP_SHADOWFRAME
1380 move a2, rINST
1381 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1382 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1383 addu a1, rINST, rINST # a1 <- byte offset
1384 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1385 bgtz a1, 1f
1386 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1387 b MterpCheckSuspendAndContinue
13881:
1389 GET_INST_OPCODE(t0) # extract opcode from rINST
1390 GOTO_OPCODE(t0) # jump to next instruction
1391#else
1392 FETCH(a0, 1) # a0 <- aaaa (lo)
1393 FETCH(a1, 2) # a1 <- AAAA (hi)
1394 sll a1, a1, 16
1395 or rINST, a0, a1 # rINST <- AAAAaaaa
1396 addu a1, rINST, rINST # a1 <- byte offset
1397 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1398 bgtz a1, 1f
1399 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1400 b MterpCheckSuspendAndContinue
14011:
1402 GET_INST_OPCODE(t0) # extract opcode from rINST
1403 GOTO_OPCODE(t0) # jump to next instruction
1404#endif
1405
1406/* ------------------------------ */
1407 .balign 128
1408.L_op_packed_switch: /* 0x2b */
1409/* File: mips/op_packed_switch.S */
1410 /*
1411 * Handle a packed-switch or sparse-switch instruction. In both cases
1412 * we decode it and hand it off to a helper function.
1413 *
1414 * We don't really expect backward branches in a switch statement, but
1415 * they're perfectly legal, so we check for them here.
1416 *
1417 * for: packed-switch, sparse-switch
1418 */
1419 /* op vAA, +BBBB */
1420#if MTERP_PROFILE_BRANCHES
1421 FETCH(a0, 1) # a0 <- bbbb (lo)
1422 FETCH(a1, 2) # a1 <- BBBB (hi)
1423 GET_OPA(a3) # a3 <- AA
1424 sll t0, a1, 16
1425 or a0, a0, t0 # a0 <- BBBBbbbb
1426 GET_VREG(a1, a3) # a1 <- vAA
1427 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1428 JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset
1429 move rINST, v0
1430 EXPORT_PC()
1431 move a0, rSELF
1432 addu a1, rFP, OFF_FP_SHADOWFRAME
1433 move a2, rINST
1434 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1435 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1436 addu a1, rINST, rINST # a1 <- byte offset
1437 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1438 bgtz a1, .Lop_packed_switch_finish
1439 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1440 b MterpCheckSuspendAndContinue
1441#else
1442 FETCH(a0, 1) # a0 <- bbbb (lo)
1443 FETCH(a1, 2) # a1 <- BBBB (hi)
1444 GET_OPA(a3) # a3 <- AA
1445 sll t0, a1, 16
1446 or a0, a0, t0 # a0 <- BBBBbbbb
1447 GET_VREG(a1, a3) # a1 <- vAA
1448 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1449 JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset
1450 move rINST, v0
1451 addu a1, rINST, rINST # a1 <- byte offset
1452 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1453 bgtz a1, 1f
1454 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1455 b MterpCheckSuspendAndContinue
14561:
1457 GET_INST_OPCODE(t0) # extract opcode from rINST
1458 GOTO_OPCODE(t0) # jump to next instruction
1459#endif
1460
1461
1462/* ------------------------------ */
1463 .balign 128
1464.L_op_sparse_switch: /* 0x2c */
1465/* File: mips/op_sparse_switch.S */
1466/* File: mips/op_packed_switch.S */
1467 /*
1468 * Handle a packed-switch or sparse-switch instruction. In both cases
1469 * we decode it and hand it off to a helper function.
1470 *
1471 * We don't really expect backward branches in a switch statement, but
1472 * they're perfectly legal, so we check for them here.
1473 *
1474 * for: packed-switch, sparse-switch
1475 */
1476 /* op vAA, +BBBB */
1477#if MTERP_PROFILE_BRANCHES
1478 FETCH(a0, 1) # a0 <- bbbb (lo)
1479 FETCH(a1, 2) # a1 <- BBBB (hi)
1480 GET_OPA(a3) # a3 <- AA
1481 sll t0, a1, 16
1482 or a0, a0, t0 # a0 <- BBBBbbbb
1483 GET_VREG(a1, a3) # a1 <- vAA
1484 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1485 JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset
1486 move rINST, v0
1487 EXPORT_PC()
1488 move a0, rSELF
1489 addu a1, rFP, OFF_FP_SHADOWFRAME
1490 move a2, rINST
1491 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1492 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1493 addu a1, rINST, rINST # a1 <- byte offset
1494 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1495 bgtz a1, .Lop_sparse_switch_finish
1496 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1497 b MterpCheckSuspendAndContinue
1498#else
1499 FETCH(a0, 1) # a0 <- bbbb (lo)
1500 FETCH(a1, 2) # a1 <- BBBB (hi)
1501 GET_OPA(a3) # a3 <- AA
1502 sll t0, a1, 16
1503 or a0, a0, t0 # a0 <- BBBBbbbb
1504 GET_VREG(a1, a3) # a1 <- vAA
1505 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
1506 JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset
1507 move rINST, v0
1508 addu a1, rINST, rINST # a1 <- byte offset
1509 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
1510 bgtz a1, 1f
1511 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1512 b MterpCheckSuspendAndContinue
15131:
1514 GET_INST_OPCODE(t0) # extract opcode from rINST
1515 GOTO_OPCODE(t0) # jump to next instruction
1516#endif
1517
1518
1519
1520/* ------------------------------ */
1521 .balign 128
1522.L_op_cmpl_float: /* 0x2d */
1523/* File: mips/op_cmpl_float.S */
1524 /*
1525 * Compare two floating-point values. Puts 0, 1, or -1 into the
1526 * destination register rTEMP based on the results of the comparison.
1527 *
1528 * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending
1529 * on what value we'd like to return when one of the operands is NaN.
1530 *
1531 * The operation we're implementing is:
1532 * if (x == y)
1533 * return 0;
1534 * else if (x < y)
1535 * return -1;
1536 * else if (x > y)
1537 * return 1;
1538 * else
1539 * return {-1 or 1}; // one or both operands was NaN
1540 *
1541 * for: cmpl-float, cmpg-float
1542 */
1543 /* op vAA, vBB, vCC */
1544
1545 /* "clasic" form */
1546 FETCH(a0, 1) # a0 <- CCBB
1547 and a2, a0, 255 # a2 <- BB
1548 srl a3, a0, 8
1549 GET_VREG_F(ft0, a2)
1550 GET_VREG_F(ft1, a3)
1551#ifdef MIPS32REVGE6
1552 cmp.ult.s ft2, ft0, ft1 # Is ft0 < ft1
1553 li rTEMP, -1
1554 bc1nez ft2, .Lop_cmpl_float_finish
1555 cmp.ult.s ft2, ft1, ft0
1556 li rTEMP, 1
1557 bc1nez ft2, .Lop_cmpl_float_finish
1558 cmp.eq.s ft2, ft0, ft1
1559 li rTEMP, 0
1560 bc1nez ft2, .Lop_cmpl_float_finish
1561 b .Lop_cmpl_float_nan
1562#else
1563 c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1
1564 li rTEMP, -1
1565 bc1t fcc0, .Lop_cmpl_float_finish
1566 c.olt.s fcc0, ft1, ft0
1567 li rTEMP, 1
1568 bc1t fcc0, .Lop_cmpl_float_finish
1569 c.eq.s fcc0, ft0, ft1
1570 li rTEMP, 0
1571 bc1t fcc0, .Lop_cmpl_float_finish
1572 b .Lop_cmpl_float_nan
1573#endif
1574
1575/* ------------------------------ */
1576 .balign 128
1577.L_op_cmpg_float: /* 0x2e */
1578/* File: mips/op_cmpg_float.S */
1579/* File: mips/op_cmpl_float.S */
1580 /*
1581 * Compare two floating-point values. Puts 0, 1, or -1 into the
1582 * destination register rTEMP based on the results of the comparison.
1583 *
1584 * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending
1585 * on what value we'd like to return when one of the operands is NaN.
1586 *
1587 * The operation we're implementing is:
1588 * if (x == y)
1589 * return 0;
1590 * else if (x < y)
1591 * return -1;
1592 * else if (x > y)
1593 * return 1;
1594 * else
1595 * return {-1 or 1}; // one or both operands was NaN
1596 *
1597 * for: cmpl-float, cmpg-float
1598 */
1599 /* op vAA, vBB, vCC */
1600
1601 /* "clasic" form */
1602 FETCH(a0, 1) # a0 <- CCBB
1603 and a2, a0, 255 # a2 <- BB
1604 srl a3, a0, 8
1605 GET_VREG_F(ft0, a2)
1606 GET_VREG_F(ft1, a3)
1607#ifdef MIPS32REVGE6
1608 cmp.ult.s ft2, ft0, ft1 # Is ft0 < ft1
1609 li rTEMP, -1
1610 bc1nez ft2, .Lop_cmpg_float_finish
1611 cmp.ult.s ft2, ft1, ft0
1612 li rTEMP, 1
1613 bc1nez ft2, .Lop_cmpg_float_finish
1614 cmp.eq.s ft2, ft0, ft1
1615 li rTEMP, 0
1616 bc1nez ft2, .Lop_cmpg_float_finish
1617 b .Lop_cmpg_float_nan
1618#else
1619 c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1
1620 li rTEMP, -1
1621 bc1t fcc0, .Lop_cmpg_float_finish
1622 c.olt.s fcc0, ft1, ft0
1623 li rTEMP, 1
1624 bc1t fcc0, .Lop_cmpg_float_finish
1625 c.eq.s fcc0, ft0, ft1
1626 li rTEMP, 0
1627 bc1t fcc0, .Lop_cmpg_float_finish
1628 b .Lop_cmpg_float_nan
1629#endif
1630
1631
1632/* ------------------------------ */
1633 .balign 128
1634.L_op_cmpl_double: /* 0x2f */
1635/* File: mips/op_cmpl_double.S */
1636 /*
1637 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
1638 * into the destination register (rTEMP) based on the comparison results.
1639 *
1640 * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending
1641 * on what value we'd like to return when one of the operands is NaN.
1642 *
1643 * See op_cmpl_float for more details.
1644 *
1645 * For: cmpl-double, cmpg-double
1646 */
1647 /* op vAA, vBB, vCC */
1648
1649 FETCH(a0, 1) # a0 <- CCBB
1650 and rOBJ, a0, 255 # s5 <- BB
1651 srl t0, a0, 8 # t0 <- CC
1652 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[BB]
1653 EAS2(t0, rFP, t0) # t0 <- &fp[CC]
1654 LOAD64_F(ft0, ft0f, rOBJ)
1655 LOAD64_F(ft1, ft1f, t0)
1656#ifdef MIPS32REVGE6
1657 cmp.ult.d ft2, ft0, ft1
1658 li rTEMP, -1
1659 bc1nez ft2, .Lop_cmpl_double_finish
1660 cmp.ult.d ft2, ft1, ft0
1661 li rTEMP, 1
1662 bc1nez ft2, .Lop_cmpl_double_finish
1663 cmp.eq.d ft2, ft0, ft1
1664 li rTEMP, 0
1665 bc1nez ft2, .Lop_cmpl_double_finish
1666 b .Lop_cmpl_double_nan
1667#else
1668 c.olt.d fcc0, ft0, ft1
1669 li rTEMP, -1
1670 bc1t fcc0, .Lop_cmpl_double_finish
1671 c.olt.d fcc0, ft1, ft0
1672 li rTEMP, 1
1673 bc1t fcc0, .Lop_cmpl_double_finish
1674 c.eq.d fcc0, ft0, ft1
1675 li rTEMP, 0
1676 bc1t fcc0, .Lop_cmpl_double_finish
1677 b .Lop_cmpl_double_nan
1678#endif
1679
1680/* ------------------------------ */
1681 .balign 128
1682.L_op_cmpg_double: /* 0x30 */
1683/* File: mips/op_cmpg_double.S */
1684/* File: mips/op_cmpl_double.S */
1685 /*
1686 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
1687 * into the destination register (rTEMP) based on the comparison results.
1688 *
1689 * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending
1690 * on what value we'd like to return when one of the operands is NaN.
1691 *
1692 * See op_cmpl_float for more details.
1693 *
1694 * For: cmpl-double, cmpg-double
1695 */
1696 /* op vAA, vBB, vCC */
1697
1698 FETCH(a0, 1) # a0 <- CCBB
1699 and rOBJ, a0, 255 # s5 <- BB
1700 srl t0, a0, 8 # t0 <- CC
1701 EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[BB]
1702 EAS2(t0, rFP, t0) # t0 <- &fp[CC]
1703 LOAD64_F(ft0, ft0f, rOBJ)
1704 LOAD64_F(ft1, ft1f, t0)
1705#ifdef MIPS32REVGE6
1706 cmp.ult.d ft2, ft0, ft1
1707 li rTEMP, -1
1708 bc1nez ft2, .Lop_cmpg_double_finish
1709 cmp.ult.d ft2, ft1, ft0
1710 li rTEMP, 1
1711 bc1nez ft2, .Lop_cmpg_double_finish
1712 cmp.eq.d ft2, ft0, ft1
1713 li rTEMP, 0
1714 bc1nez ft2, .Lop_cmpg_double_finish
1715 b .Lop_cmpg_double_nan
1716#else
1717 c.olt.d fcc0, ft0, ft1
1718 li rTEMP, -1
1719 bc1t fcc0, .Lop_cmpg_double_finish
1720 c.olt.d fcc0, ft1, ft0
1721 li rTEMP, 1
1722 bc1t fcc0, .Lop_cmpg_double_finish
1723 c.eq.d fcc0, ft0, ft1
1724 li rTEMP, 0
1725 bc1t fcc0, .Lop_cmpg_double_finish
1726 b .Lop_cmpg_double_nan
1727#endif
1728
1729
1730/* ------------------------------ */
1731 .balign 128
1732.L_op_cmp_long: /* 0x31 */
1733/* File: mips/op_cmp_long.S */
1734 /*
1735 * Compare two 64-bit values
1736 * x = y return 0
1737 * x < y return -1
1738 * x > y return 1
1739 *
1740 * I think I can improve on the ARM code by the following observation
1741 * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0
1742 * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0
1743 * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ]
1744 */
1745 /* cmp-long vAA, vBB, vCC */
1746 FETCH(a0, 1) # a0 <- CCBB
1747 GET_OPA(rOBJ) # rOBJ <- AA
1748 and a2, a0, 255 # a2 <- BB
1749 srl a3, a0, 8 # a3 <- CC
1750 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
1751 EAS2(a3, rFP, a3) # a3 <- &fp[CC]
1752 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
1753 LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1
1754
1755 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
1756 slt t0, a1, a3 # compare hi
1757 sgt t1, a1, a3
1758 subu v0, t1, t0 # v0 <- (-1, 1, 0)
1759 bnez v0, .Lop_cmp_long_finish
1760 # at this point x.hi==y.hi
1761 sltu t0, a0, a2 # compare lo
1762 sgtu t1, a0, a2
1763 subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =]
1764
1765.Lop_cmp_long_finish:
1766 GET_INST_OPCODE(t0) # extract opcode from rINST
1767 SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0
1768
1769/* ------------------------------ */
1770 .balign 128
1771.L_op_if_eq: /* 0x32 */
1772/* File: mips/op_if_eq.S */
1773/* File: mips/bincmp.S */
1774 /*
1775 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1776 * fragment that specifies the *reverse* comparison to perform, e.g.
1777 * for "if-le" you would use "gt".
1778 *
1779 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1780 */
1781 /* if-cmp vA, vB, +CCCC */
1782 GET_OPA4(a0) # a0 <- A+
1783 GET_OPB(a1) # a1 <- B
1784 GET_VREG(a3, a1) # a3 <- vB
1785 GET_VREG(a2, a0) # a2 <- vA
1786 bne a2, a3, 1f # branch to 1 if comparison failed
1787 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1788 b 2f
17891:
1790 li rINST, 2 # rINST- BYTE branch dist for not-taken
17912:
1792#if MTERP_PROFILE_BRANCHES
1793 EXPORT_PC()
1794 move a0, rSELF
1795 addu a1, rFP, OFF_FP_SHADOWFRAME
1796 move a2, rINST
1797 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1798 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1799#endif
1800 addu a2, rINST, rINST # convert to bytes
1801 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1802 bgez a2, .L_op_if_eq_finish
1803 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1804 b MterpCheckSuspendAndContinue
1805
1806
1807
1808/* ------------------------------ */
1809 .balign 128
1810.L_op_if_ne: /* 0x33 */
1811/* File: mips/op_if_ne.S */
1812/* File: mips/bincmp.S */
1813 /*
1814 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1815 * fragment that specifies the *reverse* comparison to perform, e.g.
1816 * for "if-le" you would use "gt".
1817 *
1818 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1819 */
1820 /* if-cmp vA, vB, +CCCC */
1821 GET_OPA4(a0) # a0 <- A+
1822 GET_OPB(a1) # a1 <- B
1823 GET_VREG(a3, a1) # a3 <- vB
1824 GET_VREG(a2, a0) # a2 <- vA
1825 beq a2, a3, 1f # branch to 1 if comparison failed
1826 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1827 b 2f
18281:
1829 li rINST, 2 # rINST- BYTE branch dist for not-taken
18302:
1831#if MTERP_PROFILE_BRANCHES
1832 EXPORT_PC()
1833 move a0, rSELF
1834 addu a1, rFP, OFF_FP_SHADOWFRAME
1835 move a2, rINST
1836 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1837 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1838#endif
1839 addu a2, rINST, rINST # convert to bytes
1840 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1841 bgez a2, .L_op_if_ne_finish
1842 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1843 b MterpCheckSuspendAndContinue
1844
1845
1846
1847/* ------------------------------ */
1848 .balign 128
1849.L_op_if_lt: /* 0x34 */
1850/* File: mips/op_if_lt.S */
1851/* File: mips/bincmp.S */
1852 /*
1853 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1854 * fragment that specifies the *reverse* comparison to perform, e.g.
1855 * for "if-le" you would use "gt".
1856 *
1857 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1858 */
1859 /* if-cmp vA, vB, +CCCC */
1860 GET_OPA4(a0) # a0 <- A+
1861 GET_OPB(a1) # a1 <- B
1862 GET_VREG(a3, a1) # a3 <- vB
1863 GET_VREG(a2, a0) # a2 <- vA
1864 bge a2, a3, 1f # branch to 1 if comparison failed
1865 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1866 b 2f
18671:
1868 li rINST, 2 # rINST- BYTE branch dist for not-taken
18692:
1870#if MTERP_PROFILE_BRANCHES
1871 EXPORT_PC()
1872 move a0, rSELF
1873 addu a1, rFP, OFF_FP_SHADOWFRAME
1874 move a2, rINST
1875 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1876 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1877#endif
1878 addu a2, rINST, rINST # convert to bytes
1879 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1880 bgez a2, .L_op_if_lt_finish
1881 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1882 b MterpCheckSuspendAndContinue
1883
1884
1885
1886/* ------------------------------ */
1887 .balign 128
1888.L_op_if_ge: /* 0x35 */
1889/* File: mips/op_if_ge.S */
1890/* File: mips/bincmp.S */
1891 /*
1892 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1893 * fragment that specifies the *reverse* comparison to perform, e.g.
1894 * for "if-le" you would use "gt".
1895 *
1896 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1897 */
1898 /* if-cmp vA, vB, +CCCC */
1899 GET_OPA4(a0) # a0 <- A+
1900 GET_OPB(a1) # a1 <- B
1901 GET_VREG(a3, a1) # a3 <- vB
1902 GET_VREG(a2, a0) # a2 <- vA
1903 blt a2, a3, 1f # branch to 1 if comparison failed
1904 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1905 b 2f
19061:
1907 li rINST, 2 # rINST- BYTE branch dist for not-taken
19082:
1909#if MTERP_PROFILE_BRANCHES
1910 EXPORT_PC()
1911 move a0, rSELF
1912 addu a1, rFP, OFF_FP_SHADOWFRAME
1913 move a2, rINST
1914 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1915 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1916#endif
1917 addu a2, rINST, rINST # convert to bytes
1918 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1919 bgez a2, .L_op_if_ge_finish
1920 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1921 b MterpCheckSuspendAndContinue
1922
1923
1924
1925/* ------------------------------ */
1926 .balign 128
1927.L_op_if_gt: /* 0x36 */
1928/* File: mips/op_if_gt.S */
1929/* File: mips/bincmp.S */
1930 /*
1931 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1932 * fragment that specifies the *reverse* comparison to perform, e.g.
1933 * for "if-le" you would use "gt".
1934 *
1935 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1936 */
1937 /* if-cmp vA, vB, +CCCC */
1938 GET_OPA4(a0) # a0 <- A+
1939 GET_OPB(a1) # a1 <- B
1940 GET_VREG(a3, a1) # a3 <- vB
1941 GET_VREG(a2, a0) # a2 <- vA
1942 ble a2, a3, 1f # branch to 1 if comparison failed
1943 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1944 b 2f
19451:
1946 li rINST, 2 # rINST- BYTE branch dist for not-taken
19472:
1948#if MTERP_PROFILE_BRANCHES
1949 EXPORT_PC()
1950 move a0, rSELF
1951 addu a1, rFP, OFF_FP_SHADOWFRAME
1952 move a2, rINST
1953 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1954 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1955#endif
1956 addu a2, rINST, rINST # convert to bytes
1957 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1958 bgez a2, .L_op_if_gt_finish
1959 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1960 b MterpCheckSuspendAndContinue
1961
1962
1963
1964/* ------------------------------ */
1965 .balign 128
1966.L_op_if_le: /* 0x37 */
1967/* File: mips/op_if_le.S */
1968/* File: mips/bincmp.S */
1969 /*
1970 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1971 * fragment that specifies the *reverse* comparison to perform, e.g.
1972 * for "if-le" you would use "gt".
1973 *
1974 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1975 */
1976 /* if-cmp vA, vB, +CCCC */
1977 GET_OPA4(a0) # a0 <- A+
1978 GET_OPB(a1) # a1 <- B
1979 GET_VREG(a3, a1) # a3 <- vB
1980 GET_VREG(a2, a0) # a2 <- vA
1981 bgt a2, a3, 1f # branch to 1 if comparison failed
1982 FETCH_S(rINST, 1) # rINST<- branch offset, in code units
1983 b 2f
19841:
1985 li rINST, 2 # rINST- BYTE branch dist for not-taken
19862:
1987#if MTERP_PROFILE_BRANCHES
1988 EXPORT_PC()
1989 move a0, rSELF
1990 addu a1, rFP, OFF_FP_SHADOWFRAME
1991 move a2, rINST
1992 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
1993 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
1994#endif
1995 addu a2, rINST, rINST # convert to bytes
1996 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST
1997 bgez a2, .L_op_if_le_finish
1998 lw ra, THREAD_FLAGS_OFFSET(rSELF)
1999 b MterpCheckSuspendAndContinue
2000
2001
2002
2003/* ------------------------------ */
2004 .balign 128
2005.L_op_if_eqz: /* 0x38 */
2006/* File: mips/op_if_eqz.S */
2007/* File: mips/zcmp.S */
2008 /*
2009 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2010 * fragment that specifies the *reverse* comparison to perform, e.g.
2011 * for "if-le" you would use "gt".
2012 *
2013 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2014 */
2015 /* if-cmp vAA, +BBBB */
2016 GET_OPA(a0) # a0 <- AA
2017 GET_VREG(a2, a0) # a2 <- vAA
2018 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2019 bne a2, zero, 1f # branch to 1 if comparison failed
2020 b 2f
20211:
2022 li rINST, 2 # rINST- BYTE branch dist for not-taken
20232:
2024#if MTERP_PROFILE_BRANCHES
2025 EXPORT_PC()
2026 move a0, rSELF
2027 addu a1, rFP, OFF_FP_SHADOWFRAME
2028 move a2, rINST
2029 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2030 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2031#endif
2032 addu a1, rINST, rINST # convert to bytes
2033 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2034 bgez a1, 3f
2035 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2036 b MterpCheckSuspendAndContinue
20373:
2038 GET_INST_OPCODE(t0) # extract opcode from rINST
2039 GOTO_OPCODE(t0) # jump to next instruction
2040
2041
2042/* ------------------------------ */
2043 .balign 128
2044.L_op_if_nez: /* 0x39 */
2045/* File: mips/op_if_nez.S */
2046/* File: mips/zcmp.S */
2047 /*
2048 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2049 * fragment that specifies the *reverse* comparison to perform, e.g.
2050 * for "if-le" you would use "gt".
2051 *
2052 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2053 */
2054 /* if-cmp vAA, +BBBB */
2055 GET_OPA(a0) # a0 <- AA
2056 GET_VREG(a2, a0) # a2 <- vAA
2057 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2058 beq a2, zero, 1f # branch to 1 if comparison failed
2059 b 2f
20601:
2061 li rINST, 2 # rINST- BYTE branch dist for not-taken
20622:
2063#if MTERP_PROFILE_BRANCHES
2064 EXPORT_PC()
2065 move a0, rSELF
2066 addu a1, rFP, OFF_FP_SHADOWFRAME
2067 move a2, rINST
2068 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2069 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2070#endif
2071 addu a1, rINST, rINST # convert to bytes
2072 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2073 bgez a1, 3f
2074 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2075 b MterpCheckSuspendAndContinue
20763:
2077 GET_INST_OPCODE(t0) # extract opcode from rINST
2078 GOTO_OPCODE(t0) # jump to next instruction
2079
2080
2081/* ------------------------------ */
2082 .balign 128
2083.L_op_if_ltz: /* 0x3a */
2084/* File: mips/op_if_ltz.S */
2085/* File: mips/zcmp.S */
2086 /*
2087 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2088 * fragment that specifies the *reverse* comparison to perform, e.g.
2089 * for "if-le" you would use "gt".
2090 *
2091 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2092 */
2093 /* if-cmp vAA, +BBBB */
2094 GET_OPA(a0) # a0 <- AA
2095 GET_VREG(a2, a0) # a2 <- vAA
2096 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2097 bge a2, zero, 1f # branch to 1 if comparison failed
2098 b 2f
20991:
2100 li rINST, 2 # rINST- BYTE branch dist for not-taken
21012:
2102#if MTERP_PROFILE_BRANCHES
2103 EXPORT_PC()
2104 move a0, rSELF
2105 addu a1, rFP, OFF_FP_SHADOWFRAME
2106 move a2, rINST
2107 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2108 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2109#endif
2110 addu a1, rINST, rINST # convert to bytes
2111 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2112 bgez a1, 3f
2113 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2114 b MterpCheckSuspendAndContinue
21153:
2116 GET_INST_OPCODE(t0) # extract opcode from rINST
2117 GOTO_OPCODE(t0) # jump to next instruction
2118
2119
2120/* ------------------------------ */
2121 .balign 128
2122.L_op_if_gez: /* 0x3b */
2123/* File: mips/op_if_gez.S */
2124/* File: mips/zcmp.S */
2125 /*
2126 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2127 * fragment that specifies the *reverse* comparison to perform, e.g.
2128 * for "if-le" you would use "gt".
2129 *
2130 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2131 */
2132 /* if-cmp vAA, +BBBB */
2133 GET_OPA(a0) # a0 <- AA
2134 GET_VREG(a2, a0) # a2 <- vAA
2135 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2136 blt a2, zero, 1f # branch to 1 if comparison failed
2137 b 2f
21381:
2139 li rINST, 2 # rINST- BYTE branch dist for not-taken
21402:
2141#if MTERP_PROFILE_BRANCHES
2142 EXPORT_PC()
2143 move a0, rSELF
2144 addu a1, rFP, OFF_FP_SHADOWFRAME
2145 move a2, rINST
2146 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2147 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2148#endif
2149 addu a1, rINST, rINST # convert to bytes
2150 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2151 bgez a1, 3f
2152 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2153 b MterpCheckSuspendAndContinue
21543:
2155 GET_INST_OPCODE(t0) # extract opcode from rINST
2156 GOTO_OPCODE(t0) # jump to next instruction
2157
2158
2159/* ------------------------------ */
2160 .balign 128
2161.L_op_if_gtz: /* 0x3c */
2162/* File: mips/op_if_gtz.S */
2163/* File: mips/zcmp.S */
2164 /*
2165 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2166 * fragment that specifies the *reverse* comparison to perform, e.g.
2167 * for "if-le" you would use "gt".
2168 *
2169 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2170 */
2171 /* if-cmp vAA, +BBBB */
2172 GET_OPA(a0) # a0 <- AA
2173 GET_VREG(a2, a0) # a2 <- vAA
2174 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2175 ble a2, zero, 1f # branch to 1 if comparison failed
2176 b 2f
21771:
2178 li rINST, 2 # rINST- BYTE branch dist for not-taken
21792:
2180#if MTERP_PROFILE_BRANCHES
2181 EXPORT_PC()
2182 move a0, rSELF
2183 addu a1, rFP, OFF_FP_SHADOWFRAME
2184 move a2, rINST
2185 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2186 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2187#endif
2188 addu a1, rINST, rINST # convert to bytes
2189 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2190 bgez a1, 3f
2191 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2192 b MterpCheckSuspendAndContinue
21933:
2194 GET_INST_OPCODE(t0) # extract opcode from rINST
2195 GOTO_OPCODE(t0) # jump to next instruction
2196
2197
2198/* ------------------------------ */
2199 .balign 128
2200.L_op_if_lez: /* 0x3d */
2201/* File: mips/op_if_lez.S */
2202/* File: mips/zcmp.S */
2203 /*
2204 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
2205 * fragment that specifies the *reverse* comparison to perform, e.g.
2206 * for "if-le" you would use "gt".
2207 *
2208 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
2209 */
2210 /* if-cmp vAA, +BBBB */
2211 GET_OPA(a0) # a0 <- AA
2212 GET_VREG(a2, a0) # a2 <- vAA
2213 FETCH_S(rINST, 1) # rINST <- branch offset, in code units
2214 bgt a2, zero, 1f # branch to 1 if comparison failed
2215 b 2f
22161:
2217 li rINST, 2 # rINST- BYTE branch dist for not-taken
22182:
2219#if MTERP_PROFILE_BRANCHES
2220 EXPORT_PC()
2221 move a0, rSELF
2222 addu a1, rFP, OFF_FP_SHADOWFRAME
2223 move a2, rINST
2224 JAL(MterpProfileBranch) # (self, shadow_frame, offset)
2225 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST
2226#endif
2227 addu a1, rINST, rINST # convert to bytes
2228 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST
2229 bgez a1, 3f
2230 lw ra, THREAD_FLAGS_OFFSET(rSELF)
2231 b MterpCheckSuspendAndContinue
22323:
2233 GET_INST_OPCODE(t0) # extract opcode from rINST
2234 GOTO_OPCODE(t0) # jump to next instruction
2235
2236
2237/* ------------------------------ */
2238 .balign 128
2239.L_op_unused_3e: /* 0x3e */
2240/* File: mips/op_unused_3e.S */
2241/* File: mips/unused.S */
2242/*
2243 * Bail to reference interpreter to throw.
2244 */
2245 b MterpFallback
2246
2247
2248/* ------------------------------ */
2249 .balign 128
2250.L_op_unused_3f: /* 0x3f */
2251/* File: mips/op_unused_3f.S */
2252/* File: mips/unused.S */
2253/*
2254 * Bail to reference interpreter to throw.
2255 */
2256 b MterpFallback
2257
2258
2259/* ------------------------------ */
2260 .balign 128
2261.L_op_unused_40: /* 0x40 */
2262/* File: mips/op_unused_40.S */
2263/* File: mips/unused.S */
2264/*
2265 * Bail to reference interpreter to throw.
2266 */
2267 b MterpFallback
2268
2269
2270/* ------------------------------ */
2271 .balign 128
2272.L_op_unused_41: /* 0x41 */
2273/* File: mips/op_unused_41.S */
2274/* File: mips/unused.S */
2275/*
2276 * Bail to reference interpreter to throw.
2277 */
2278 b MterpFallback
2279
2280
2281/* ------------------------------ */
2282 .balign 128
2283.L_op_unused_42: /* 0x42 */
2284/* File: mips/op_unused_42.S */
2285/* File: mips/unused.S */
2286/*
2287 * Bail to reference interpreter to throw.
2288 */
2289 b MterpFallback
2290
2291
2292/* ------------------------------ */
2293 .balign 128
2294.L_op_unused_43: /* 0x43 */
2295/* File: mips/op_unused_43.S */
2296/* File: mips/unused.S */
2297/*
2298 * Bail to reference interpreter to throw.
2299 */
2300 b MterpFallback
2301
2302
2303/* ------------------------------ */
2304 .balign 128
2305.L_op_aget: /* 0x44 */
2306/* File: mips/op_aget.S */
2307 /*
2308 * Array get, 32 bits or less. vAA <- vBB[vCC].
2309 *
2310 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2311 * instructions. We use a pair of FETCH_Bs instead.
2312 *
2313 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2314 *
2315 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2316 * If this changes, specialize.
2317 */
2318 /* op vAA, vBB, vCC */
2319 FETCH_B(a2, 1, 0) # a2 <- BB
2320 GET_OPA(rOBJ) # rOBJ <- AA
2321 FETCH_B(a3, 1, 1) # a3 <- CC
2322 GET_VREG(a0, a2) # a0 <- vBB (array object)
2323 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2324 # null array object?
2325 beqz a0, common_errNullObject # yes, bail
2326 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2327 .if 2
2328 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width
2329 .else
2330 addu a0, a0, a1
2331 .endif
2332 # a1 >= a3; compare unsigned index
2333 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2334 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2335 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2336 GET_INST_OPCODE(t0) # extract opcode from rINST
2337 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2
2338
2339/* ------------------------------ */
2340 .balign 128
2341.L_op_aget_wide: /* 0x45 */
2342/* File: mips/op_aget_wide.S */
2343 /*
2344 * Array get, 64 bits. vAA <- vBB[vCC].
2345 *
2346 * Arrays of long/double are 64-bit aligned.
2347 */
2348 /* aget-wide vAA, vBB, vCC */
2349 FETCH(a0, 1) # a0 <- CCBB
2350 GET_OPA(rOBJ) # rOBJ <- AA
2351 and a2, a0, 255 # a2 <- BB
2352 srl a3, a0, 8 # a3 <- CC
2353 GET_VREG(a0, a2) # a0 <- vBB (array object)
2354 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2355 # null array object?
2356 beqz a0, common_errNullObject # yes, bail
2357 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2358 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
2359 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2360
2361 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2362 LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET)
2363 GET_INST_OPCODE(t0) # extract opcode from rINST
2364 SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3
2365
2366/* ------------------------------ */
2367 .balign 128
2368.L_op_aget_object: /* 0x46 */
2369/* File: mips/op_aget_object.S */
2370 /*
2371 * Array object get. vAA <- vBB[vCC].
2372 *
2373 * for: aget-object
2374 */
2375 /* op vAA, vBB, vCC */
2376 FETCH_B(a2, 1, 0) # a2 <- BB
2377 GET_OPA(rOBJ) # rOBJ <- AA
2378 FETCH_B(a3, 1, 1) # a3 <- CC
2379 EXPORT_PC()
2380 GET_VREG(a0, a2) # a0 <- vBB (array object)
2381 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2382 JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index)
2383 lw a1, THREAD_EXCEPTION_OFFSET(rSELF)
2384 PREFETCH_INST(2) # load rINST
2385 bnez a1, MterpException
2386 SET_VREG_OBJECT(v0, rOBJ) # vAA <- v0
2387 ADVANCE(2) # advance rPC
2388 GET_INST_OPCODE(t0) # extract opcode from rINST
2389 GOTO_OPCODE(t0) # jump to next instruction
2390
2391/* ------------------------------ */
2392 .balign 128
2393.L_op_aget_boolean: /* 0x47 */
2394/* File: mips/op_aget_boolean.S */
2395/* File: mips/op_aget.S */
2396 /*
2397 * Array get, 32 bits or less. vAA <- vBB[vCC].
2398 *
2399 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2400 * instructions. We use a pair of FETCH_Bs instead.
2401 *
2402 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2403 *
2404 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2405 * If this changes, specialize.
2406 */
2407 /* op vAA, vBB, vCC */
2408 FETCH_B(a2, 1, 0) # a2 <- BB
2409 GET_OPA(rOBJ) # rOBJ <- AA
2410 FETCH_B(a3, 1, 1) # a3 <- CC
2411 GET_VREG(a0, a2) # a0 <- vBB (array object)
2412 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2413 # null array object?
2414 beqz a0, common_errNullObject # yes, bail
2415 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2416 .if 0
2417 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2418 .else
2419 addu a0, a0, a1
2420 .endif
2421 # a1 >= a3; compare unsigned index
2422 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2423 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2424 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2425 GET_INST_OPCODE(t0) # extract opcode from rINST
2426 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2
2427
2428
2429/* ------------------------------ */
2430 .balign 128
2431.L_op_aget_byte: /* 0x48 */
2432/* File: mips/op_aget_byte.S */
2433/* File: mips/op_aget.S */
2434 /*
2435 * Array get, 32 bits or less. vAA <- vBB[vCC].
2436 *
2437 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2438 * instructions. We use a pair of FETCH_Bs instead.
2439 *
2440 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2441 *
2442 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2443 * If this changes, specialize.
2444 */
2445 /* op vAA, vBB, vCC */
2446 FETCH_B(a2, 1, 0) # a2 <- BB
2447 GET_OPA(rOBJ) # rOBJ <- AA
2448 FETCH_B(a3, 1, 1) # a3 <- CC
2449 GET_VREG(a0, a2) # a0 <- vBB (array object)
2450 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2451 # null array object?
2452 beqz a0, common_errNullObject # yes, bail
2453 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2454 .if 0
2455 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2456 .else
2457 addu a0, a0, a1
2458 .endif
2459 # a1 >= a3; compare unsigned index
2460 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2461 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2462 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2463 GET_INST_OPCODE(t0) # extract opcode from rINST
2464 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2
2465
2466
2467/* ------------------------------ */
2468 .balign 128
2469.L_op_aget_char: /* 0x49 */
2470/* File: mips/op_aget_char.S */
2471/* File: mips/op_aget.S */
2472 /*
2473 * Array get, 32 bits or less. vAA <- vBB[vCC].
2474 *
2475 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2476 * instructions. We use a pair of FETCH_Bs instead.
2477 *
2478 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2479 *
2480 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2481 * If this changes, specialize.
2482 */
2483 /* op vAA, vBB, vCC */
2484 FETCH_B(a2, 1, 0) # a2 <- BB
2485 GET_OPA(rOBJ) # rOBJ <- AA
2486 FETCH_B(a3, 1, 1) # a3 <- CC
2487 GET_VREG(a0, a2) # a0 <- vBB (array object)
2488 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2489 # null array object?
2490 beqz a0, common_errNullObject # yes, bail
2491 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2492 .if 1
2493 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2494 .else
2495 addu a0, a0, a1
2496 .endif
2497 # a1 >= a3; compare unsigned index
2498 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2499 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2500 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2501 GET_INST_OPCODE(t0) # extract opcode from rINST
2502 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2
2503
2504
2505/* ------------------------------ */
2506 .balign 128
2507.L_op_aget_short: /* 0x4a */
2508/* File: mips/op_aget_short.S */
2509/* File: mips/op_aget.S */
2510 /*
2511 * Array get, 32 bits or less. vAA <- vBB[vCC].
2512 *
2513 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2514 * instructions. We use a pair of FETCH_Bs instead.
2515 *
2516 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2517 *
2518 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2519 * If this changes, specialize.
2520 */
2521 /* op vAA, vBB, vCC */
2522 FETCH_B(a2, 1, 0) # a2 <- BB
2523 GET_OPA(rOBJ) # rOBJ <- AA
2524 FETCH_B(a3, 1, 1) # a3 <- CC
2525 GET_VREG(a0, a2) # a0 <- vBB (array object)
2526 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2527 # null array object?
2528 beqz a0, common_errNullObject # yes, bail
2529 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2530 .if 1
2531 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2532 .else
2533 addu a0, a0, a1
2534 .endif
2535 # a1 >= a3; compare unsigned index
2536 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2537 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2538 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2539 GET_INST_OPCODE(t0) # extract opcode from rINST
2540 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2
2541
2542
2543/* ------------------------------ */
2544 .balign 128
2545.L_op_aput: /* 0x4b */
2546/* File: mips/op_aput.S */
2547
2548 /*
2549 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2550 *
2551 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2552 *
2553 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2554 * If this changes, specialize.
2555 */
2556 /* op vAA, vBB, vCC */
2557 FETCH_B(a2, 1, 0) # a2 <- BB
2558 GET_OPA(rOBJ) # rOBJ <- AA
2559 FETCH_B(a3, 1, 1) # a3 <- CC
2560 GET_VREG(a0, a2) # a0 <- vBB (array object)
2561 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2562 # null array object?
2563 beqz a0, common_errNullObject # yes, bail
2564 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2565 .if 2
2566 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width
2567 .else
2568 addu a0, a0, a1
2569 .endif
2570 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2571 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2572 GET_VREG(a2, rOBJ) # a2 <- vAA
2573 GET_INST_OPCODE(t0) # extract opcode from rINST
2574 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2575 GOTO_OPCODE(t0) # jump to next instruction
2576
2577/* ------------------------------ */
2578 .balign 128
2579.L_op_aput_wide: /* 0x4c */
2580/* File: mips/op_aput_wide.S */
2581 /*
2582 * Array put, 64 bits. vBB[vCC] <- vAA.
2583 *
2584 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2585 */
2586 /* aput-wide vAA, vBB, vCC */
2587 FETCH(a0, 1) # a0 <- CCBB
2588 GET_OPA(t0) # t0 <- AA
2589 and a2, a0, 255 # a2 <- BB
2590 srl a3, a0, 8 # a3 <- CC
2591 GET_VREG(a0, a2) # a0 <- vBB (array object)
2592 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2593 # null array object?
2594 beqz a0, common_errNullObject # yes, bail
2595 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2596 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width
2597 EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA]
2598 # compare unsigned index, length
2599 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2600
2601 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2602 LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1
2603 GET_INST_OPCODE(t0) # extract opcode from rINST
2604 STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC]
2605 GOTO_OPCODE(t0) # jump to next instruction
2606
2607/* ------------------------------ */
2608 .balign 128
2609.L_op_aput_object: /* 0x4d */
2610/* File: mips/op_aput_object.S */
2611 /*
2612 * Store an object into an array. vBB[vCC] <- vAA.
2613 *
2614 */
2615 /* op vAA, vBB, vCC */
2616 EXPORT_PC()
2617 addu a0, rFP, OFF_FP_SHADOWFRAME
2618 move a1, rPC
2619 move a2, rINST
2620 JAL(MterpAputObject)
2621 beqz v0, MterpPossibleException
2622 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2623 GET_INST_OPCODE(t0) # extract opcode from rINST
2624 GOTO_OPCODE(t0) # jump to next instruction
2625
2626/* ------------------------------ */
2627 .balign 128
2628.L_op_aput_boolean: /* 0x4e */
2629/* File: mips/op_aput_boolean.S */
2630/* File: mips/op_aput.S */
2631
2632 /*
2633 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2634 *
2635 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2636 *
2637 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2638 * If this changes, specialize.
2639 */
2640 /* op vAA, vBB, vCC */
2641 FETCH_B(a2, 1, 0) # a2 <- BB
2642 GET_OPA(rOBJ) # rOBJ <- AA
2643 FETCH_B(a3, 1, 1) # a3 <- CC
2644 GET_VREG(a0, a2) # a0 <- vBB (array object)
2645 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2646 # null array object?
2647 beqz a0, common_errNullObject # yes, bail
2648 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2649 .if 0
2650 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2651 .else
2652 addu a0, a0, a1
2653 .endif
2654 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2655 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2656 GET_VREG(a2, rOBJ) # a2 <- vAA
2657 GET_INST_OPCODE(t0) # extract opcode from rINST
2658 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2659 GOTO_OPCODE(t0) # jump to next instruction
2660
2661
2662/* ------------------------------ */
2663 .balign 128
2664.L_op_aput_byte: /* 0x4f */
2665/* File: mips/op_aput_byte.S */
2666/* File: mips/op_aput.S */
2667
2668 /*
2669 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2670 *
2671 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2672 *
2673 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2674 * If this changes, specialize.
2675 */
2676 /* op vAA, vBB, vCC */
2677 FETCH_B(a2, 1, 0) # a2 <- BB
2678 GET_OPA(rOBJ) # rOBJ <- AA
2679 FETCH_B(a3, 1, 1) # a3 <- CC
2680 GET_VREG(a0, a2) # a0 <- vBB (array object)
2681 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2682 # null array object?
2683 beqz a0, common_errNullObject # yes, bail
2684 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2685 .if 0
2686 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width
2687 .else
2688 addu a0, a0, a1
2689 .endif
2690 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2691 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2692 GET_VREG(a2, rOBJ) # a2 <- vAA
2693 GET_INST_OPCODE(t0) # extract opcode from rINST
2694 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2695 GOTO_OPCODE(t0) # jump to next instruction
2696
2697
2698/* ------------------------------ */
2699 .balign 128
2700.L_op_aput_char: /* 0x50 */
2701/* File: mips/op_aput_char.S */
2702/* File: mips/op_aput.S */
2703
2704 /*
2705 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2706 *
2707 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2708 *
2709 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2710 * If this changes, specialize.
2711 */
2712 /* op vAA, vBB, vCC */
2713 FETCH_B(a2, 1, 0) # a2 <- BB
2714 GET_OPA(rOBJ) # rOBJ <- AA
2715 FETCH_B(a3, 1, 1) # a3 <- CC
2716 GET_VREG(a0, a2) # a0 <- vBB (array object)
2717 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2718 # null array object?
2719 beqz a0, common_errNullObject # yes, bail
2720 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2721 .if 1
2722 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2723 .else
2724 addu a0, a0, a1
2725 .endif
2726 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2727 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2728 GET_VREG(a2, rOBJ) # a2 <- vAA
2729 GET_INST_OPCODE(t0) # extract opcode from rINST
2730 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2731 GOTO_OPCODE(t0) # jump to next instruction
2732
2733
2734/* ------------------------------ */
2735 .balign 128
2736.L_op_aput_short: /* 0x51 */
2737/* File: mips/op_aput_short.S */
2738/* File: mips/op_aput.S */
2739
2740 /*
2741 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2742 *
2743 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2744 *
2745 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2746 * If this changes, specialize.
2747 */
2748 /* op vAA, vBB, vCC */
2749 FETCH_B(a2, 1, 0) # a2 <- BB
2750 GET_OPA(rOBJ) # rOBJ <- AA
2751 FETCH_B(a3, 1, 1) # a3 <- CC
2752 GET_VREG(a0, a2) # a0 <- vBB (array object)
2753 GET_VREG(a1, a3) # a1 <- vCC (requested index)
2754 # null array object?
2755 beqz a0, common_errNullObject # yes, bail
2756 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
2757 .if 1
2758 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width
2759 .else
2760 addu a0, a0, a1
2761 .endif
2762 bgeu a1, a3, common_errArrayIndex # index >= length, bail
2763 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
2764 GET_VREG(a2, rOBJ) # a2 <- vAA
2765 GET_INST_OPCODE(t0) # extract opcode from rINST
2766 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2767 GOTO_OPCODE(t0) # jump to next instruction
2768
2769
2770/* ------------------------------ */
2771 .balign 128
2772.L_op_iget: /* 0x52 */
2773/* File: mips/op_iget.S */
2774 /*
2775 * General instance field get.
2776 *
2777 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2778 */
2779 EXPORT_PC()
2780 FETCH(a0, 1) # a0 <- field ref CCCC
2781 GET_OPB(a1) # a1 <- B
2782 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2783 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2784 move a3, rSELF # a3 <- self
2785 JAL(artGet32InstanceFromCode)
2786 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2787 GET_OPA4(a2) # a2<- A+
2788 PREFETCH_INST(2) # load rINST
2789 bnez a3, MterpPossibleException # bail out
2790 .if 0
2791 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2792 .else
2793 SET_VREG(v0, a2) # fp[A] <- v0
2794 .endif
2795 ADVANCE(2) # advance rPC
2796 GET_INST_OPCODE(t0) # extract opcode from rINST
2797 GOTO_OPCODE(t0) # jump to next instruction
2798
2799/* ------------------------------ */
2800 .balign 128
2801.L_op_iget_wide: /* 0x53 */
2802/* File: mips/op_iget_wide.S */
2803 /*
2804 * 64-bit instance field get.
2805 *
2806 * for: iget-wide
2807 */
2808 EXPORT_PC()
2809 FETCH(a0, 1) # a0 <- field byte offset
2810 GET_OPB(a1) # a1 <- B
2811 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2812 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2813 move a3, rSELF # a3 <- self
2814 JAL(artGet64InstanceFromCode)
2815 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2816 GET_OPA4(a2) # a2<- A+
2817 PREFETCH_INST(2) # load rINST
2818 bnez a3, MterpException # bail out
2819 SET_VREG64(v0, v1, a2) # fp[A] <- v0/v1
2820 ADVANCE(2) # advance rPC
2821 GET_INST_OPCODE(t0) # extract opcode from rINST
2822 GOTO_OPCODE(t0) # jump to next instruction
2823
2824/* ------------------------------ */
2825 .balign 128
2826.L_op_iget_object: /* 0x54 */
2827/* File: mips/op_iget_object.S */
2828/* File: mips/op_iget.S */
2829 /*
2830 * General instance field get.
2831 *
2832 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2833 */
2834 EXPORT_PC()
2835 FETCH(a0, 1) # a0 <- field ref CCCC
2836 GET_OPB(a1) # a1 <- B
2837 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2838 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2839 move a3, rSELF # a3 <- self
2840 JAL(artGetObjInstanceFromCode)
2841 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2842 GET_OPA4(a2) # a2<- A+
2843 PREFETCH_INST(2) # load rINST
2844 bnez a3, MterpPossibleException # bail out
2845 .if 1
2846 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2847 .else
2848 SET_VREG(v0, a2) # fp[A] <- v0
2849 .endif
2850 ADVANCE(2) # advance rPC
2851 GET_INST_OPCODE(t0) # extract opcode from rINST
2852 GOTO_OPCODE(t0) # jump to next instruction
2853
2854
2855/* ------------------------------ */
2856 .balign 128
2857.L_op_iget_boolean: /* 0x55 */
2858/* File: mips/op_iget_boolean.S */
2859/* File: mips/op_iget.S */
2860 /*
2861 * General instance field get.
2862 *
2863 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2864 */
2865 EXPORT_PC()
2866 FETCH(a0, 1) # a0 <- field ref CCCC
2867 GET_OPB(a1) # a1 <- B
2868 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2869 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2870 move a3, rSELF # a3 <- self
2871 JAL(artGetBooleanInstanceFromCode)
2872 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2873 GET_OPA4(a2) # a2<- A+
2874 PREFETCH_INST(2) # load rINST
2875 bnez a3, MterpPossibleException # bail out
2876 .if 0
2877 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2878 .else
2879 SET_VREG(v0, a2) # fp[A] <- v0
2880 .endif
2881 ADVANCE(2) # advance rPC
2882 GET_INST_OPCODE(t0) # extract opcode from rINST
2883 GOTO_OPCODE(t0) # jump to next instruction
2884
2885
2886/* ------------------------------ */
2887 .balign 128
2888.L_op_iget_byte: /* 0x56 */
2889/* File: mips/op_iget_byte.S */
2890/* File: mips/op_iget.S */
2891 /*
2892 * General instance field get.
2893 *
2894 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2895 */
2896 EXPORT_PC()
2897 FETCH(a0, 1) # a0 <- field ref CCCC
2898 GET_OPB(a1) # a1 <- B
2899 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2900 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2901 move a3, rSELF # a3 <- self
2902 JAL(artGetByteInstanceFromCode)
2903 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2904 GET_OPA4(a2) # a2<- A+
2905 PREFETCH_INST(2) # load rINST
2906 bnez a3, MterpPossibleException # bail out
2907 .if 0
2908 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2909 .else
2910 SET_VREG(v0, a2) # fp[A] <- v0
2911 .endif
2912 ADVANCE(2) # advance rPC
2913 GET_INST_OPCODE(t0) # extract opcode from rINST
2914 GOTO_OPCODE(t0) # jump to next instruction
2915
2916
2917/* ------------------------------ */
2918 .balign 128
2919.L_op_iget_char: /* 0x57 */
2920/* File: mips/op_iget_char.S */
2921/* File: mips/op_iget.S */
2922 /*
2923 * General instance field get.
2924 *
2925 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2926 */
2927 EXPORT_PC()
2928 FETCH(a0, 1) # a0 <- field ref CCCC
2929 GET_OPB(a1) # a1 <- B
2930 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2931 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2932 move a3, rSELF # a3 <- self
2933 JAL(artGetCharInstanceFromCode)
2934 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2935 GET_OPA4(a2) # a2<- A+
2936 PREFETCH_INST(2) # load rINST
2937 bnez a3, MterpPossibleException # bail out
2938 .if 0
2939 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2940 .else
2941 SET_VREG(v0, a2) # fp[A] <- v0
2942 .endif
2943 ADVANCE(2) # advance rPC
2944 GET_INST_OPCODE(t0) # extract opcode from rINST
2945 GOTO_OPCODE(t0) # jump to next instruction
2946
2947
2948/* ------------------------------ */
2949 .balign 128
2950.L_op_iget_short: /* 0x58 */
2951/* File: mips/op_iget_short.S */
2952/* File: mips/op_iget.S */
2953 /*
2954 * General instance field get.
2955 *
2956 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2957 */
2958 EXPORT_PC()
2959 FETCH(a0, 1) # a0 <- field ref CCCC
2960 GET_OPB(a1) # a1 <- B
2961 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2962 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2963 move a3, rSELF # a3 <- self
2964 JAL(artGetShortInstanceFromCode)
2965 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
2966 GET_OPA4(a2) # a2<- A+
2967 PREFETCH_INST(2) # load rINST
2968 bnez a3, MterpPossibleException # bail out
2969 .if 0
2970 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
2971 .else
2972 SET_VREG(v0, a2) # fp[A] <- v0
2973 .endif
2974 ADVANCE(2) # advance rPC
2975 GET_INST_OPCODE(t0) # extract opcode from rINST
2976 GOTO_OPCODE(t0) # jump to next instruction
2977
2978
2979/* ------------------------------ */
2980 .balign 128
2981.L_op_iput: /* 0x59 */
2982/* File: mips/op_iput.S */
2983 /*
2984 * General 32-bit instance field put.
2985 *
2986 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2987 */
2988 # op vA, vB, field /* CCCC */
2989 .extern artSet32InstanceFromMterp
2990 EXPORT_PC()
2991 FETCH(a0, 1) # a0 <- field ref CCCC
2992 GET_OPB(a1) # a1 <- B
2993 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
2994 GET_OPA4(a2) # a2 <- A+
2995 GET_VREG(a2, a2) # a2 <- fp[A]
2996 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2997 PREFETCH_INST(2) # load rINST
2998 JAL(artSet32InstanceFromMterp)
2999 bnez v0, MterpPossibleException # bail out
3000 ADVANCE(2) # advance rPC
3001 GET_INST_OPCODE(t0) # extract opcode from rINST
3002 GOTO_OPCODE(t0) # jump to next instruction
3003
3004/* ------------------------------ */
3005 .balign 128
3006.L_op_iput_wide: /* 0x5a */
3007/* File: mips/op_iput_wide.S */
3008 # iput-wide vA, vB, field /* CCCC */
3009 .extern artSet64InstanceFromMterp
3010 EXPORT_PC()
3011 FETCH(a0, 1) # a0 <- field ref CCCC
3012 GET_OPB(a1) # a1 <- B
3013 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
3014 GET_OPA4(a2) # a2 <- A+
3015 EAS2(a2, rFP, a2) # a2 <- &fp[A]
3016 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
3017 PREFETCH_INST(2) # load rINST
3018 JAL(artSet64InstanceFromMterp)
3019 bnez v0, MterpPossibleException # bail out
3020 ADVANCE(2) # advance rPC
3021 GET_INST_OPCODE(t0) # extract opcode from rINST
3022 GOTO_OPCODE(t0) # jump to next instruction
3023
3024/* ------------------------------ */
3025 .balign 128
3026.L_op_iput_object: /* 0x5b */
3027/* File: mips/op_iput_object.S */
3028 /*
3029 * 32-bit instance field put.
3030 *
3031 * for: iput-object, iput-object-volatile
3032 */
3033 # op vA, vB, field /* CCCC */
3034 EXPORT_PC()
3035 addu a0, rFP, OFF_FP_SHADOWFRAME
3036 move a1, rPC
3037 move a2, rINST
3038 move a3, rSELF
3039 JAL(MterpIputObject)
3040 beqz v0, MterpException
3041 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
3042 GET_INST_OPCODE(t0) # extract opcode from rINST
3043 GOTO_OPCODE(t0) # jump to next instruction
3044
3045/* ------------------------------ */
3046 .balign 128
3047.L_op_iput_boolean: /* 0x5c */
3048/* File: mips/op_iput_boolean.S */
3049/* File: mips/op_iput.S */
3050 /*
3051 * General 32-bit instance field put.
3052 *
3053 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
3054 */
3055 # op vA, vB, field /* CCCC */
3056 .extern artSet8InstanceFromMterp
3057 EXPORT_PC()
3058 FETCH(a0, 1) # a0 <- field ref CCCC
3059 GET_OPB(a1) # a1 <- B
3060 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
3061 GET_OPA4(a2) # a2 <- A+
3062 GET_VREG(a2, a2) # a2 <- fp[A]
3063 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
3064 PREFETCH_INST(2) # load rINST
3065 JAL(artSet8InstanceFromMterp)
3066 bnez v0, MterpPossibleException # bail out
3067 ADVANCE(2) # advance rPC
3068 GET_INST_OPCODE(t0) # extract opcode from rINST
3069 GOTO_OPCODE(t0) # jump to next instruction
3070
3071
3072/* ------------------------------ */
3073 .balign 128
3074.L_op_iput_byte: /* 0x5d */
3075/* File: mips/op_iput_byte.S */
3076/* File: mips/op_iput.S */
3077 /*
3078 * General 32-bit instance field put.
3079 *
3080 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
3081 */
3082 # op vA, vB, field /* CCCC */
3083 .extern artSet8InstanceFromMterp
3084 EXPORT_PC()
3085 FETCH(a0, 1) # a0 <- field ref CCCC
3086 GET_OPB(a1) # a1 <- B
3087 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
3088 GET_OPA4(a2) # a2 <- A+
3089 GET_VREG(a2, a2) # a2 <- fp[A]
3090 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
3091 PREFETCH_INST(2) # load rINST
3092 JAL(artSet8InstanceFromMterp)
3093 bnez v0, MterpPossibleException # bail out
3094 ADVANCE(2) # advance rPC
3095 GET_INST_OPCODE(t0) # extract opcode from rINST
3096 GOTO_OPCODE(t0) # jump to next instruction
3097
3098
3099/* ------------------------------ */
3100 .balign 128
3101.L_op_iput_char: /* 0x5e */
3102/* File: mips/op_iput_char.S */
3103/* File: mips/op_iput.S */
3104 /*
3105 * General 32-bit instance field put.
3106 *
3107 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
3108 */
3109 # op vA, vB, field /* CCCC */
3110 .extern artSet16InstanceFromMterp
3111 EXPORT_PC()
3112 FETCH(a0, 1) # a0 <- field ref CCCC
3113 GET_OPB(a1) # a1 <- B
3114 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
3115 GET_OPA4(a2) # a2 <- A+
3116 GET_VREG(a2, a2) # a2 <- fp[A]
3117 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
3118 PREFETCH_INST(2) # load rINST
3119 JAL(artSet16InstanceFromMterp)
3120 bnez v0, MterpPossibleException # bail out
3121 ADVANCE(2) # advance rPC
3122 GET_INST_OPCODE(t0) # extract opcode from rINST
3123 GOTO_OPCODE(t0) # jump to next instruction
3124
3125
3126/* ------------------------------ */
3127 .balign 128
3128.L_op_iput_short: /* 0x5f */
3129/* File: mips/op_iput_short.S */
3130/* File: mips/op_iput.S */
3131 /*
3132 * General 32-bit instance field put.
3133 *
3134 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
3135 */
3136 # op vA, vB, field /* CCCC */
3137 .extern artSet16InstanceFromMterp
3138 EXPORT_PC()
3139 FETCH(a0, 1) # a0 <- field ref CCCC
3140 GET_OPB(a1) # a1 <- B
3141 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer
3142 GET_OPA4(a2) # a2 <- A+
3143 GET_VREG(a2, a2) # a2 <- fp[A]
3144 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer
3145 PREFETCH_INST(2) # load rINST
3146 JAL(artSet16InstanceFromMterp)
3147 bnez v0, MterpPossibleException # bail out
3148 ADVANCE(2) # advance rPC
3149 GET_INST_OPCODE(t0) # extract opcode from rINST
3150 GOTO_OPCODE(t0) # jump to next instruction
3151
3152
3153/* ------------------------------ */
3154 .balign 128
3155.L_op_sget: /* 0x60 */
3156/* File: mips/op_sget.S */
3157 /*
3158 * General SGET handler.
3159 *
3160 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3161 */
3162 # op vAA, field /* BBBB */
3163 .extern artGet32StaticFromCode
3164 EXPORT_PC()
3165 FETCH(a0, 1) # a0 <- field ref BBBB
3166 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3167 move a2, rSELF # a2 <- self
3168 JAL(artGet32StaticFromCode)
3169 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3170 GET_OPA(a2) # a2 <- AA
3171 PREFETCH_INST(2)
3172 bnez a3, MterpException # bail out
3173.if 0
3174 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3175.else
3176 SET_VREG(v0, a2) # fp[AA] <- v0
3177.endif
3178 ADVANCE(2)
3179 GET_INST_OPCODE(t0) # extract opcode from rINST
3180 GOTO_OPCODE(t0) # jump to next instruction
3181
3182/* ------------------------------ */
3183 .balign 128
3184.L_op_sget_wide: /* 0x61 */
3185/* File: mips/op_sget_wide.S */
3186 /*
3187 * 64-bit SGET handler.
3188 */
3189 # sget-wide vAA, field /* BBBB */
3190 .extern artGet64StaticFromCode
3191 EXPORT_PC()
3192 FETCH(a0, 1) # a0 <- field ref BBBB
3193 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3194 move a2, rSELF # a2 <- self
3195 JAL(artGet64StaticFromCode)
3196 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3197 bnez a3, MterpException
3198 GET_OPA(a1) # a1 <- AA
3199 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
3200 SET_VREG64(v0, v1, a1) # vAA/vAA+1 <- v0/v1
3201 GET_INST_OPCODE(t0) # extract opcode from rINST
3202 GOTO_OPCODE(t0) # jump to next instruction
3203
3204/* ------------------------------ */
3205 .balign 128
3206.L_op_sget_object: /* 0x62 */
3207/* File: mips/op_sget_object.S */
3208/* File: mips/op_sget.S */
3209 /*
3210 * General SGET handler.
3211 *
3212 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3213 */
3214 # op vAA, field /* BBBB */
3215 .extern artGetObjStaticFromCode
3216 EXPORT_PC()
3217 FETCH(a0, 1) # a0 <- field ref BBBB
3218 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3219 move a2, rSELF # a2 <- self
3220 JAL(artGetObjStaticFromCode)
3221 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3222 GET_OPA(a2) # a2 <- AA
3223 PREFETCH_INST(2)
3224 bnez a3, MterpException # bail out
3225.if 1
3226 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3227.else
3228 SET_VREG(v0, a2) # fp[AA] <- v0
3229.endif
3230 ADVANCE(2)
3231 GET_INST_OPCODE(t0) # extract opcode from rINST
3232 GOTO_OPCODE(t0) # jump to next instruction
3233
3234
3235/* ------------------------------ */
3236 .balign 128
3237.L_op_sget_boolean: /* 0x63 */
3238/* File: mips/op_sget_boolean.S */
3239/* File: mips/op_sget.S */
3240 /*
3241 * General SGET handler.
3242 *
3243 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3244 */
3245 # op vAA, field /* BBBB */
3246 .extern artGetBooleanStaticFromCode
3247 EXPORT_PC()
3248 FETCH(a0, 1) # a0 <- field ref BBBB
3249 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3250 move a2, rSELF # a2 <- self
3251 JAL(artGetBooleanStaticFromCode)
3252 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3253 GET_OPA(a2) # a2 <- AA
3254 PREFETCH_INST(2)
3255 bnez a3, MterpException # bail out
3256.if 0
3257 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3258.else
3259 SET_VREG(v0, a2) # fp[AA] <- v0
3260.endif
3261 ADVANCE(2)
3262 GET_INST_OPCODE(t0) # extract opcode from rINST
3263 GOTO_OPCODE(t0) # jump to next instruction
3264
3265
3266/* ------------------------------ */
3267 .balign 128
3268.L_op_sget_byte: /* 0x64 */
3269/* File: mips/op_sget_byte.S */
3270/* File: mips/op_sget.S */
3271 /*
3272 * General SGET handler.
3273 *
3274 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3275 */
3276 # op vAA, field /* BBBB */
3277 .extern artGetByteStaticFromCode
3278 EXPORT_PC()
3279 FETCH(a0, 1) # a0 <- field ref BBBB
3280 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3281 move a2, rSELF # a2 <- self
3282 JAL(artGetByteStaticFromCode)
3283 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3284 GET_OPA(a2) # a2 <- AA
3285 PREFETCH_INST(2)
3286 bnez a3, MterpException # bail out
3287.if 0
3288 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3289.else
3290 SET_VREG(v0, a2) # fp[AA] <- v0
3291.endif
3292 ADVANCE(2)
3293 GET_INST_OPCODE(t0) # extract opcode from rINST
3294 GOTO_OPCODE(t0) # jump to next instruction
3295
3296
3297/* ------------------------------ */
3298 .balign 128
3299.L_op_sget_char: /* 0x65 */
3300/* File: mips/op_sget_char.S */
3301/* File: mips/op_sget.S */
3302 /*
3303 * General SGET handler.
3304 *
3305 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3306 */
3307 # op vAA, field /* BBBB */
3308 .extern artGetCharStaticFromCode
3309 EXPORT_PC()
3310 FETCH(a0, 1) # a0 <- field ref BBBB
3311 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3312 move a2, rSELF # a2 <- self
3313 JAL(artGetCharStaticFromCode)
3314 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3315 GET_OPA(a2) # a2 <- AA
3316 PREFETCH_INST(2)
3317 bnez a3, MterpException # bail out
3318.if 0
3319 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3320.else
3321 SET_VREG(v0, a2) # fp[AA] <- v0
3322.endif
3323 ADVANCE(2)
3324 GET_INST_OPCODE(t0) # extract opcode from rINST
3325 GOTO_OPCODE(t0) # jump to next instruction
3326
3327
3328/* ------------------------------ */
3329 .balign 128
3330.L_op_sget_short: /* 0x66 */
3331/* File: mips/op_sget_short.S */
3332/* File: mips/op_sget.S */
3333 /*
3334 * General SGET handler.
3335 *
3336 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
3337 */
3338 # op vAA, field /* BBBB */
3339 .extern artGetShortStaticFromCode
3340 EXPORT_PC()
3341 FETCH(a0, 1) # a0 <- field ref BBBB
3342 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3343 move a2, rSELF # a2 <- self
3344 JAL(artGetShortStaticFromCode)
3345 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
3346 GET_OPA(a2) # a2 <- AA
3347 PREFETCH_INST(2)
3348 bnez a3, MterpException # bail out
3349.if 0
3350 SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0
3351.else
3352 SET_VREG(v0, a2) # fp[AA] <- v0
3353.endif
3354 ADVANCE(2)
3355 GET_INST_OPCODE(t0) # extract opcode from rINST
3356 GOTO_OPCODE(t0) # jump to next instruction
3357
3358
3359/* ------------------------------ */
3360 .balign 128
3361.L_op_sput: /* 0x67 */
3362/* File: mips/op_sput.S */
3363 /*
3364 * General SPUT handler.
3365 *
3366 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3367 */
3368 # op vAA, field /* BBBB */
3369 EXPORT_PC()
3370 FETCH(a0, 1) # a0 <- field ref BBBB
3371 GET_OPA(a3) # a3 <- AA
3372 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer
3373 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
3374 move a3, rSELF # a3 <- self
3375 PREFETCH_INST(2) # load rINST
3376 JAL(artSet32StaticFromCode)
3377 bnez v0, MterpException # bail out
3378 ADVANCE(2) # advance rPC
3379 GET_INST_OPCODE(t0) # extract opcode from rINST
3380 GOTO_OPCODE(t0) # jump to next instruction
3381
3382/* ------------------------------ */
3383 .balign 128
3384.L_op_sput_wide: /* 0x68 */
3385/* File: mips/op_sput_wide.S */
3386 /*
3387 * 64-bit SPUT handler.
3388 */
3389 # sput-wide vAA, field /* BBBB */
3390 .extern artSet64IndirectStaticFromMterp
3391 EXPORT_PC()
3392 FETCH(a0, 1) # a0 <- field ref CCCC
3393 lw a1, OFF_FP_METHOD(rFP) # a1 <- method
3394 GET_OPA(a2) # a2 <- AA
3395 EAS2(a2, rFP, a2) # a2 <- &fp[AA]
3396 move a3, rSELF # a3 <- self
3397 PREFETCH_INST(2) # load rINST
3398 JAL(artSet64IndirectStaticFromMterp)
3399 bnez v0, MterpException # bail out
3400 ADVANCE(2) # advance rPC
3401 GET_INST_OPCODE(t0) # extract opcode from rINST
3402 GOTO_OPCODE(t0) # jump to next instruction
3403
3404/* ------------------------------ */
3405 .balign 128
3406.L_op_sput_object: /* 0x69 */
3407/* File: mips/op_sput_object.S */
3408 /*
3409 * General 32-bit SPUT handler.
3410 *
3411 * for: sput-object,
3412 */
3413 /* op vAA, field@BBBB */
3414 EXPORT_PC()
3415 addu a0, rFP, OFF_FP_SHADOWFRAME
3416 move a1, rPC
3417 move a2, rINST
3418 move a3, rSELF
3419 JAL(MterpSputObject)
3420 beqz v0, MterpException
3421 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
3422 GET_INST_OPCODE(t0) # extract opcode from rINST
3423 GOTO_OPCODE(t0) # jump to next instruction
3424
3425/* ------------------------------ */
3426 .balign 128
3427.L_op_sput_boolean: /* 0x6a */
3428/* File: mips/op_sput_boolean.S */
3429/* File: mips/op_sput.S */
3430 /*
3431 * General SPUT handler.
3432 *
3433 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3434 */
3435 # op vAA, field /* BBBB */
3436 EXPORT_PC()
3437 FETCH(a0, 1) # a0 <- field ref BBBB
3438 GET_OPA(a3) # a3 <- AA
3439 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer
3440 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
3441 move a3, rSELF # a3 <- self
3442 PREFETCH_INST(2) # load rINST
3443 JAL(artSet8StaticFromCode)
3444 bnez v0, MterpException # bail out
3445 ADVANCE(2) # advance rPC
3446 GET_INST_OPCODE(t0) # extract opcode from rINST
3447 GOTO_OPCODE(t0) # jump to next instruction
3448
3449
3450/* ------------------------------ */
3451 .balign 128
3452.L_op_sput_byte: /* 0x6b */
3453/* File: mips/op_sput_byte.S */
3454/* File: mips/op_sput.S */
3455 /*
3456 * General SPUT handler.
3457 *
3458 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3459 */
3460 # op vAA, field /* BBBB */
3461 EXPORT_PC()
3462 FETCH(a0, 1) # a0 <- field ref BBBB
3463 GET_OPA(a3) # a3 <- AA
3464 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer
3465 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
3466 move a3, rSELF # a3 <- self
3467 PREFETCH_INST(2) # load rINST
3468 JAL(artSet8StaticFromCode)
3469 bnez v0, MterpException # bail out
3470 ADVANCE(2) # advance rPC
3471 GET_INST_OPCODE(t0) # extract opcode from rINST
3472 GOTO_OPCODE(t0) # jump to next instruction
3473
3474
3475/* ------------------------------ */
3476 .balign 128
3477.L_op_sput_char: /* 0x6c */
3478/* File: mips/op_sput_char.S */
3479/* File: mips/op_sput.S */
3480 /*
3481 * General SPUT handler.
3482 *
3483 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3484 */
3485 # op vAA, field /* BBBB */
3486 EXPORT_PC()
3487 FETCH(a0, 1) # a0 <- field ref BBBB
3488 GET_OPA(a3) # a3 <- AA
3489 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer
3490 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
3491 move a3, rSELF # a3 <- self
3492 PREFETCH_INST(2) # load rINST
3493 JAL(artSet16StaticFromCode)
3494 bnez v0, MterpException # bail out
3495 ADVANCE(2) # advance rPC
3496 GET_INST_OPCODE(t0) # extract opcode from rINST
3497 GOTO_OPCODE(t0) # jump to next instruction
3498
3499
3500/* ------------------------------ */
3501 .balign 128
3502.L_op_sput_short: /* 0x6d */
3503/* File: mips/op_sput_short.S */
3504/* File: mips/op_sput.S */
3505 /*
3506 * General SPUT handler.
3507 *
3508 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3509 */
3510 # op vAA, field /* BBBB */
3511 EXPORT_PC()
3512 FETCH(a0, 1) # a0 <- field ref BBBB
3513 GET_OPA(a3) # a3 <- AA
3514 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer
3515 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
3516 move a3, rSELF # a3 <- self
3517 PREFETCH_INST(2) # load rINST
3518 JAL(artSet16StaticFromCode)
3519 bnez v0, MterpException # bail out
3520 ADVANCE(2) # advance rPC
3521 GET_INST_OPCODE(t0) # extract opcode from rINST
3522 GOTO_OPCODE(t0) # jump to next instruction
3523
3524
3525/* ------------------------------ */
3526 .balign 128
3527.L_op_invoke_virtual: /* 0x6e */
3528/* File: mips/op_invoke_virtual.S */
3529/* File: mips/invoke.S */
3530 /*
3531 * Generic invoke handler wrapper.
3532 */
3533 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3534 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3535 .extern MterpInvokeVirtual
3536 EXPORT_PC()
3537 move a0, rSELF
3538 addu a1, rFP, OFF_FP_SHADOWFRAME
3539 move a2, rPC
3540 move a3, rINST
3541 JAL(MterpInvokeVirtual)
3542 beqz v0, MterpException
3543 FETCH_ADVANCE_INST(3)
3544 JAL(MterpShouldSwitchInterpreters)
3545 bnez v0, MterpFallback
3546 GET_INST_OPCODE(t0)
3547 GOTO_OPCODE(t0)
3548
3549
3550/* ------------------------------ */
3551 .balign 128
3552.L_op_invoke_super: /* 0x6f */
3553/* File: mips/op_invoke_super.S */
3554/* File: mips/invoke.S */
3555 /*
3556 * Generic invoke handler wrapper.
3557 */
3558 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3559 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3560 .extern MterpInvokeSuper
3561 EXPORT_PC()
3562 move a0, rSELF
3563 addu a1, rFP, OFF_FP_SHADOWFRAME
3564 move a2, rPC
3565 move a3, rINST
3566 JAL(MterpInvokeSuper)
3567 beqz v0, MterpException
3568 FETCH_ADVANCE_INST(3)
3569 JAL(MterpShouldSwitchInterpreters)
3570 bnez v0, MterpFallback
3571 GET_INST_OPCODE(t0)
3572 GOTO_OPCODE(t0)
3573
3574
3575/* ------------------------------ */
3576 .balign 128
3577.L_op_invoke_direct: /* 0x70 */
3578/* File: mips/op_invoke_direct.S */
3579/* File: mips/invoke.S */
3580 /*
3581 * Generic invoke handler wrapper.
3582 */
3583 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3584 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3585 .extern MterpInvokeDirect
3586 EXPORT_PC()
3587 move a0, rSELF
3588 addu a1, rFP, OFF_FP_SHADOWFRAME
3589 move a2, rPC
3590 move a3, rINST
3591 JAL(MterpInvokeDirect)
3592 beqz v0, MterpException
3593 FETCH_ADVANCE_INST(3)
3594 JAL(MterpShouldSwitchInterpreters)
3595 bnez v0, MterpFallback
3596 GET_INST_OPCODE(t0)
3597 GOTO_OPCODE(t0)
3598
3599
3600/* ------------------------------ */
3601 .balign 128
3602.L_op_invoke_static: /* 0x71 */
3603/* File: mips/op_invoke_static.S */
3604/* File: mips/invoke.S */
3605 /*
3606 * Generic invoke handler wrapper.
3607 */
3608 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3609 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3610 .extern MterpInvokeStatic
3611 EXPORT_PC()
3612 move a0, rSELF
3613 addu a1, rFP, OFF_FP_SHADOWFRAME
3614 move a2, rPC
3615 move a3, rINST
3616 JAL(MterpInvokeStatic)
3617 beqz v0, MterpException
3618 FETCH_ADVANCE_INST(3)
3619 JAL(MterpShouldSwitchInterpreters)
3620 bnez v0, MterpFallback
3621 GET_INST_OPCODE(t0)
3622 GOTO_OPCODE(t0)
3623
3624
3625/* ------------------------------ */
3626 .balign 128
3627.L_op_invoke_interface: /* 0x72 */
3628/* File: mips/op_invoke_interface.S */
3629/* File: mips/invoke.S */
3630 /*
3631 * Generic invoke handler wrapper.
3632 */
3633 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3634 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3635 .extern MterpInvokeInterface
3636 EXPORT_PC()
3637 move a0, rSELF
3638 addu a1, rFP, OFF_FP_SHADOWFRAME
3639 move a2, rPC
3640 move a3, rINST
3641 JAL(MterpInvokeInterface)
3642 beqz v0, MterpException
3643 FETCH_ADVANCE_INST(3)
3644 JAL(MterpShouldSwitchInterpreters)
3645 bnez v0, MterpFallback
3646 GET_INST_OPCODE(t0)
3647 GOTO_OPCODE(t0)
3648
3649
3650/* ------------------------------ */
3651 .balign 128
3652.L_op_return_void_no_barrier: /* 0x73 */
3653/* File: mips/op_return_void_no_barrier.S */
3654 lw ra, THREAD_FLAGS_OFFSET(rSELF)
3655 move a0, rSELF
3656 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
3657 beqz ra, 1f
3658 JAL(MterpSuspendCheck) # (self)
36591:
3660 move v0, zero
3661 move v1, zero
3662 b MterpReturn
3663
3664/* ------------------------------ */
3665 .balign 128
3666.L_op_invoke_virtual_range: /* 0x74 */
3667/* File: mips/op_invoke_virtual_range.S */
3668/* File: mips/invoke.S */
3669 /*
3670 * Generic invoke handler wrapper.
3671 */
3672 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3673 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3674 .extern MterpInvokeVirtualRange
3675 EXPORT_PC()
3676 move a0, rSELF
3677 addu a1, rFP, OFF_FP_SHADOWFRAME
3678 move a2, rPC
3679 move a3, rINST
3680 JAL(MterpInvokeVirtualRange)
3681 beqz v0, MterpException
3682 FETCH_ADVANCE_INST(3)
3683 JAL(MterpShouldSwitchInterpreters)
3684 bnez v0, MterpFallback
3685 GET_INST_OPCODE(t0)
3686 GOTO_OPCODE(t0)
3687
3688
3689/* ------------------------------ */
3690 .balign 128
3691.L_op_invoke_super_range: /* 0x75 */
3692/* File: mips/op_invoke_super_range.S */
3693/* File: mips/invoke.S */
3694 /*
3695 * Generic invoke handler wrapper.
3696 */
3697 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3698 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3699 .extern MterpInvokeSuperRange
3700 EXPORT_PC()
3701 move a0, rSELF
3702 addu a1, rFP, OFF_FP_SHADOWFRAME
3703 move a2, rPC
3704 move a3, rINST
3705 JAL(MterpInvokeSuperRange)
3706 beqz v0, MterpException
3707 FETCH_ADVANCE_INST(3)
3708 JAL(MterpShouldSwitchInterpreters)
3709 bnez v0, MterpFallback
3710 GET_INST_OPCODE(t0)
3711 GOTO_OPCODE(t0)
3712
3713
3714/* ------------------------------ */
3715 .balign 128
3716.L_op_invoke_direct_range: /* 0x76 */
3717/* File: mips/op_invoke_direct_range.S */
3718/* File: mips/invoke.S */
3719 /*
3720 * Generic invoke handler wrapper.
3721 */
3722 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3723 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3724 .extern MterpInvokeDirectRange
3725 EXPORT_PC()
3726 move a0, rSELF
3727 addu a1, rFP, OFF_FP_SHADOWFRAME
3728 move a2, rPC
3729 move a3, rINST
3730 JAL(MterpInvokeDirectRange)
3731 beqz v0, MterpException
3732 FETCH_ADVANCE_INST(3)
3733 JAL(MterpShouldSwitchInterpreters)
3734 bnez v0, MterpFallback
3735 GET_INST_OPCODE(t0)
3736 GOTO_OPCODE(t0)
3737
3738
3739/* ------------------------------ */
3740 .balign 128
3741.L_op_invoke_static_range: /* 0x77 */
3742/* File: mips/op_invoke_static_range.S */
3743/* File: mips/invoke.S */
3744 /*
3745 * Generic invoke handler wrapper.
3746 */
3747 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3748 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3749 .extern MterpInvokeStaticRange
3750 EXPORT_PC()
3751 move a0, rSELF
3752 addu a1, rFP, OFF_FP_SHADOWFRAME
3753 move a2, rPC
3754 move a3, rINST
3755 JAL(MterpInvokeStaticRange)
3756 beqz v0, MterpException
3757 FETCH_ADVANCE_INST(3)
3758 JAL(MterpShouldSwitchInterpreters)
3759 bnez v0, MterpFallback
3760 GET_INST_OPCODE(t0)
3761 GOTO_OPCODE(t0)
3762
3763
3764/* ------------------------------ */
3765 .balign 128
3766.L_op_invoke_interface_range: /* 0x78 */
3767/* File: mips/op_invoke_interface_range.S */
3768/* File: mips/invoke.S */
3769 /*
3770 * Generic invoke handler wrapper.
3771 */
3772 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
3773 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
3774 .extern MterpInvokeInterfaceRange
3775 EXPORT_PC()
3776 move a0, rSELF
3777 addu a1, rFP, OFF_FP_SHADOWFRAME
3778 move a2, rPC
3779 move a3, rINST
3780 JAL(MterpInvokeInterfaceRange)
3781 beqz v0, MterpException
3782 FETCH_ADVANCE_INST(3)
3783 JAL(MterpShouldSwitchInterpreters)
3784 bnez v0, MterpFallback
3785 GET_INST_OPCODE(t0)
3786 GOTO_OPCODE(t0)
3787
3788
3789/* ------------------------------ */
3790 .balign 128
3791.L_op_unused_79: /* 0x79 */
3792/* File: mips/op_unused_79.S */
3793/* File: mips/unused.S */
3794/*
3795 * Bail to reference interpreter to throw.
3796 */
3797 b MterpFallback
3798
3799
3800/* ------------------------------ */
3801 .balign 128
3802.L_op_unused_7a: /* 0x7a */
3803/* File: mips/op_unused_7a.S */
3804/* File: mips/unused.S */
3805/*
3806 * Bail to reference interpreter to throw.
3807 */
3808 b MterpFallback
3809
3810
3811/* ------------------------------ */
3812 .balign 128
3813.L_op_neg_int: /* 0x7b */
3814/* File: mips/op_neg_int.S */
3815/* File: mips/unop.S */
3816 /*
3817 * Generic 32-bit unary operation. Provide an "instr" line that
3818 * specifies an instruction that performs "result = op a0".
3819 * This could be a MIPS instruction or a function call.
3820 *
3821 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3822 * int-to-byte, int-to-char, int-to-short
3823 */
3824 /* unop vA, vB */
3825 GET_OPB(a3) # a3 <- B
3826 GET_OPA4(t0) # t0 <- A+
3827 GET_VREG(a0, a3) # a0 <- vB
3828 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3829 # optional op
3830 negu a0, a0 # a0 <- op, a0-a3 changed
3831 GET_INST_OPCODE(t1) # extract opcode from rINST
3832 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3833 /* 9-10 instructions */
3834
3835
3836/* ------------------------------ */
3837 .balign 128
3838.L_op_not_int: /* 0x7c */
3839/* File: mips/op_not_int.S */
3840/* File: mips/unop.S */
3841 /*
3842 * Generic 32-bit unary operation. Provide an "instr" line that
3843 * specifies an instruction that performs "result = op a0".
3844 * This could be a MIPS instruction or a function call.
3845 *
3846 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3847 * int-to-byte, int-to-char, int-to-short
3848 */
3849 /* unop vA, vB */
3850 GET_OPB(a3) # a3 <- B
3851 GET_OPA4(t0) # t0 <- A+
3852 GET_VREG(a0, a3) # a0 <- vB
3853 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3854 # optional op
3855 not a0, a0 # a0 <- op, a0-a3 changed
3856 GET_INST_OPCODE(t1) # extract opcode from rINST
3857 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3858 /* 9-10 instructions */
3859
3860
3861/* ------------------------------ */
3862 .balign 128
3863.L_op_neg_long: /* 0x7d */
3864/* File: mips/op_neg_long.S */
3865/* File: mips/unopWide.S */
3866 /*
3867 * Generic 64-bit unary operation. Provide an "instr" line that
3868 * specifies an instruction that performs "result = op a0/a1".
3869 * This could be MIPS instruction or a function call.
3870 *
3871 * For: neg-long, not-long, neg-double,
3872 */
3873 /* unop vA, vB */
3874 GET_OPA4(rOBJ) # rOBJ <- A+
3875 GET_OPB(a3) # a3 <- B
3876 EAS2(a3, rFP, a3) # a3 <- &fp[B]
3877 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3878 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3879 negu v0, a0 # optional op
3880 negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed
3881 GET_INST_OPCODE(t0) # extract opcode from rINST
3882 SET_VREG64(v0, v1, rOBJ) # vAA <- a0/a1
3883 GOTO_OPCODE(t0) # jump to next instruction
3884 /* 12-13 instructions */
3885
3886
3887/* ------------------------------ */
3888 .balign 128
3889.L_op_not_long: /* 0x7e */
3890/* File: mips/op_not_long.S */
3891/* File: mips/unopWide.S */
3892 /*
3893 * Generic 64-bit unary operation. Provide an "instr" line that
3894 * specifies an instruction that performs "result = op a0/a1".
3895 * This could be MIPS instruction or a function call.
3896 *
3897 * For: neg-long, not-long, neg-double,
3898 */
3899 /* unop vA, vB */
3900 GET_OPA4(rOBJ) # rOBJ <- A+
3901 GET_OPB(a3) # a3 <- B
3902 EAS2(a3, rFP, a3) # a3 <- &fp[B]
3903 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3904 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3905 not a0, a0 # optional op
3906 not a1, a1 # a0/a1 <- op, a2-a3 changed
3907 GET_INST_OPCODE(t0) # extract opcode from rINST
3908 SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1
3909 GOTO_OPCODE(t0) # jump to next instruction
3910 /* 12-13 instructions */
3911
3912
3913/* ------------------------------ */
3914 .balign 128
3915.L_op_neg_float: /* 0x7f */
3916/* File: mips/op_neg_float.S */
3917/* File: mips/unop.S */
3918 /*
3919 * Generic 32-bit unary operation. Provide an "instr" line that
3920 * specifies an instruction that performs "result = op a0".
3921 * This could be a MIPS instruction or a function call.
3922 *
3923 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3924 * int-to-byte, int-to-char, int-to-short
3925 */
3926 /* unop vA, vB */
3927 GET_OPB(a3) # a3 <- B
3928 GET_OPA4(t0) # t0 <- A+
3929 GET_VREG(a0, a3) # a0 <- vB
3930 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3931 # optional op
3932 addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed
3933 GET_INST_OPCODE(t1) # extract opcode from rINST
3934 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
3935 /* 9-10 instructions */
3936
3937
3938/* ------------------------------ */
3939 .balign 128
3940.L_op_neg_double: /* 0x80 */
3941/* File: mips/op_neg_double.S */
3942/* File: mips/unopWide.S */
3943 /*
3944 * Generic 64-bit unary operation. Provide an "instr" line that
3945 * specifies an instruction that performs "result = op a0/a1".
3946 * This could be MIPS instruction or a function call.
3947 *
3948 * For: neg-long, not-long, neg-double,
3949 */
3950 /* unop vA, vB */
3951 GET_OPA4(rOBJ) # rOBJ <- A+
3952 GET_OPB(a3) # a3 <- B
3953 EAS2(a3, rFP, a3) # a3 <- &fp[B]
3954 LOAD64(a0, a1, a3) # a0/a1 <- vAA
3955 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3956 # optional op
3957 addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed
3958 GET_INST_OPCODE(t0) # extract opcode from rINST
3959 SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1
3960 GOTO_OPCODE(t0) # jump to next instruction
3961 /* 12-13 instructions */
3962
3963
3964/* ------------------------------ */
3965 .balign 128
3966.L_op_int_to_long: /* 0x81 */
3967/* File: mips/op_int_to_long.S */
3968/* File: mips/unopWider.S */
3969 /*
3970 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3971 * that specifies an instruction that performs "result = op a0", where
3972 * "result" is a 64-bit quantity in a0/a1.
3973 *
3974 * For: int-to-long
3975 */
3976 /* unop vA, vB */
3977 GET_OPA4(rOBJ) # rOBJ <- A+
3978 GET_OPB(a3) # a3 <- B
3979 GET_VREG(a0, a3) # a0 <- vB
3980 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
3981 # optional op
3982 sra a1, a0, 31 # result <- op, a0-a3 changed
3983 GET_INST_OPCODE(t0) # extract opcode from rINST
3984 SET_VREG64(a0, a1, rOBJ) # vA/vA+1 <- a0/a1
3985 GOTO_OPCODE(t0) # jump to next instruction
3986 /* 10-11 instructions */
3987
3988
3989/* ------------------------------ */
3990 .balign 128
3991.L_op_int_to_float: /* 0x82 */
3992/* File: mips/op_int_to_float.S */
3993/* File: mips/funop.S */
3994 /*
3995 * Generic 32-bit unary operation. Provide an "instr" line that
3996 * specifies an instruction that performs "result = op a0".
3997 * This could be a MIPS instruction or a function call.
3998 *
3999 * for: int-to-float, float-to-int
4000 */
4001 /* unop vA, vB */
4002 GET_OPB(a3) # a3 <- B
4003 GET_OPA4(rOBJ) # t0 <- A+
4004 GET_VREG_F(fa0, a3)
4005 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4006 cvt.s.w fv0, fa0
4007
4008.Lop_int_to_float_set_vreg_f:
4009 SET_VREG_F(fv0, rOBJ)
4010 GET_INST_OPCODE(t1) # extract opcode from rINST
4011 GOTO_OPCODE(t1) # jump to next instruction
4012
4013
4014/* ------------------------------ */
4015 .balign 128
4016.L_op_int_to_double: /* 0x83 */
4017/* File: mips/op_int_to_double.S */
4018/* File: mips/funopWider.S */
4019 /*
4020 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
4021 * that specifies an instruction that performs "result = op a0", where
4022 * "result" is a 64-bit quantity in a0/a1.
4023 *
4024 * For: int-to-double, float-to-long, float-to-double
4025 */
4026 /* unop vA, vB */
4027 GET_OPA4(rOBJ) # rOBJ <- A+
4028 GET_OPB(a3) # a3 <- B
4029 GET_VREG_F(fa0, a3)
4030 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4031 cvt.d.w fv0, fa0
4032
4033.Lop_int_to_double_set_vreg:
4034 SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1
4035 GET_INST_OPCODE(t0) # extract opcode from rINST
4036 GOTO_OPCODE(t0) # jump to next instruction
4037
4038
4039/* ------------------------------ */
4040 .balign 128
4041.L_op_long_to_int: /* 0x84 */
4042/* File: mips/op_long_to_int.S */
4043/* we ignore the high word, making this equivalent to a 32-bit reg move */
4044/* File: mips/op_move.S */
4045 /* for move, move-object, long-to-int */
4046 /* op vA, vB */
4047 GET_OPB(a1) # a1 <- B from 15:12
4048 GET_OPA4(a0) # a0 <- A from 11:8
4049 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4050 GET_VREG(a2, a1) # a2 <- fp[B]
4051 GET_INST_OPCODE(t0) # t0 <- opcode from rINST
4052 .if 0
4053 SET_VREG_OBJECT(a2, a0) # fp[A] <- a2
4054 .else
4055 SET_VREG(a2, a0) # fp[A] <- a2
4056 .endif
4057 GOTO_OPCODE(t0) # jump to next instruction
4058
4059
4060/* ------------------------------ */
4061 .balign 128
4062.L_op_long_to_float: /* 0x85 */
4063/* File: mips/op_long_to_float.S */
4064/* File: mips/unopNarrower.S */
4065 /*
4066 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
4067 * that specifies an instruction that performs "result = op a0/a1", where
4068 * "result" is a 32-bit quantity in a0.
4069 *
4070 * For: long-to-float, double-to-int, double-to-float
4071 * If hard floating point support is available, use fa0 as the parameter,
4072 * except for long-to-float opcode.
4073 * (This would work for long-to-int, but that instruction is actually
4074 * an exact match for OP_MOVE.)
4075 */
4076 /* unop vA, vB */
4077 GET_OPB(a3) # a3 <- B
4078 GET_OPA4(rOBJ) # t1 <- A+
4079 EAS2(a3, rFP, a3) # a3 <- &fp[B]
4080 LOAD64(rARG0, rARG1, a3)
4081 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4082 JAL(__floatdisf)
4083
4084.Lop_long_to_float_set_vreg_f:
4085 SET_VREG_F(fv0, rOBJ) # vA <- result0
4086 GET_INST_OPCODE(t0) # extract opcode from rINST
4087 GOTO_OPCODE(t0) # jump to next instruction
4088
4089
4090/* ------------------------------ */
4091 .balign 128
4092.L_op_long_to_double: /* 0x86 */
4093/* File: mips/op_long_to_double.S */
4094/* File: mips/funopWide.S */
4095 /*
4096 * Generic 64-bit unary operation. Provide an "instr" line that
4097 * specifies an instruction that performs "result = op a0/a1".
4098 * This could be a MIPS instruction or a function call.
4099 *
4100 * long-to-double, double-to-long
4101 */
4102 /* unop vA, vB */
4103 GET_OPA4(rOBJ) # t1 <- A+
4104 GET_OPB(a3) # a3 <- B
4105 EAS2(a3, rFP, a3) # a3 <- &fp[B]
4106 LOAD64(rARG0, rARG1, a3)
4107 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4108 # optional op
4109 JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed
4110
4111.Lop_long_to_double_set_vreg:
4112 SET_VREG64_F(fv0, fv0f, rOBJ) # vAA <- a0/a1
4113 GET_INST_OPCODE(t0) # extract opcode from rINST
4114 GOTO_OPCODE(t0) # jump to next instruction
4115 /* 12-13 instructions */
4116
4117
4118/* ------------------------------ */
4119 .balign 128
4120.L_op_float_to_int: /* 0x87 */
4121/* File: mips/op_float_to_int.S */
4122/* File: mips/funop.S */
4123 /*
4124 * Generic 32-bit unary operation. Provide an "instr" line that
4125 * specifies an instruction that performs "result = op a0".
4126 * This could be a MIPS instruction or a function call.
4127 *
4128 * for: int-to-float, float-to-int
4129 */
4130 /* unop vA, vB */
4131 GET_OPB(a3) # a3 <- B
4132 GET_OPA4(rOBJ) # t0 <- A+
4133 GET_VREG_F(fa0, a3)
4134 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4135 b f2i_doconv
4136
4137.Lop_float_to_int_set_vreg_f:
4138 SET_VREG_F(fv0, rOBJ)
4139 GET_INST_OPCODE(t1) # extract opcode from rINST
4140 GOTO_OPCODE(t1) # jump to next instruction
4141
4142
4143/* ------------------------------ */
4144 .balign 128
4145.L_op_float_to_long: /* 0x88 */
4146/* File: mips/op_float_to_long.S */
4147/* File: mips/funopWider.S */
4148 /*
4149 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
4150 * that specifies an instruction that performs "result = op a0", where
4151 * "result" is a 64-bit quantity in a0/a1.
4152 *
4153 * For: int-to-double, float-to-long, float-to-double
4154 */
4155 /* unop vA, vB */
4156 GET_OPA4(rOBJ) # rOBJ <- A+
4157 GET_OPB(a3) # a3 <- B
4158 GET_VREG_F(fa0, a3)
4159 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4160 b f2l_doconv
4161
4162.Lop_float_to_long_set_vreg:
4163 SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1
4164 GET_INST_OPCODE(t0) # extract opcode from rINST
4165 GOTO_OPCODE(t0) # jump to next instruction
4166
4167
4168/* ------------------------------ */
4169 .balign 128
4170.L_op_float_to_double: /* 0x89 */
4171/* File: mips/op_float_to_double.S */
4172/* File: mips/funopWider.S */
4173 /*
4174 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
4175 * that specifies an instruction that performs "result = op a0", where
4176 * "result" is a 64-bit quantity in a0/a1.
4177 *
4178 * For: int-to-double, float-to-long, float-to-double
4179 */
4180 /* unop vA, vB */
4181 GET_OPA4(rOBJ) # rOBJ <- A+
4182 GET_OPB(a3) # a3 <- B
4183 GET_VREG_F(fa0, a3)
4184 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4185 cvt.d.s fv0, fa0
4186
4187.Lop_float_to_double_set_vreg:
4188 SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1
4189 GET_INST_OPCODE(t0) # extract opcode from rINST
4190 GOTO_OPCODE(t0) # jump to next instruction
4191
4192
4193/* ------------------------------ */
4194 .balign 128
4195.L_op_double_to_int: /* 0x8a */
4196/* File: mips/op_double_to_int.S */
4197/* File: mips/unopNarrower.S */
4198 /*
4199 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
4200 * that specifies an instruction that performs "result = op a0/a1", where
4201 * "result" is a 32-bit quantity in a0.
4202 *
4203 * For: long-to-float, double-to-int, double-to-float
4204 * If hard floating point support is available, use fa0 as the parameter,
4205 * except for long-to-float opcode.
4206 * (This would work for long-to-int, but that instruction is actually
4207 * an exact match for OP_MOVE.)
4208 */
4209 /* unop vA, vB */
4210 GET_OPB(a3) # a3 <- B
4211 GET_OPA4(rOBJ) # t1 <- A+
4212 EAS2(a3, rFP, a3) # a3 <- &fp[B]
4213 LOAD64_F(fa0, fa0f, a3)
4214 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4215 b d2i_doconv
4216
4217.Lop_double_to_int_set_vreg_f:
4218 SET_VREG_F(fv0, rOBJ) # vA <- result0
4219 GET_INST_OPCODE(t0) # extract opcode from rINST
4220 GOTO_OPCODE(t0) # jump to next instruction
4221
4222/*
4223 * Convert the double in a0/a1 to an int in a0.
4224 *
4225 * We have to clip values to int min/max per the specification. The
4226 * expected common case is a "reasonable" value that converts directly
4227 * to modest integer. The EABI convert function isn't doing this for us.
4228 */
4229
4230/* ------------------------------ */
4231 .balign 128
4232.L_op_double_to_long: /* 0x8b */
4233/* File: mips/op_double_to_long.S */
4234/* File: mips/funopWide.S */
4235 /*
4236 * Generic 64-bit unary operation. Provide an "instr" line that
4237 * specifies an instruction that performs "result = op a0/a1".
4238 * This could be a MIPS instruction or a function call.
4239 *
4240 * long-to-double, double-to-long
4241 */
4242 /* unop vA, vB */
4243 GET_OPA4(rOBJ) # t1 <- A+
4244 GET_OPB(a3) # a3 <- B
4245 EAS2(a3, rFP, a3) # a3 <- &fp[B]
4246 LOAD64_F(fa0, fa0f, a3)
4247 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4248 # optional op
4249 b d2l_doconv # a0/a1 <- op, a2-a3 changed
4250
4251.Lop_double_to_long_set_vreg:
4252 SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1
4253 GET_INST_OPCODE(t0) # extract opcode from rINST
4254 GOTO_OPCODE(t0) # jump to next instruction
4255 /* 12-13 instructions */
4256
4257
4258/* ------------------------------ */
4259 .balign 128
4260.L_op_double_to_float: /* 0x8c */
4261/* File: mips/op_double_to_float.S */
4262/* File: mips/unopNarrower.S */
4263 /*
4264 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
4265 * that specifies an instruction that performs "result = op a0/a1", where
4266 * "result" is a 32-bit quantity in a0.
4267 *
4268 * For: long-to-float, double-to-int, double-to-float
4269 * If hard floating point support is available, use fa0 as the parameter,
4270 * except for long-to-float opcode.
4271 * (This would work for long-to-int, but that instruction is actually
4272 * an exact match for OP_MOVE.)
4273 */
4274 /* unop vA, vB */
4275 GET_OPB(a3) # a3 <- B
4276 GET_OPA4(rOBJ) # t1 <- A+
4277 EAS2(a3, rFP, a3) # a3 <- &fp[B]
4278 LOAD64_F(fa0, fa0f, a3)
4279 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4280 cvt.s.d fv0, fa0
4281
4282.Lop_double_to_float_set_vreg_f:
4283 SET_VREG_F(fv0, rOBJ) # vA <- result0
4284 GET_INST_OPCODE(t0) # extract opcode from rINST
4285 GOTO_OPCODE(t0) # jump to next instruction
4286
4287
4288/* ------------------------------ */
4289 .balign 128
4290.L_op_int_to_byte: /* 0x8d */
4291/* File: mips/op_int_to_byte.S */
4292/* File: mips/unop.S */
4293 /*
4294 * Generic 32-bit unary operation. Provide an "instr" line that
4295 * specifies an instruction that performs "result = op a0".
4296 * This could be a MIPS instruction or a function call.
4297 *
4298 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4299 * int-to-byte, int-to-char, int-to-short
4300 */
4301 /* unop vA, vB */
4302 GET_OPB(a3) # a3 <- B
4303 GET_OPA4(t0) # t0 <- A+
4304 GET_VREG(a0, a3) # a0 <- vB
4305 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4306 sll a0, a0, 24 # optional op
4307 sra a0, a0, 24 # a0 <- op, a0-a3 changed
4308 GET_INST_OPCODE(t1) # extract opcode from rINST
4309 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4310 /* 9-10 instructions */
4311
4312
4313/* ------------------------------ */
4314 .balign 128
4315.L_op_int_to_char: /* 0x8e */
4316/* File: mips/op_int_to_char.S */
4317/* File: mips/unop.S */
4318 /*
4319 * Generic 32-bit unary operation. Provide an "instr" line that
4320 * specifies an instruction that performs "result = op a0".
4321 * This could be a MIPS instruction or a function call.
4322 *
4323 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4324 * int-to-byte, int-to-char, int-to-short
4325 */
4326 /* unop vA, vB */
4327 GET_OPB(a3) # a3 <- B
4328 GET_OPA4(t0) # t0 <- A+
4329 GET_VREG(a0, a3) # a0 <- vB
4330 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4331 # optional op
4332 and a0, 0xffff # a0 <- op, a0-a3 changed
4333 GET_INST_OPCODE(t1) # extract opcode from rINST
4334 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4335 /* 9-10 instructions */
4336
4337
4338/* ------------------------------ */
4339 .balign 128
4340.L_op_int_to_short: /* 0x8f */
4341/* File: mips/op_int_to_short.S */
4342/* File: mips/unop.S */
4343 /*
4344 * Generic 32-bit unary operation. Provide an "instr" line that
4345 * specifies an instruction that performs "result = op a0".
4346 * This could be a MIPS instruction or a function call.
4347 *
4348 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
4349 * int-to-byte, int-to-char, int-to-short
4350 */
4351 /* unop vA, vB */
4352 GET_OPB(a3) # a3 <- B
4353 GET_OPA4(t0) # t0 <- A+
4354 GET_VREG(a0, a3) # a0 <- vB
4355 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
4356 sll a0, 16 # optional op
4357 sra a0, 16 # a0 <- op, a0-a3 changed
4358 GET_INST_OPCODE(t1) # extract opcode from rINST
4359 SET_VREG_GOTO(a0, t0, t1) # vAA <- result0
4360 /* 9-10 instructions */
4361
4362
4363/* ------------------------------ */
4364 .balign 128
4365.L_op_add_int: /* 0x90 */
4366/* File: mips/op_add_int.S */
4367/* File: mips/binop.S */
4368 /*
4369 * Generic 32-bit binary operation. Provide an "instr" line that
4370 * specifies an instruction that performs "result = a0 op a1".
4371 * This could be a MIPS instruction or a function call. (If the result
4372 * comes back in a register other than a0, you can override "result".)
4373 *
4374 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4375 * vCC (a1). Useful for integer division and modulus. Note that we
4376 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4377 * handles it correctly.
4378 *
4379 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4380 * xor-int, shl-int, shr-int, ushr-int
4381 */
4382 /* binop vAA, vBB, vCC */
4383 FETCH(a0, 1) # a0 <- CCBB
4384 GET_OPA(rOBJ) # rOBJ <- AA
4385 srl a3, a0, 8 # a3 <- CC
4386 and a2, a0, 255 # a2 <- BB
4387 GET_VREG(a1, a3) # a1 <- vCC
4388 GET_VREG(a0, a2) # a0 <- vBB
4389 .if 0
4390 # is second operand zero?
4391 beqz a1, common_errDivideByZero
4392 .endif
4393
4394 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4395 # optional op
4396 addu a0, a0, a1 # a0 <- op, a0-a3 changed
4397 GET_INST_OPCODE(t0) # extract opcode from rINST
4398 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4399 /* 11-14 instructions */
4400
4401
4402/* ------------------------------ */
4403 .balign 128
4404.L_op_sub_int: /* 0x91 */
4405/* File: mips/op_sub_int.S */
4406/* File: mips/binop.S */
4407 /*
4408 * Generic 32-bit binary operation. Provide an "instr" line that
4409 * specifies an instruction that performs "result = a0 op a1".
4410 * This could be a MIPS instruction or a function call. (If the result
4411 * comes back in a register other than a0, you can override "result".)
4412 *
4413 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4414 * vCC (a1). Useful for integer division and modulus. Note that we
4415 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4416 * handles it correctly.
4417 *
4418 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4419 * xor-int, shl-int, shr-int, ushr-int
4420 */
4421 /* binop vAA, vBB, vCC */
4422 FETCH(a0, 1) # a0 <- CCBB
4423 GET_OPA(rOBJ) # rOBJ <- AA
4424 srl a3, a0, 8 # a3 <- CC
4425 and a2, a0, 255 # a2 <- BB
4426 GET_VREG(a1, a3) # a1 <- vCC
4427 GET_VREG(a0, a2) # a0 <- vBB
4428 .if 0
4429 # is second operand zero?
4430 beqz a1, common_errDivideByZero
4431 .endif
4432
4433 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4434 # optional op
4435 subu a0, a0, a1 # a0 <- op, a0-a3 changed
4436 GET_INST_OPCODE(t0) # extract opcode from rINST
4437 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4438 /* 11-14 instructions */
4439
4440
4441/* ------------------------------ */
4442 .balign 128
4443.L_op_mul_int: /* 0x92 */
4444/* File: mips/op_mul_int.S */
4445/* File: mips/binop.S */
4446 /*
4447 * Generic 32-bit binary operation. Provide an "instr" line that
4448 * specifies an instruction that performs "result = a0 op a1".
4449 * This could be a MIPS instruction or a function call. (If the result
4450 * comes back in a register other than a0, you can override "result".)
4451 *
4452 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4453 * vCC (a1). Useful for integer division and modulus. Note that we
4454 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4455 * handles it correctly.
4456 *
4457 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4458 * xor-int, shl-int, shr-int, ushr-int
4459 */
4460 /* binop vAA, vBB, vCC */
4461 FETCH(a0, 1) # a0 <- CCBB
4462 GET_OPA(rOBJ) # rOBJ <- AA
4463 srl a3, a0, 8 # a3 <- CC
4464 and a2, a0, 255 # a2 <- BB
4465 GET_VREG(a1, a3) # a1 <- vCC
4466 GET_VREG(a0, a2) # a0 <- vBB
4467 .if 0
4468 # is second operand zero?
4469 beqz a1, common_errDivideByZero
4470 .endif
4471
4472 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4473 # optional op
4474 mul a0, a0, a1 # a0 <- op, a0-a3 changed
4475 GET_INST_OPCODE(t0) # extract opcode from rINST
4476 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4477 /* 11-14 instructions */
4478
4479
4480/* ------------------------------ */
4481 .balign 128
4482.L_op_div_int: /* 0x93 */
4483/* File: mips/op_div_int.S */
4484#ifdef MIPS32REVGE6
4485/* File: mips/binop.S */
4486 /*
4487 * Generic 32-bit binary operation. Provide an "instr" line that
4488 * specifies an instruction that performs "result = a0 op a1".
4489 * This could be a MIPS instruction or a function call. (If the result
4490 * comes back in a register other than a0, you can override "result".)
4491 *
4492 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4493 * vCC (a1). Useful for integer division and modulus. Note that we
4494 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4495 * handles it correctly.
4496 *
4497 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4498 * xor-int, shl-int, shr-int, ushr-int
4499 */
4500 /* binop vAA, vBB, vCC */
4501 FETCH(a0, 1) # a0 <- CCBB
4502 GET_OPA(rOBJ) # rOBJ <- AA
4503 srl a3, a0, 8 # a3 <- CC
4504 and a2, a0, 255 # a2 <- BB
4505 GET_VREG(a1, a3) # a1 <- vCC
4506 GET_VREG(a0, a2) # a0 <- vBB
4507 .if 1
4508 # is second operand zero?
4509 beqz a1, common_errDivideByZero
4510 .endif
4511
4512 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4513 # optional op
4514 div a0, a0, a1 # a0 <- op, a0-a3 changed
4515 GET_INST_OPCODE(t0) # extract opcode from rINST
4516 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4517 /* 11-14 instructions */
4518
4519#else
4520/* File: mips/binop.S */
4521 /*
4522 * Generic 32-bit binary operation. Provide an "instr" line that
4523 * specifies an instruction that performs "result = a0 op a1".
4524 * This could be a MIPS instruction or a function call. (If the result
4525 * comes back in a register other than a0, you can override "result".)
4526 *
4527 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4528 * vCC (a1). Useful for integer division and modulus. Note that we
4529 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4530 * handles it correctly.
4531 *
4532 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4533 * xor-int, shl-int, shr-int, ushr-int
4534 */
4535 /* binop vAA, vBB, vCC */
4536 FETCH(a0, 1) # a0 <- CCBB
4537 GET_OPA(rOBJ) # rOBJ <- AA
4538 srl a3, a0, 8 # a3 <- CC
4539 and a2, a0, 255 # a2 <- BB
4540 GET_VREG(a1, a3) # a1 <- vCC
4541 GET_VREG(a0, a2) # a0 <- vBB
4542 .if 1
4543 # is second operand zero?
4544 beqz a1, common_errDivideByZero
4545 .endif
4546
4547 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4548 div zero, a0, a1 # optional op
4549 mflo a0 # a0 <- op, a0-a3 changed
4550 GET_INST_OPCODE(t0) # extract opcode from rINST
4551 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4552 /* 11-14 instructions */
4553
4554#endif
4555
4556/* ------------------------------ */
4557 .balign 128
4558.L_op_rem_int: /* 0x94 */
4559/* File: mips/op_rem_int.S */
4560#ifdef MIPS32REVGE6
4561/* File: mips/binop.S */
4562 /*
4563 * Generic 32-bit binary operation. Provide an "instr" line that
4564 * specifies an instruction that performs "result = a0 op a1".
4565 * This could be a MIPS instruction or a function call. (If the result
4566 * comes back in a register other than a0, you can override "result".)
4567 *
4568 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4569 * vCC (a1). Useful for integer division and modulus. Note that we
4570 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4571 * handles it correctly.
4572 *
4573 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4574 * xor-int, shl-int, shr-int, ushr-int
4575 */
4576 /* binop vAA, vBB, vCC */
4577 FETCH(a0, 1) # a0 <- CCBB
4578 GET_OPA(rOBJ) # rOBJ <- AA
4579 srl a3, a0, 8 # a3 <- CC
4580 and a2, a0, 255 # a2 <- BB
4581 GET_VREG(a1, a3) # a1 <- vCC
4582 GET_VREG(a0, a2) # a0 <- vBB
4583 .if 1
4584 # is second operand zero?
4585 beqz a1, common_errDivideByZero
4586 .endif
4587
4588 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4589 # optional op
4590 mod a0, a0, a1 # a0 <- op, a0-a3 changed
4591 GET_INST_OPCODE(t0) # extract opcode from rINST
4592 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4593 /* 11-14 instructions */
4594
4595#else
4596/* File: mips/binop.S */
4597 /*
4598 * Generic 32-bit binary operation. Provide an "instr" line that
4599 * specifies an instruction that performs "result = a0 op a1".
4600 * This could be a MIPS instruction or a function call. (If the result
4601 * comes back in a register other than a0, you can override "result".)
4602 *
4603 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4604 * vCC (a1). Useful for integer division and modulus. Note that we
4605 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4606 * handles it correctly.
4607 *
4608 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4609 * xor-int, shl-int, shr-int, ushr-int
4610 */
4611 /* binop vAA, vBB, vCC */
4612 FETCH(a0, 1) # a0 <- CCBB
4613 GET_OPA(rOBJ) # rOBJ <- AA
4614 srl a3, a0, 8 # a3 <- CC
4615 and a2, a0, 255 # a2 <- BB
4616 GET_VREG(a1, a3) # a1 <- vCC
4617 GET_VREG(a0, a2) # a0 <- vBB
4618 .if 1
4619 # is second operand zero?
4620 beqz a1, common_errDivideByZero
4621 .endif
4622
4623 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4624 div zero, a0, a1 # optional op
4625 mfhi a0 # a0 <- op, a0-a3 changed
4626 GET_INST_OPCODE(t0) # extract opcode from rINST
4627 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4628 /* 11-14 instructions */
4629
4630#endif
4631
4632/* ------------------------------ */
4633 .balign 128
4634.L_op_and_int: /* 0x95 */
4635/* File: mips/op_and_int.S */
4636/* File: mips/binop.S */
4637 /*
4638 * Generic 32-bit binary operation. Provide an "instr" line that
4639 * specifies an instruction that performs "result = a0 op a1".
4640 * This could be a MIPS instruction or a function call. (If the result
4641 * comes back in a register other than a0, you can override "result".)
4642 *
4643 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4644 * vCC (a1). Useful for integer division and modulus. Note that we
4645 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4646 * handles it correctly.
4647 *
4648 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4649 * xor-int, shl-int, shr-int, ushr-int
4650 */
4651 /* binop vAA, vBB, vCC */
4652 FETCH(a0, 1) # a0 <- CCBB
4653 GET_OPA(rOBJ) # rOBJ <- AA
4654 srl a3, a0, 8 # a3 <- CC
4655 and a2, a0, 255 # a2 <- BB
4656 GET_VREG(a1, a3) # a1 <- vCC
4657 GET_VREG(a0, a2) # a0 <- vBB
4658 .if 0
4659 # is second operand zero?
4660 beqz a1, common_errDivideByZero
4661 .endif
4662
4663 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4664 # optional op
4665 and a0, a0, a1 # a0 <- op, a0-a3 changed
4666 GET_INST_OPCODE(t0) # extract opcode from rINST
4667 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4668 /* 11-14 instructions */
4669
4670
4671/* ------------------------------ */
4672 .balign 128
4673.L_op_or_int: /* 0x96 */
4674/* File: mips/op_or_int.S */
4675/* File: mips/binop.S */
4676 /*
4677 * Generic 32-bit binary operation. Provide an "instr" line that
4678 * specifies an instruction that performs "result = a0 op a1".
4679 * This could be a MIPS instruction or a function call. (If the result
4680 * comes back in a register other than a0, you can override "result".)
4681 *
4682 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4683 * vCC (a1). Useful for integer division and modulus. Note that we
4684 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4685 * handles it correctly.
4686 *
4687 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4688 * xor-int, shl-int, shr-int, ushr-int
4689 */
4690 /* binop vAA, vBB, vCC */
4691 FETCH(a0, 1) # a0 <- CCBB
4692 GET_OPA(rOBJ) # rOBJ <- AA
4693 srl a3, a0, 8 # a3 <- CC
4694 and a2, a0, 255 # a2 <- BB
4695 GET_VREG(a1, a3) # a1 <- vCC
4696 GET_VREG(a0, a2) # a0 <- vBB
4697 .if 0
4698 # is second operand zero?
4699 beqz a1, common_errDivideByZero
4700 .endif
4701
4702 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4703 # optional op
4704 or a0, a0, a1 # a0 <- op, a0-a3 changed
4705 GET_INST_OPCODE(t0) # extract opcode from rINST
4706 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4707 /* 11-14 instructions */
4708
4709
4710/* ------------------------------ */
4711 .balign 128
4712.L_op_xor_int: /* 0x97 */
4713/* File: mips/op_xor_int.S */
4714/* File: mips/binop.S */
4715 /*
4716 * Generic 32-bit binary operation. Provide an "instr" line that
4717 * specifies an instruction that performs "result = a0 op a1".
4718 * This could be a MIPS instruction or a function call. (If the result
4719 * comes back in a register other than a0, you can override "result".)
4720 *
4721 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4722 * vCC (a1). Useful for integer division and modulus. Note that we
4723 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4724 * handles it correctly.
4725 *
4726 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4727 * xor-int, shl-int, shr-int, ushr-int
4728 */
4729 /* binop vAA, vBB, vCC */
4730 FETCH(a0, 1) # a0 <- CCBB
4731 GET_OPA(rOBJ) # rOBJ <- AA
4732 srl a3, a0, 8 # a3 <- CC
4733 and a2, a0, 255 # a2 <- BB
4734 GET_VREG(a1, a3) # a1 <- vCC
4735 GET_VREG(a0, a2) # a0 <- vBB
4736 .if 0
4737 # is second operand zero?
4738 beqz a1, common_errDivideByZero
4739 .endif
4740
4741 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4742 # optional op
4743 xor a0, a0, a1 # a0 <- op, a0-a3 changed
4744 GET_INST_OPCODE(t0) # extract opcode from rINST
4745 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4746 /* 11-14 instructions */
4747
4748
4749/* ------------------------------ */
4750 .balign 128
4751.L_op_shl_int: /* 0x98 */
4752/* File: mips/op_shl_int.S */
4753/* File: mips/binop.S */
4754 /*
4755 * Generic 32-bit binary operation. Provide an "instr" line that
4756 * specifies an instruction that performs "result = a0 op a1".
4757 * This could be a MIPS instruction or a function call. (If the result
4758 * comes back in a register other than a0, you can override "result".)
4759 *
4760 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4761 * vCC (a1). Useful for integer division and modulus. Note that we
4762 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4763 * handles it correctly.
4764 *
4765 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4766 * xor-int, shl-int, shr-int, ushr-int
4767 */
4768 /* binop vAA, vBB, vCC */
4769 FETCH(a0, 1) # a0 <- CCBB
4770 GET_OPA(rOBJ) # rOBJ <- AA
4771 srl a3, a0, 8 # a3 <- CC
4772 and a2, a0, 255 # a2 <- BB
4773 GET_VREG(a1, a3) # a1 <- vCC
4774 GET_VREG(a0, a2) # a0 <- vBB
4775 .if 0
4776 # is second operand zero?
4777 beqz a1, common_errDivideByZero
4778 .endif
4779
4780 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4781 # optional op
4782 sll a0, a0, a1 # a0 <- op, a0-a3 changed
4783 GET_INST_OPCODE(t0) # extract opcode from rINST
4784 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4785 /* 11-14 instructions */
4786
4787
4788/* ------------------------------ */
4789 .balign 128
4790.L_op_shr_int: /* 0x99 */
4791/* File: mips/op_shr_int.S */
4792/* File: mips/binop.S */
4793 /*
4794 * Generic 32-bit binary operation. Provide an "instr" line that
4795 * specifies an instruction that performs "result = a0 op a1".
4796 * This could be a MIPS instruction or a function call. (If the result
4797 * comes back in a register other than a0, you can override "result".)
4798 *
4799 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4800 * vCC (a1). Useful for integer division and modulus. Note that we
4801 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4802 * handles it correctly.
4803 *
4804 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4805 * xor-int, shl-int, shr-int, ushr-int
4806 */
4807 /* binop vAA, vBB, vCC */
4808 FETCH(a0, 1) # a0 <- CCBB
4809 GET_OPA(rOBJ) # rOBJ <- AA
4810 srl a3, a0, 8 # a3 <- CC
4811 and a2, a0, 255 # a2 <- BB
4812 GET_VREG(a1, a3) # a1 <- vCC
4813 GET_VREG(a0, a2) # a0 <- vBB
4814 .if 0
4815 # is second operand zero?
4816 beqz a1, common_errDivideByZero
4817 .endif
4818
4819 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4820 # optional op
4821 sra a0, a0, a1 # a0 <- op, a0-a3 changed
4822 GET_INST_OPCODE(t0) # extract opcode from rINST
4823 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4824 /* 11-14 instructions */
4825
4826
4827/* ------------------------------ */
4828 .balign 128
4829.L_op_ushr_int: /* 0x9a */
4830/* File: mips/op_ushr_int.S */
4831/* File: mips/binop.S */
4832 /*
4833 * Generic 32-bit binary operation. Provide an "instr" line that
4834 * specifies an instruction that performs "result = a0 op a1".
4835 * This could be a MIPS instruction or a function call. (If the result
4836 * comes back in a register other than a0, you can override "result".)
4837 *
4838 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4839 * vCC (a1). Useful for integer division and modulus. Note that we
4840 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4841 * handles it correctly.
4842 *
4843 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4844 * xor-int, shl-int, shr-int, ushr-int
4845 */
4846 /* binop vAA, vBB, vCC */
4847 FETCH(a0, 1) # a0 <- CCBB
4848 GET_OPA(rOBJ) # rOBJ <- AA
4849 srl a3, a0, 8 # a3 <- CC
4850 and a2, a0, 255 # a2 <- BB
4851 GET_VREG(a1, a3) # a1 <- vCC
4852 GET_VREG(a0, a2) # a0 <- vBB
4853 .if 0
4854 # is second operand zero?
4855 beqz a1, common_errDivideByZero
4856 .endif
4857
4858 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4859 # optional op
4860 srl a0, a0, a1 # a0 <- op, a0-a3 changed
4861 GET_INST_OPCODE(t0) # extract opcode from rINST
4862 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
4863 /* 11-14 instructions */
4864
4865
4866/* ------------------------------ */
4867 .balign 128
4868.L_op_add_long: /* 0x9b */
4869/* File: mips/op_add_long.S */
4870/*
4871 * The compiler generates the following sequence for
4872 * [v1 v0] = [a1 a0] + [a3 a2];
4873 * addu v0,a2,a0
4874 * addu a1,a3,a1
4875 * sltu v1,v0,a2
4876 * addu v1,v1,a1
4877 */
4878/* File: mips/binopWide.S */
4879 /*
4880 * Generic 64-bit binary operation. Provide an "instr" line that
4881 * specifies an instruction that performs "result = a0-a1 op a2-a3".
4882 * This could be a MIPS instruction or a function call. (If the result
4883 * comes back in a register other than a0, you can override "result".)
4884 *
4885 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4886 * vCC (a1). Useful for integer division and modulus.
4887 *
4888 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4889 * xor-long
4890 *
4891 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4892 */
4893 /* binop vAA, vBB, vCC */
4894 FETCH(a0, 1) # a0 <- CCBB
4895 GET_OPA(rOBJ) # rOBJ <- AA
4896 and a2, a0, 255 # a2 <- BB
4897 srl a3, a0, 8 # a3 <- CC
4898 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
4899 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
4900 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
4901 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
4902 .if 0
4903 or t0, a2, a3 # second arg (a2-a3) is zero?
4904 beqz t0, common_errDivideByZero
4905 .endif
4906 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4907
4908 addu v0, a2, a0 # optional op
4909 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed
4910 GET_INST_OPCODE(t0) # extract opcode from rINST
4911 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1
4912 /* 14-17 instructions */
4913
4914
4915/* ------------------------------ */
4916 .balign 128
4917.L_op_sub_long: /* 0x9c */
4918/* File: mips/op_sub_long.S */
4919/*
4920 * For little endian the code sequence looks as follows:
4921 * subu v0,a0,a2
4922 * subu v1,a1,a3
4923 * sltu a0,a0,v0
4924 * subu v1,v1,a0
4925 */
4926/* File: mips/binopWide.S */
4927 /*
4928 * Generic 64-bit binary operation. Provide an "instr" line that
4929 * specifies an instruction that performs "result = a0-a1 op a2-a3".
4930 * This could be a MIPS instruction or a function call. (If the result
4931 * comes back in a register other than a0, you can override "result".)
4932 *
4933 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4934 * vCC (a1). Useful for integer division and modulus.
4935 *
4936 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4937 * xor-long
4938 *
4939 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4940 */
4941 /* binop vAA, vBB, vCC */
4942 FETCH(a0, 1) # a0 <- CCBB
4943 GET_OPA(rOBJ) # rOBJ <- AA
4944 and a2, a0, 255 # a2 <- BB
4945 srl a3, a0, 8 # a3 <- CC
4946 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
4947 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
4948 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
4949 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
4950 .if 0
4951 or t0, a2, a3 # second arg (a2-a3) is zero?
4952 beqz t0, common_errDivideByZero
4953 .endif
4954 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
4955
4956 subu v0, a0, a2 # optional op
4957 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed
4958 GET_INST_OPCODE(t0) # extract opcode from rINST
4959 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1
4960 /* 14-17 instructions */
4961
4962
4963/* ------------------------------ */
4964 .balign 128
4965.L_op_mul_long: /* 0x9d */
4966/* File: mips/op_mul_long.S */
4967 /*
4968 * Signed 64-bit integer multiply.
4969 * a1 a0
4970 * x a3 a2
4971 * -------------
4972 * a2a1 a2a0
4973 * a3a0
4974 * a3a1 (<= unused)
4975 * ---------------
4976 * v1 v0
4977 */
4978 /* mul-long vAA, vBB, vCC */
4979 FETCH(a0, 1) # a0 <- CCBB
4980 and t0, a0, 255 # a2 <- BB
4981 srl t1, a0, 8 # a3 <- CC
4982 EAS2(t0, rFP, t0) # t0 <- &fp[BB]
4983 LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1
4984
4985 EAS2(t1, rFP, t1) # t0 <- &fp[CC]
4986 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
4987
4988 mul v1, a3, a0 # v1= a3a0
4989#ifdef MIPS32REVGE6
4990 mulu v0, a2, a0 # v0= a2a0
4991 muhu t1, a2, a0
4992#else
4993 multu a2, a0
4994 mfhi t1
4995 mflo v0 # v0= a2a0
4996#endif
4997 mul t0, a2, a1 # t0= a2a1
4998 addu v1, v1, t1 # v1+= hi(a2a0)
4999 addu v1, v1, t0 # v1= a3a0 + a2a1;
5000
5001 GET_OPA(a0) # a0 <- AA
5002 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5003 b .Lop_mul_long_finish
5004
5005/* ------------------------------ */
5006 .balign 128
5007.L_op_div_long: /* 0x9e */
5008/* File: mips/op_div_long.S */
5009/* File: mips/binopWide.S */
5010 /*
5011 * Generic 64-bit binary operation. Provide an "instr" line that
5012 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5013 * This could be a MIPS instruction or a function call. (If the result
5014 * comes back in a register other than a0, you can override "result".)
5015 *
5016 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5017 * vCC (a1). Useful for integer division and modulus.
5018 *
5019 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5020 * xor-long
5021 *
5022 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5023 */
5024 /* binop vAA, vBB, vCC */
5025 FETCH(a0, 1) # a0 <- CCBB
5026 GET_OPA(rOBJ) # rOBJ <- AA
5027 and a2, a0, 255 # a2 <- BB
5028 srl a3, a0, 8 # a3 <- CC
5029 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5030 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5031 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5032 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
5033 .if 1
5034 or t0, a2, a3 # second arg (a2-a3) is zero?
5035 beqz t0, common_errDivideByZero
5036 .endif
5037 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5038
5039 # optional op
5040 JAL(__divdi3) # result <- op, a0-a3 changed
5041 GET_INST_OPCODE(t0) # extract opcode from rINST
5042 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1
5043 /* 14-17 instructions */
5044
5045
5046/* ------------------------------ */
5047 .balign 128
5048.L_op_rem_long: /* 0x9f */
5049/* File: mips/op_rem_long.S */
5050/* File: mips/binopWide.S */
5051 /*
5052 * Generic 64-bit binary operation. Provide an "instr" line that
5053 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5054 * This could be a MIPS instruction or a function call. (If the result
5055 * comes back in a register other than a0, you can override "result".)
5056 *
5057 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5058 * vCC (a1). Useful for integer division and modulus.
5059 *
5060 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5061 * xor-long
5062 *
5063 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5064 */
5065 /* binop vAA, vBB, vCC */
5066 FETCH(a0, 1) # a0 <- CCBB
5067 GET_OPA(rOBJ) # rOBJ <- AA
5068 and a2, a0, 255 # a2 <- BB
5069 srl a3, a0, 8 # a3 <- CC
5070 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5071 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5072 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5073 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
5074 .if 1
5075 or t0, a2, a3 # second arg (a2-a3) is zero?
5076 beqz t0, common_errDivideByZero
5077 .endif
5078 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5079
5080 # optional op
5081 JAL(__moddi3) # result <- op, a0-a3 changed
5082 GET_INST_OPCODE(t0) # extract opcode from rINST
5083 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1
5084 /* 14-17 instructions */
5085
5086
5087/* ------------------------------ */
5088 .balign 128
5089.L_op_and_long: /* 0xa0 */
5090/* File: mips/op_and_long.S */
5091/* File: mips/binopWide.S */
5092 /*
5093 * Generic 64-bit binary operation. Provide an "instr" line that
5094 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5095 * This could be a MIPS instruction or a function call. (If the result
5096 * comes back in a register other than a0, you can override "result".)
5097 *
5098 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5099 * vCC (a1). Useful for integer division and modulus.
5100 *
5101 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5102 * xor-long
5103 *
5104 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5105 */
5106 /* binop vAA, vBB, vCC */
5107 FETCH(a0, 1) # a0 <- CCBB
5108 GET_OPA(rOBJ) # rOBJ <- AA
5109 and a2, a0, 255 # a2 <- BB
5110 srl a3, a0, 8 # a3 <- CC
5111 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5112 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5113 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5114 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
5115 .if 0
5116 or t0, a2, a3 # second arg (a2-a3) is zero?
5117 beqz t0, common_errDivideByZero
5118 .endif
5119 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5120
5121 and a0, a0, a2 # optional op
5122 and a1, a1, a3 # result <- op, a0-a3 changed
5123 GET_INST_OPCODE(t0) # extract opcode from rINST
5124 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5125 /* 14-17 instructions */
5126
5127
5128/* ------------------------------ */
5129 .balign 128
5130.L_op_or_long: /* 0xa1 */
5131/* File: mips/op_or_long.S */
5132/* File: mips/binopWide.S */
5133 /*
5134 * Generic 64-bit binary operation. Provide an "instr" line that
5135 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5136 * This could be a MIPS instruction or a function call. (If the result
5137 * comes back in a register other than a0, you can override "result".)
5138 *
5139 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5140 * vCC (a1). Useful for integer division and modulus.
5141 *
5142 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5143 * xor-long
5144 *
5145 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5146 */
5147 /* binop vAA, vBB, vCC */
5148 FETCH(a0, 1) # a0 <- CCBB
5149 GET_OPA(rOBJ) # rOBJ <- AA
5150 and a2, a0, 255 # a2 <- BB
5151 srl a3, a0, 8 # a3 <- CC
5152 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5153 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5154 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5155 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
5156 .if 0
5157 or t0, a2, a3 # second arg (a2-a3) is zero?
5158 beqz t0, common_errDivideByZero
5159 .endif
5160 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5161
5162 or a0, a0, a2 # optional op
5163 or a1, a1, a3 # result <- op, a0-a3 changed
5164 GET_INST_OPCODE(t0) # extract opcode from rINST
5165 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5166 /* 14-17 instructions */
5167
5168
5169/* ------------------------------ */
5170 .balign 128
5171.L_op_xor_long: /* 0xa2 */
5172/* File: mips/op_xor_long.S */
5173/* File: mips/binopWide.S */
5174 /*
5175 * Generic 64-bit binary operation. Provide an "instr" line that
5176 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5177 * This could be a MIPS instruction or a function call. (If the result
5178 * comes back in a register other than a0, you can override "result".)
5179 *
5180 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5181 * vCC (a1). Useful for integer division and modulus.
5182 *
5183 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5184 * xor-long
5185 *
5186 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5187 */
5188 /* binop vAA, vBB, vCC */
5189 FETCH(a0, 1) # a0 <- CCBB
5190 GET_OPA(rOBJ) # rOBJ <- AA
5191 and a2, a0, 255 # a2 <- BB
5192 srl a3, a0, 8 # a3 <- CC
5193 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5194 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5195 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1
5196 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1
5197 .if 0
5198 or t0, a2, a3 # second arg (a2-a3) is zero?
5199 beqz t0, common_errDivideByZero
5200 .endif
5201 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5202
5203 xor a0, a0, a2 # optional op
5204 xor a1, a1, a3 # result <- op, a0-a3 changed
5205 GET_INST_OPCODE(t0) # extract opcode from rINST
5206 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
5207 /* 14-17 instructions */
5208
5209
5210/* ------------------------------ */
5211 .balign 128
5212.L_op_shl_long: /* 0xa3 */
5213/* File: mips/op_shl_long.S */
5214 /*
5215 * Long integer shift. This is different from the generic 32/64-bit
5216 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5217 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5218 * 6 bits of the shift distance.
5219 */
5220 /* shl-long vAA, vBB, vCC */
5221 FETCH(a0, 1) # a0 <- CCBB
5222 GET_OPA(t2) # t2 <- AA
5223 and a3, a0, 255 # a3 <- BB
5224 srl a0, a0, 8 # a0 <- CC
5225 EAS2(a3, rFP, a3) # a3 <- &fp[BB]
5226 GET_VREG(a2, a0) # a2 <- vCC
5227 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5228
5229 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5230 GET_INST_OPCODE(t0) # extract opcode from rINST
5231
5232 andi v1, a2, 0x20 # shift< shift & 0x20
5233 sll v0, a0, a2 # rlo<- alo << (shift&31)
5234 bnez v1, .Lop_shl_long_finish
5235 not v1, a2 # rhi<- 31-shift (shift is 5b)
5236 srl a0, 1
5237 srl a0, v1 # alo<- alo >> (32-(shift&31))
5238 sll v1, a1, a2 # rhi<- ahi << (shift&31)
5239 or v1, a0 # rhi<- rhi | alo
5240 SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1
5241
5242/* ------------------------------ */
5243 .balign 128
5244.L_op_shr_long: /* 0xa4 */
5245/* File: mips/op_shr_long.S */
5246 /*
5247 * Long integer shift. This is different from the generic 32/64-bit
5248 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5249 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5250 * 6 bits of the shift distance.
5251 */
5252 /* shr-long vAA, vBB, vCC */
5253 FETCH(a0, 1) # a0 <- CCBB
5254 GET_OPA(t3) # t3 <- AA
5255 and a3, a0, 255 # a3 <- BB
5256 srl a0, a0, 8 # a0 <- CC
5257 EAS2(a3, rFP, a3) # a3 <- &fp[BB]
5258 GET_VREG(a2, a0) # a2 <- vCC
5259 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5260 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5261 GET_INST_OPCODE(t0) # extract opcode from rINST
5262
5263 andi v0, a2, 0x20 # shift & 0x20
5264 sra v1, a1, a2 # rhi<- ahi >> (shift&31)
5265 bnez v0, .Lop_shr_long_finish
5266 srl v0, a0, a2 # rlo<- alo >> (shift&31)
5267 not a0, a2 # alo<- 31-shift (shift is 5b)
5268 sll a1, 1
5269 sll a1, a0 # ahi<- ahi << (32-(shift&31))
5270 or v0, a1 # rlo<- rlo | ahi
5271 SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v0
5272
5273/* ------------------------------ */
5274 .balign 128
5275.L_op_ushr_long: /* 0xa5 */
5276/* File: mips/op_ushr_long.S */
5277 /*
5278 * Long integer shift. This is different from the generic 32/64-bit
5279 * binary operations because vAA/vBB are 64-bit but vCC (the shift
5280 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
5281 * 6 bits of the shift distance.
5282 */
5283 /* ushr-long vAA, vBB, vCC */
5284 FETCH(a0, 1) # a0 <- CCBB
5285 GET_OPA(rOBJ) # rOBJ <- AA
5286 and a3, a0, 255 # a3 <- BB
5287 srl a0, a0, 8 # a0 <- CC
5288 EAS2(a3, rFP, a3) # a3 <- &fp[BB]
5289 GET_VREG(a2, a0) # a2 <- vCC
5290 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1
5291
5292 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5293 GET_INST_OPCODE(t0) # extract opcode from rINST
5294
5295 andi v0, a2, 0x20 # shift & 0x20
5296 srl v1, a1, a2 # rhi<- ahi >> (shift&31)
5297 bnez v0, .Lop_ushr_long_finish
5298 srl v0, a0, a2 # rlo<- alo >> (shift&31)
5299 not a0, a2 # alo<- 31-n (shift is 5b)
5300 sll a1, 1
5301 sll a1, a0 # ahi<- ahi << (32-(shift&31))
5302 or v0, a1 # rlo<- rlo | ahi
5303 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1
5304
5305/* ------------------------------ */
5306 .balign 128
5307.L_op_add_float: /* 0xa6 */
5308/* File: mips/op_add_float.S */
5309/* File: mips/fbinop.S */
5310 /*
5311 * Generic 32-bit binary float operation.
5312 *
5313 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp
5314 */
5315
5316 /* binop vAA, vBB, vCC */
5317 FETCH(a0, 1) # a0 <- CCBB
5318 GET_OPA(rOBJ) # s5 <- AA
5319 srl a3, a0, 8 # a3 <- CC
5320 and a2, a0, 255 # a2 <- BB
5321 GET_VREG_F(fa1, a3) # a1 <- vCC
5322 GET_VREG_F(fa0, a2) # a0 <- vBB
5323
5324 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5325 add.s fv0, fa0, fa1 # f0 = result
5326 SET_VREG_F(fv0, rOBJ) # vAA <- fv0
5327 GET_INST_OPCODE(t0) # extract opcode from rINST
5328 GOTO_OPCODE(t0) # jump to next instruction
5329
5330
5331/* ------------------------------ */
5332 .balign 128
5333.L_op_sub_float: /* 0xa7 */
5334/* File: mips/op_sub_float.S */
5335/* File: mips/fbinop.S */
5336 /*
5337 * Generic 32-bit binary float operation.
5338 *
5339 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp
5340 */
5341
5342 /* binop vAA, vBB, vCC */
5343 FETCH(a0, 1) # a0 <- CCBB
5344 GET_OPA(rOBJ) # s5 <- AA
5345 srl a3, a0, 8 # a3 <- CC
5346 and a2, a0, 255 # a2 <- BB
5347 GET_VREG_F(fa1, a3) # a1 <- vCC
5348 GET_VREG_F(fa0, a2) # a0 <- vBB
5349
5350 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5351 sub.s fv0, fa0, fa1 # f0 = result
5352 SET_VREG_F(fv0, rOBJ) # vAA <- fv0
5353 GET_INST_OPCODE(t0) # extract opcode from rINST
5354 GOTO_OPCODE(t0) # jump to next instruction
5355
5356
5357/* ------------------------------ */
5358 .balign 128
5359.L_op_mul_float: /* 0xa8 */
5360/* File: mips/op_mul_float.S */
5361/* File: mips/fbinop.S */
5362 /*
5363 * Generic 32-bit binary float operation.
5364 *
5365 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp
5366 */
5367
5368 /* binop vAA, vBB, vCC */
5369 FETCH(a0, 1) # a0 <- CCBB
5370 GET_OPA(rOBJ) # s5 <- AA
5371 srl a3, a0, 8 # a3 <- CC
5372 and a2, a0, 255 # a2 <- BB
5373 GET_VREG_F(fa1, a3) # a1 <- vCC
5374 GET_VREG_F(fa0, a2) # a0 <- vBB
5375
5376 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5377 mul.s fv0, fa0, fa1 # f0 = result
5378 SET_VREG_F(fv0, rOBJ) # vAA <- fv0
5379 GET_INST_OPCODE(t0) # extract opcode from rINST
5380 GOTO_OPCODE(t0) # jump to next instruction
5381
5382
5383/* ------------------------------ */
5384 .balign 128
5385.L_op_div_float: /* 0xa9 */
5386/* File: mips/op_div_float.S */
5387/* File: mips/fbinop.S */
5388 /*
5389 * Generic 32-bit binary float operation.
5390 *
5391 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp
5392 */
5393
5394 /* binop vAA, vBB, vCC */
5395 FETCH(a0, 1) # a0 <- CCBB
5396 GET_OPA(rOBJ) # s5 <- AA
5397 srl a3, a0, 8 # a3 <- CC
5398 and a2, a0, 255 # a2 <- BB
5399 GET_VREG_F(fa1, a3) # a1 <- vCC
5400 GET_VREG_F(fa0, a2) # a0 <- vBB
5401
5402 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5403 div.s fv0, fa0, fa1 # f0 = result
5404 SET_VREG_F(fv0, rOBJ) # vAA <- fv0
5405 GET_INST_OPCODE(t0) # extract opcode from rINST
5406 GOTO_OPCODE(t0) # jump to next instruction
5407
5408
5409/* ------------------------------ */
5410 .balign 128
5411.L_op_rem_float: /* 0xaa */
5412/* File: mips/op_rem_float.S */
5413/* File: mips/fbinop.S */
5414 /*
5415 * Generic 32-bit binary float operation.
5416 *
5417 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp
5418 */
5419
5420 /* binop vAA, vBB, vCC */
5421 FETCH(a0, 1) # a0 <- CCBB
5422 GET_OPA(rOBJ) # s5 <- AA
5423 srl a3, a0, 8 # a3 <- CC
5424 and a2, a0, 255 # a2 <- BB
5425 GET_VREG_F(fa1, a3) # a1 <- vCC
5426 GET_VREG_F(fa0, a2) # a0 <- vBB
5427
5428 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5429 JAL(fmodf) # f0 = result
5430 SET_VREG_F(fv0, rOBJ) # vAA <- fv0
5431 GET_INST_OPCODE(t0) # extract opcode from rINST
5432 GOTO_OPCODE(t0) # jump to next instruction
5433
5434
5435/* ------------------------------ */
5436 .balign 128
5437.L_op_add_double: /* 0xab */
5438/* File: mips/op_add_double.S */
5439/* File: mips/fbinopWide.S */
5440 /*
5441 * Generic 64-bit binary operation. Provide an "instr" line that
5442 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5443 * This could be an MIPS instruction or a function call.
5444 *
5445 * for: add-double, sub-double, mul-double, div-double,
5446 * rem-double
5447 *
5448 */
5449 /* binop vAA, vBB, vCC */
5450 FETCH(a0, 1) # a0 <- CCBB
5451 GET_OPA(rOBJ) # s5 <- AA
5452 and a2, a0, 255 # a2 <- BB
5453 srl a3, a0, 8 # a3 <- CC
5454 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5455 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5456 LOAD64_F(fa0, fa0f, a2)
5457 LOAD64_F(fa1, fa1f, t1)
5458
5459 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5460 add.d fv0, fa0, fa1
5461 SET_VREG64_F(fv0, fv0f, rOBJ)
5462 b .Lop_add_double_finish
5463
5464
5465/* ------------------------------ */
5466 .balign 128
5467.L_op_sub_double: /* 0xac */
5468/* File: mips/op_sub_double.S */
5469/* File: mips/fbinopWide.S */
5470 /*
5471 * Generic 64-bit binary operation. Provide an "instr" line that
5472 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5473 * This could be an MIPS instruction or a function call.
5474 *
5475 * for: add-double, sub-double, mul-double, div-double,
5476 * rem-double
5477 *
5478 */
5479 /* binop vAA, vBB, vCC */
5480 FETCH(a0, 1) # a0 <- CCBB
5481 GET_OPA(rOBJ) # s5 <- AA
5482 and a2, a0, 255 # a2 <- BB
5483 srl a3, a0, 8 # a3 <- CC
5484 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5485 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5486 LOAD64_F(fa0, fa0f, a2)
5487 LOAD64_F(fa1, fa1f, t1)
5488
5489 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5490 sub.d fv0, fa0, fa1
5491 SET_VREG64_F(fv0, fv0f, rOBJ)
5492 b .Lop_sub_double_finish
5493
5494
5495/* ------------------------------ */
5496 .balign 128
5497.L_op_mul_double: /* 0xad */
5498/* File: mips/op_mul_double.S */
5499/* File: mips/fbinopWide.S */
5500 /*
5501 * Generic 64-bit binary operation. Provide an "instr" line that
5502 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5503 * This could be an MIPS instruction or a function call.
5504 *
5505 * for: add-double, sub-double, mul-double, div-double,
5506 * rem-double
5507 *
5508 */
5509 /* binop vAA, vBB, vCC */
5510 FETCH(a0, 1) # a0 <- CCBB
5511 GET_OPA(rOBJ) # s5 <- AA
5512 and a2, a0, 255 # a2 <- BB
5513 srl a3, a0, 8 # a3 <- CC
5514 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5515 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5516 LOAD64_F(fa0, fa0f, a2)
5517 LOAD64_F(fa1, fa1f, t1)
5518
5519 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5520 mul.d fv0, fa0, fa1
5521 SET_VREG64_F(fv0, fv0f, rOBJ)
5522 b .Lop_mul_double_finish
5523
5524
5525/* ------------------------------ */
5526 .balign 128
5527.L_op_div_double: /* 0xae */
5528/* File: mips/op_div_double.S */
5529/* File: mips/fbinopWide.S */
5530 /*
5531 * Generic 64-bit binary operation. Provide an "instr" line that
5532 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5533 * This could be an MIPS instruction or a function call.
5534 *
5535 * for: add-double, sub-double, mul-double, div-double,
5536 * rem-double
5537 *
5538 */
5539 /* binop vAA, vBB, vCC */
5540 FETCH(a0, 1) # a0 <- CCBB
5541 GET_OPA(rOBJ) # s5 <- AA
5542 and a2, a0, 255 # a2 <- BB
5543 srl a3, a0, 8 # a3 <- CC
5544 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5545 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5546 LOAD64_F(fa0, fa0f, a2)
5547 LOAD64_F(fa1, fa1f, t1)
5548
5549 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5550 div.d fv0, fa0, fa1
5551 SET_VREG64_F(fv0, fv0f, rOBJ)
5552 b .Lop_div_double_finish
5553
5554
5555/* ------------------------------ */
5556 .balign 128
5557.L_op_rem_double: /* 0xaf */
5558/* File: mips/op_rem_double.S */
5559/* File: mips/fbinopWide.S */
5560 /*
5561 * Generic 64-bit binary operation. Provide an "instr" line that
5562 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5563 * This could be an MIPS instruction or a function call.
5564 *
5565 * for: add-double, sub-double, mul-double, div-double,
5566 * rem-double
5567 *
5568 */
5569 /* binop vAA, vBB, vCC */
5570 FETCH(a0, 1) # a0 <- CCBB
5571 GET_OPA(rOBJ) # s5 <- AA
5572 and a2, a0, 255 # a2 <- BB
5573 srl a3, a0, 8 # a3 <- CC
5574 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
5575 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
5576 LOAD64_F(fa0, fa0f, a2)
5577 LOAD64_F(fa1, fa1f, t1)
5578
5579 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
5580 JAL(fmod)
5581 SET_VREG64_F(fv0, fv0f, rOBJ)
5582 b .Lop_rem_double_finish
5583
5584
5585/* ------------------------------ */
5586 .balign 128
5587.L_op_add_int_2addr: /* 0xb0 */
5588/* File: mips/op_add_int_2addr.S */
5589/* File: mips/binop2addr.S */
5590 /*
5591 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5592 * that specifies an instruction that performs "result = a0 op a1".
5593 * This could be an MIPS instruction or a function call.
5594 *
5595 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5596 * vCC (a1). Useful for integer division and modulus.
5597 *
5598 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5599 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5600 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5601 */
5602 /* binop/2addr vA, vB */
5603 GET_OPA4(rOBJ) # rOBJ <- A+
5604 GET_OPB(a3) # a3 <- B
5605 GET_VREG(a0, rOBJ) # a0 <- vA
5606 GET_VREG(a1, a3) # a1 <- vB
5607 .if 0
5608 # is second operand zero?
5609 beqz a1, common_errDivideByZero
5610 .endif
5611 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5612
5613 # optional op
5614 addu a0, a0, a1 # a0 <- op, a0-a3 changed
5615 GET_INST_OPCODE(t0) # extract opcode from rINST
5616 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5617 /* 10-13 instructions */
5618
5619
5620/* ------------------------------ */
5621 .balign 128
5622.L_op_sub_int_2addr: /* 0xb1 */
5623/* File: mips/op_sub_int_2addr.S */
5624/* File: mips/binop2addr.S */
5625 /*
5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5627 * that specifies an instruction that performs "result = a0 op a1".
5628 * This could be an MIPS instruction or a function call.
5629 *
5630 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5631 * vCC (a1). Useful for integer division and modulus.
5632 *
5633 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5634 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5635 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5636 */
5637 /* binop/2addr vA, vB */
5638 GET_OPA4(rOBJ) # rOBJ <- A+
5639 GET_OPB(a3) # a3 <- B
5640 GET_VREG(a0, rOBJ) # a0 <- vA
5641 GET_VREG(a1, a3) # a1 <- vB
5642 .if 0
5643 # is second operand zero?
5644 beqz a1, common_errDivideByZero
5645 .endif
5646 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5647
5648 # optional op
5649 subu a0, a0, a1 # a0 <- op, a0-a3 changed
5650 GET_INST_OPCODE(t0) # extract opcode from rINST
5651 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5652 /* 10-13 instructions */
5653
5654
5655/* ------------------------------ */
5656 .balign 128
5657.L_op_mul_int_2addr: /* 0xb2 */
5658/* File: mips/op_mul_int_2addr.S */
5659/* File: mips/binop2addr.S */
5660 /*
5661 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5662 * that specifies an instruction that performs "result = a0 op a1".
5663 * This could be an MIPS instruction or a function call.
5664 *
5665 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5666 * vCC (a1). Useful for integer division and modulus.
5667 *
5668 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5669 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5670 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5671 */
5672 /* binop/2addr vA, vB */
5673 GET_OPA4(rOBJ) # rOBJ <- A+
5674 GET_OPB(a3) # a3 <- B
5675 GET_VREG(a0, rOBJ) # a0 <- vA
5676 GET_VREG(a1, a3) # a1 <- vB
5677 .if 0
5678 # is second operand zero?
5679 beqz a1, common_errDivideByZero
5680 .endif
5681 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5682
5683 # optional op
5684 mul a0, a0, a1 # a0 <- op, a0-a3 changed
5685 GET_INST_OPCODE(t0) # extract opcode from rINST
5686 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5687 /* 10-13 instructions */
5688
5689
5690/* ------------------------------ */
5691 .balign 128
5692.L_op_div_int_2addr: /* 0xb3 */
5693/* File: mips/op_div_int_2addr.S */
5694#ifdef MIPS32REVGE6
5695/* File: mips/binop2addr.S */
5696 /*
5697 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5698 * that specifies an instruction that performs "result = a0 op a1".
5699 * This could be an MIPS instruction or a function call.
5700 *
5701 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5702 * vCC (a1). Useful for integer division and modulus.
5703 *
5704 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5705 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5706 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5707 */
5708 /* binop/2addr vA, vB */
5709 GET_OPA4(rOBJ) # rOBJ <- A+
5710 GET_OPB(a3) # a3 <- B
5711 GET_VREG(a0, rOBJ) # a0 <- vA
5712 GET_VREG(a1, a3) # a1 <- vB
5713 .if 1
5714 # is second operand zero?
5715 beqz a1, common_errDivideByZero
5716 .endif
5717 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5718
5719 # optional op
5720 div a0, a0, a1 # a0 <- op, a0-a3 changed
5721 GET_INST_OPCODE(t0) # extract opcode from rINST
5722 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5723 /* 10-13 instructions */
5724
5725#else
5726/* File: mips/binop2addr.S */
5727 /*
5728 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5729 * that specifies an instruction that performs "result = a0 op a1".
5730 * This could be an MIPS instruction or a function call.
5731 *
5732 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5733 * vCC (a1). Useful for integer division and modulus.
5734 *
5735 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5736 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5737 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5738 */
5739 /* binop/2addr vA, vB */
5740 GET_OPA4(rOBJ) # rOBJ <- A+
5741 GET_OPB(a3) # a3 <- B
5742 GET_VREG(a0, rOBJ) # a0 <- vA
5743 GET_VREG(a1, a3) # a1 <- vB
5744 .if 1
5745 # is second operand zero?
5746 beqz a1, common_errDivideByZero
5747 .endif
5748 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5749
5750 div zero, a0, a1 # optional op
5751 mflo a0 # a0 <- op, a0-a3 changed
5752 GET_INST_OPCODE(t0) # extract opcode from rINST
5753 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5754 /* 10-13 instructions */
5755
5756#endif
5757
5758/* ------------------------------ */
5759 .balign 128
5760.L_op_rem_int_2addr: /* 0xb4 */
5761/* File: mips/op_rem_int_2addr.S */
5762#ifdef MIPS32REVGE6
5763/* File: mips/binop2addr.S */
5764 /*
5765 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5766 * that specifies an instruction that performs "result = a0 op a1".
5767 * This could be an MIPS instruction or a function call.
5768 *
5769 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5770 * vCC (a1). Useful for integer division and modulus.
5771 *
5772 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5773 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5774 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5775 */
5776 /* binop/2addr vA, vB */
5777 GET_OPA4(rOBJ) # rOBJ <- A+
5778 GET_OPB(a3) # a3 <- B
5779 GET_VREG(a0, rOBJ) # a0 <- vA
5780 GET_VREG(a1, a3) # a1 <- vB
5781 .if 1
5782 # is second operand zero?
5783 beqz a1, common_errDivideByZero
5784 .endif
5785 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5786
5787 # optional op
5788 mod a0, a0, a1 # a0 <- op, a0-a3 changed
5789 GET_INST_OPCODE(t0) # extract opcode from rINST
5790 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5791 /* 10-13 instructions */
5792
5793#else
5794/* File: mips/binop2addr.S */
5795 /*
5796 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5797 * that specifies an instruction that performs "result = a0 op a1".
5798 * This could be an MIPS instruction or a function call.
5799 *
5800 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5801 * vCC (a1). Useful for integer division and modulus.
5802 *
5803 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5804 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5805 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5806 */
5807 /* binop/2addr vA, vB */
5808 GET_OPA4(rOBJ) # rOBJ <- A+
5809 GET_OPB(a3) # a3 <- B
5810 GET_VREG(a0, rOBJ) # a0 <- vA
5811 GET_VREG(a1, a3) # a1 <- vB
5812 .if 1
5813 # is second operand zero?
5814 beqz a1, common_errDivideByZero
5815 .endif
5816 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5817
5818 div zero, a0, a1 # optional op
5819 mfhi a0 # a0 <- op, a0-a3 changed
5820 GET_INST_OPCODE(t0) # extract opcode from rINST
5821 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5822 /* 10-13 instructions */
5823
5824#endif
5825
5826/* ------------------------------ */
5827 .balign 128
5828.L_op_and_int_2addr: /* 0xb5 */
5829/* File: mips/op_and_int_2addr.S */
5830/* File: mips/binop2addr.S */
5831 /*
5832 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5833 * that specifies an instruction that performs "result = a0 op a1".
5834 * This could be an MIPS instruction or a function call.
5835 *
5836 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5837 * vCC (a1). Useful for integer division and modulus.
5838 *
5839 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5840 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5841 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5842 */
5843 /* binop/2addr vA, vB */
5844 GET_OPA4(rOBJ) # rOBJ <- A+
5845 GET_OPB(a3) # a3 <- B
5846 GET_VREG(a0, rOBJ) # a0 <- vA
5847 GET_VREG(a1, a3) # a1 <- vB
5848 .if 0
5849 # is second operand zero?
5850 beqz a1, common_errDivideByZero
5851 .endif
5852 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5853
5854 # optional op
5855 and a0, a0, a1 # a0 <- op, a0-a3 changed
5856 GET_INST_OPCODE(t0) # extract opcode from rINST
5857 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5858 /* 10-13 instructions */
5859
5860
5861/* ------------------------------ */
5862 .balign 128
5863.L_op_or_int_2addr: /* 0xb6 */
5864/* File: mips/op_or_int_2addr.S */
5865/* File: mips/binop2addr.S */
5866 /*
5867 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5868 * that specifies an instruction that performs "result = a0 op a1".
5869 * This could be an MIPS instruction or a function call.
5870 *
5871 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5872 * vCC (a1). Useful for integer division and modulus.
5873 *
5874 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5875 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5876 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5877 */
5878 /* binop/2addr vA, vB */
5879 GET_OPA4(rOBJ) # rOBJ <- A+
5880 GET_OPB(a3) # a3 <- B
5881 GET_VREG(a0, rOBJ) # a0 <- vA
5882 GET_VREG(a1, a3) # a1 <- vB
5883 .if 0
5884 # is second operand zero?
5885 beqz a1, common_errDivideByZero
5886 .endif
5887 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5888
5889 # optional op
5890 or a0, a0, a1 # a0 <- op, a0-a3 changed
5891 GET_INST_OPCODE(t0) # extract opcode from rINST
5892 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5893 /* 10-13 instructions */
5894
5895
5896/* ------------------------------ */
5897 .balign 128
5898.L_op_xor_int_2addr: /* 0xb7 */
5899/* File: mips/op_xor_int_2addr.S */
5900/* File: mips/binop2addr.S */
5901 /*
5902 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5903 * that specifies an instruction that performs "result = a0 op a1".
5904 * This could be an MIPS instruction or a function call.
5905 *
5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5907 * vCC (a1). Useful for integer division and modulus.
5908 *
5909 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5910 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5911 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5912 */
5913 /* binop/2addr vA, vB */
5914 GET_OPA4(rOBJ) # rOBJ <- A+
5915 GET_OPB(a3) # a3 <- B
5916 GET_VREG(a0, rOBJ) # a0 <- vA
5917 GET_VREG(a1, a3) # a1 <- vB
5918 .if 0
5919 # is second operand zero?
5920 beqz a1, common_errDivideByZero
5921 .endif
5922 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5923
5924 # optional op
5925 xor a0, a0, a1 # a0 <- op, a0-a3 changed
5926 GET_INST_OPCODE(t0) # extract opcode from rINST
5927 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5928 /* 10-13 instructions */
5929
5930
5931/* ------------------------------ */
5932 .balign 128
5933.L_op_shl_int_2addr: /* 0xb8 */
5934/* File: mips/op_shl_int_2addr.S */
5935/* File: mips/binop2addr.S */
5936 /*
5937 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5938 * that specifies an instruction that performs "result = a0 op a1".
5939 * This could be an MIPS instruction or a function call.
5940 *
5941 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5942 * vCC (a1). Useful for integer division and modulus.
5943 *
5944 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5945 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5946 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5947 */
5948 /* binop/2addr vA, vB */
5949 GET_OPA4(rOBJ) # rOBJ <- A+
5950 GET_OPB(a3) # a3 <- B
5951 GET_VREG(a0, rOBJ) # a0 <- vA
5952 GET_VREG(a1, a3) # a1 <- vB
5953 .if 0
5954 # is second operand zero?
5955 beqz a1, common_errDivideByZero
5956 .endif
5957 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5958
5959 # optional op
5960 sll a0, a0, a1 # a0 <- op, a0-a3 changed
5961 GET_INST_OPCODE(t0) # extract opcode from rINST
5962 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5963 /* 10-13 instructions */
5964
5965
5966/* ------------------------------ */
5967 .balign 128
5968.L_op_shr_int_2addr: /* 0xb9 */
5969/* File: mips/op_shr_int_2addr.S */
5970/* File: mips/binop2addr.S */
5971 /*
5972 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5973 * that specifies an instruction that performs "result = a0 op a1".
5974 * This could be an MIPS instruction or a function call.
5975 *
5976 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5977 * vCC (a1). Useful for integer division and modulus.
5978 *
5979 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5980 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5981 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5982 */
5983 /* binop/2addr vA, vB */
5984 GET_OPA4(rOBJ) # rOBJ <- A+
5985 GET_OPB(a3) # a3 <- B
5986 GET_VREG(a0, rOBJ) # a0 <- vA
5987 GET_VREG(a1, a3) # a1 <- vB
5988 .if 0
5989 # is second operand zero?
5990 beqz a1, common_errDivideByZero
5991 .endif
5992 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
5993
5994 # optional op
5995 sra a0, a0, a1 # a0 <- op, a0-a3 changed
5996 GET_INST_OPCODE(t0) # extract opcode from rINST
5997 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
5998 /* 10-13 instructions */
5999
6000
6001/* ------------------------------ */
6002 .balign 128
6003.L_op_ushr_int_2addr: /* 0xba */
6004/* File: mips/op_ushr_int_2addr.S */
6005/* File: mips/binop2addr.S */
6006 /*
6007 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6008 * that specifies an instruction that performs "result = a0 op a1".
6009 * This could be an MIPS instruction or a function call.
6010 *
6011 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6012 * vCC (a1). Useful for integer division and modulus.
6013 *
6014 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6015 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6016 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
6017 */
6018 /* binop/2addr vA, vB */
6019 GET_OPA4(rOBJ) # rOBJ <- A+
6020 GET_OPB(a3) # a3 <- B
6021 GET_VREG(a0, rOBJ) # a0 <- vA
6022 GET_VREG(a1, a3) # a1 <- vB
6023 .if 0
6024 # is second operand zero?
6025 beqz a1, common_errDivideByZero
6026 .endif
6027 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6028
6029 # optional op
6030 srl a0, a0, a1 # a0 <- op, a0-a3 changed
6031 GET_INST_OPCODE(t0) # extract opcode from rINST
6032 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6033 /* 10-13 instructions */
6034
6035
6036/* ------------------------------ */
6037 .balign 128
6038.L_op_add_long_2addr: /* 0xbb */
6039/* File: mips/op_add_long_2addr.S */
6040/*
6041 * See op_add_long.S for details
6042 */
6043/* File: mips/binopWide2addr.S */
6044 /*
6045 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6046 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6047 * This could be a MIPS instruction or a function call. (If the result
6048 * comes back in a register other than a0, you can override "result".)
6049 *
6050 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6051 * vCC (a1). Useful for integer division and modulus.
6052 *
6053 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6054 * and-long/2addr, or-long/2addr, xor-long/2addr
6055 * rem-double/2addr
6056 */
6057 /* binop/2addr vA, vB */
6058 GET_OPA4(rOBJ) # rOBJ <- A+
6059 GET_OPB(a1) # a1 <- B
6060 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6061 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6062 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6063 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6064 .if 0
6065 or t0, a2, a3 # second arg (a2-a3) is zero?
6066 beqz t0, common_errDivideByZero
6067 .endif
6068 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6069
6070 addu v0, a2, a0 # optional op
6071 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed
6072 GET_INST_OPCODE(t0) # extract opcode from rINST
6073 SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1
6074 GOTO_OPCODE(t0) # jump to next instruction
6075 /* 12-15 instructions */
6076
6077
6078/* ------------------------------ */
6079 .balign 128
6080.L_op_sub_long_2addr: /* 0xbc */
6081/* File: mips/op_sub_long_2addr.S */
6082/*
6083 * See op_sub_long.S for more details
6084 */
6085/* File: mips/binopWide2addr.S */
6086 /*
6087 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6088 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6089 * This could be a MIPS instruction or a function call. (If the result
6090 * comes back in a register other than a0, you can override "result".)
6091 *
6092 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6093 * vCC (a1). Useful for integer division and modulus.
6094 *
6095 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6096 * and-long/2addr, or-long/2addr, xor-long/2addr
6097 * rem-double/2addr
6098 */
6099 /* binop/2addr vA, vB */
6100 GET_OPA4(rOBJ) # rOBJ <- A+
6101 GET_OPB(a1) # a1 <- B
6102 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6103 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6104 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6105 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6106 .if 0
6107 or t0, a2, a3 # second arg (a2-a3) is zero?
6108 beqz t0, common_errDivideByZero
6109 .endif
6110 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6111
6112 subu v0, a0, a2 # optional op
6113 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed
6114 GET_INST_OPCODE(t0) # extract opcode from rINST
6115 SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1
6116 GOTO_OPCODE(t0) # jump to next instruction
6117 /* 12-15 instructions */
6118
6119
6120/* ------------------------------ */
6121 .balign 128
6122.L_op_mul_long_2addr: /* 0xbd */
6123/* File: mips/op_mul_long_2addr.S */
6124 /*
6125 * See op_mul_long.S for more details
6126 */
6127 /* mul-long/2addr vA, vB */
6128 GET_OPA4(rOBJ) # rOBJ <- A+
6129
6130 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6131 LOAD64(a0, a1, t0) # vAA.low / high
6132
6133 GET_OPB(t1) # t1 <- B
6134 EAS2(t1, rFP, t1) # t1 <- &fp[B]
6135 LOAD64(a2, a3, t1) # vBB.low / high
6136
6137 mul v1, a3, a0 # v1= a3a0
6138#ifdef MIPS32REVGE6
6139 mulu v0, a2, a0 # v0= a2a0
6140 muhu t1, a2, a0
6141#else
6142 multu a2, a0
6143 mfhi t1
6144 mflo v0 # v0= a2a0
6145 #endif
6146 mul t2, a2, a1 # t2= a2a1
6147 addu v1, v1, t1 # v1= a3a0 + hi(a2a0)
6148 addu v1, v1, t2 # v1= v1 + a2a1;
6149
6150 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6151 GET_INST_OPCODE(t1) # extract opcode from rINST
6152 # vAA <- v0 (low)
6153 SET_VREG64(v0, v1, rOBJ) # vAA+1 <- v1 (high)
6154 GOTO_OPCODE(t1) # jump to next instruction
6155
6156/* ------------------------------ */
6157 .balign 128
6158.L_op_div_long_2addr: /* 0xbe */
6159/* File: mips/op_div_long_2addr.S */
6160/* File: mips/binopWide2addr.S */
6161 /*
6162 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6163 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6164 * This could be a MIPS instruction or a function call. (If the result
6165 * comes back in a register other than a0, you can override "result".)
6166 *
6167 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6168 * vCC (a1). Useful for integer division and modulus.
6169 *
6170 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6171 * and-long/2addr, or-long/2addr, xor-long/2addr
6172 * rem-double/2addr
6173 */
6174 /* binop/2addr vA, vB */
6175 GET_OPA4(rOBJ) # rOBJ <- A+
6176 GET_OPB(a1) # a1 <- B
6177 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6178 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6179 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6180 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6181 .if 1
6182 or t0, a2, a3 # second arg (a2-a3) is zero?
6183 beqz t0, common_errDivideByZero
6184 .endif
6185 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6186
6187 # optional op
6188 JAL(__divdi3) # result <- op, a0-a3 changed
6189 GET_INST_OPCODE(t0) # extract opcode from rINST
6190 SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1
6191 GOTO_OPCODE(t0) # jump to next instruction
6192 /* 12-15 instructions */
6193
6194
6195/* ------------------------------ */
6196 .balign 128
6197.L_op_rem_long_2addr: /* 0xbf */
6198/* File: mips/op_rem_long_2addr.S */
6199/* File: mips/binopWide2addr.S */
6200 /*
6201 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6202 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6203 * This could be a MIPS instruction or a function call. (If the result
6204 * comes back in a register other than a0, you can override "result".)
6205 *
6206 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6207 * vCC (a1). Useful for integer division and modulus.
6208 *
6209 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6210 * and-long/2addr, or-long/2addr, xor-long/2addr
6211 * rem-double/2addr
6212 */
6213 /* binop/2addr vA, vB */
6214 GET_OPA4(rOBJ) # rOBJ <- A+
6215 GET_OPB(a1) # a1 <- B
6216 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6217 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6218 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6219 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6220 .if 1
6221 or t0, a2, a3 # second arg (a2-a3) is zero?
6222 beqz t0, common_errDivideByZero
6223 .endif
6224 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6225
6226 # optional op
6227 JAL(__moddi3) # result <- op, a0-a3 changed
6228 GET_INST_OPCODE(t0) # extract opcode from rINST
6229 SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1
6230 GOTO_OPCODE(t0) # jump to next instruction
6231 /* 12-15 instructions */
6232
6233
6234/* ------------------------------ */
6235 .balign 128
6236.L_op_and_long_2addr: /* 0xc0 */
6237/* File: mips/op_and_long_2addr.S */
6238/* File: mips/binopWide2addr.S */
6239 /*
6240 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6241 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6242 * This could be a MIPS instruction or a function call. (If the result
6243 * comes back in a register other than a0, you can override "result".)
6244 *
6245 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6246 * vCC (a1). Useful for integer division and modulus.
6247 *
6248 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6249 * and-long/2addr, or-long/2addr, xor-long/2addr
6250 * rem-double/2addr
6251 */
6252 /* binop/2addr vA, vB */
6253 GET_OPA4(rOBJ) # rOBJ <- A+
6254 GET_OPB(a1) # a1 <- B
6255 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6256 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6257 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6258 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6259 .if 0
6260 or t0, a2, a3 # second arg (a2-a3) is zero?
6261 beqz t0, common_errDivideByZero
6262 .endif
6263 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6264
6265 and a0, a0, a2 # optional op
6266 and a1, a1, a3 # result <- op, a0-a3 changed
6267 GET_INST_OPCODE(t0) # extract opcode from rINST
6268 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6269 GOTO_OPCODE(t0) # jump to next instruction
6270 /* 12-15 instructions */
6271
6272
6273/* ------------------------------ */
6274 .balign 128
6275.L_op_or_long_2addr: /* 0xc1 */
6276/* File: mips/op_or_long_2addr.S */
6277/* File: mips/binopWide2addr.S */
6278 /*
6279 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6280 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6281 * This could be a MIPS instruction or a function call. (If the result
6282 * comes back in a register other than a0, you can override "result".)
6283 *
6284 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6285 * vCC (a1). Useful for integer division and modulus.
6286 *
6287 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6288 * and-long/2addr, or-long/2addr, xor-long/2addr
6289 * rem-double/2addr
6290 */
6291 /* binop/2addr vA, vB */
6292 GET_OPA4(rOBJ) # rOBJ <- A+
6293 GET_OPB(a1) # a1 <- B
6294 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6295 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6296 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6297 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6298 .if 0
6299 or t0, a2, a3 # second arg (a2-a3) is zero?
6300 beqz t0, common_errDivideByZero
6301 .endif
6302 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6303
6304 or a0, a0, a2 # optional op
6305 or a1, a1, a3 # result <- op, a0-a3 changed
6306 GET_INST_OPCODE(t0) # extract opcode from rINST
6307 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6308 GOTO_OPCODE(t0) # jump to next instruction
6309 /* 12-15 instructions */
6310
6311
6312/* ------------------------------ */
6313 .balign 128
6314.L_op_xor_long_2addr: /* 0xc2 */
6315/* File: mips/op_xor_long_2addr.S */
6316/* File: mips/binopWide2addr.S */
6317 /*
6318 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6319 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6320 * This could be a MIPS instruction or a function call. (If the result
6321 * comes back in a register other than a0, you can override "result".)
6322 *
6323 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6324 * vCC (a1). Useful for integer division and modulus.
6325 *
6326 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6327 * and-long/2addr, or-long/2addr, xor-long/2addr
6328 * rem-double/2addr
6329 */
6330 /* binop/2addr vA, vB */
6331 GET_OPA4(rOBJ) # rOBJ <- A+
6332 GET_OPB(a1) # a1 <- B
6333 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6334 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6335 LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1
6336 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6337 .if 0
6338 or t0, a2, a3 # second arg (a2-a3) is zero?
6339 beqz t0, common_errDivideByZero
6340 .endif
6341 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6342
6343 xor a0, a0, a2 # optional op
6344 xor a1, a1, a3 # result <- op, a0-a3 changed
6345 GET_INST_OPCODE(t0) # extract opcode from rINST
6346 SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1
6347 GOTO_OPCODE(t0) # jump to next instruction
6348 /* 12-15 instructions */
6349
6350
6351/* ------------------------------ */
6352 .balign 128
6353.L_op_shl_long_2addr: /* 0xc3 */
6354/* File: mips/op_shl_long_2addr.S */
6355 /*
6356 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6357 * 32-bit shift distance.
6358 */
6359 /* shl-long/2addr vA, vB */
6360 GET_OPA4(rOBJ) # rOBJ <- A+
6361 GET_OPB(a3) # a3 <- B
6362 GET_VREG(a2, a3) # a2 <- vB
6363 EAS2(t2, rFP, rOBJ) # t2 <- &fp[A]
6364 LOAD64(a0, a1, t2) # a0/a1 <- vAA/vAA+1
6365
6366 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6367 GET_INST_OPCODE(t0) # extract opcode from rINST
6368
6369 andi v1, a2, 0x20 # shift< shift & 0x20
6370 sll v0, a0, a2 # rlo<- alo << (shift&31)
6371 bnez v1, .Lop_shl_long_2addr_finish
6372 not v1, a2 # rhi<- 31-shift (shift is 5b)
6373 srl a0, 1
6374 srl a0, v1 # alo<- alo >> (32-(shift&31))
6375 sll v1, a1, a2 # rhi<- ahi << (shift&31)
6376 or v1, a0 # rhi<- rhi | alo
6377 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- a0/a1
6378
6379/* ------------------------------ */
6380 .balign 128
6381.L_op_shr_long_2addr: /* 0xc4 */
6382/* File: mips/op_shr_long_2addr.S */
6383 /*
6384 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6385 * 32-bit shift distance.
6386 */
6387 /* shr-long/2addr vA, vB */
6388 GET_OPA4(t2) # t2 <- A+
6389 GET_OPB(a3) # a3 <- B
6390 GET_VREG(a2, a3) # a2 <- vB
6391 EAS2(t0, rFP, t2) # t0 <- &fp[A]
6392 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6393 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6394 GET_INST_OPCODE(t0) # extract opcode from rINST
6395
6396 andi v0, a2, 0x20 # shift & 0x20
6397 sra v1, a1, a2 # rhi<- ahi >> (shift&31)
6398 bnez v0, .Lop_shr_long_2addr_finish
6399 srl v0, a0, a2 # rlo<- alo >> (shift&31)
6400 not a0, a2 # alo<- 31-shift (shift is 5b)
6401 sll a1, 1
6402 sll a1, a0 # ahi<- ahi << (32-(shift&31))
6403 or v0, a1 # rlo<- rlo | ahi
6404 SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1
6405
6406/* ------------------------------ */
6407 .balign 128
6408.L_op_ushr_long_2addr: /* 0xc5 */
6409/* File: mips/op_ushr_long_2addr.S */
6410 /*
6411 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6412 * 32-bit shift distance.
6413 */
6414 /* ushr-long/2addr vA, vB */
6415 GET_OPA4(t3) # t3 <- A+
6416 GET_OPB(a3) # a3 <- B
6417 GET_VREG(a2, a3) # a2 <- vB
6418 EAS2(t0, rFP, t3) # t0 <- &fp[A]
6419 LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1
6420
6421 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6422 GET_INST_OPCODE(t0) # extract opcode from rINST
6423
6424 andi v0, a2, 0x20 # shift & 0x20
6425 srl v1, a1, a2 # rhi<- ahi >> (shift&31)
6426 bnez v0, .Lop_ushr_long_2addr_finish
6427 srl v0, a0, a2 # rlo<- alo >> (shift&31)
6428 not a0, a2 # alo<- 31-n (shift is 5b)
6429 sll a1, 1
6430 sll a1, a0 # ahi<- ahi << (32-(shift&31))
6431 or v0, a1 # rlo<- rlo | ahi
6432 SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/vAA+1 <- a0/a1
6433
6434/* ------------------------------ */
6435 .balign 128
6436.L_op_add_float_2addr: /* 0xc6 */
6437/* File: mips/op_add_float_2addr.S */
6438/* File: mips/fbinop2addr.S */
6439 /*
6440 * Generic 32-bit "/2addr" binary operation. Provide an "instr"
6441 * that specifies an instruction that performs "result = a0 op a1".
6442 * This could be an MIPS instruction or a function call.
6443 *
6444 * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
6445 * div-float/2addr, rem-float/2addr
6446 */
6447 /* binop/2addr vA, vB */
6448 GET_OPA4(rOBJ) # t1 <- A+
6449 GET_OPB(a3) # a3 <- B
6450 GET_VREG_F(fa0, rOBJ)
6451 GET_VREG_F(fa1, a3)
6452 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6453
6454 add.s fv0, fa0, fa1
6455 SET_VREG_F(fv0, rOBJ) # vAA <- result
6456 GET_INST_OPCODE(t0) # extract opcode from rINST
6457 GOTO_OPCODE(t0) # jump to next instruction
6458
6459
6460/* ------------------------------ */
6461 .balign 128
6462.L_op_sub_float_2addr: /* 0xc7 */
6463/* File: mips/op_sub_float_2addr.S */
6464/* File: mips/fbinop2addr.S */
6465 /*
6466 * Generic 32-bit "/2addr" binary operation. Provide an "instr"
6467 * that specifies an instruction that performs "result = a0 op a1".
6468 * This could be an MIPS instruction or a function call.
6469 *
6470 * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
6471 * div-float/2addr, rem-float/2addr
6472 */
6473 /* binop/2addr vA, vB */
6474 GET_OPA4(rOBJ) # t1 <- A+
6475 GET_OPB(a3) # a3 <- B
6476 GET_VREG_F(fa0, rOBJ)
6477 GET_VREG_F(fa1, a3)
6478 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6479
6480 sub.s fv0, fa0, fa1
6481 SET_VREG_F(fv0, rOBJ) # vAA <- result
6482 GET_INST_OPCODE(t0) # extract opcode from rINST
6483 GOTO_OPCODE(t0) # jump to next instruction
6484
6485
6486/* ------------------------------ */
6487 .balign 128
6488.L_op_mul_float_2addr: /* 0xc8 */
6489/* File: mips/op_mul_float_2addr.S */
6490/* File: mips/fbinop2addr.S */
6491 /*
6492 * Generic 32-bit "/2addr" binary operation. Provide an "instr"
6493 * that specifies an instruction that performs "result = a0 op a1".
6494 * This could be an MIPS instruction or a function call.
6495 *
6496 * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
6497 * div-float/2addr, rem-float/2addr
6498 */
6499 /* binop/2addr vA, vB */
6500 GET_OPA4(rOBJ) # t1 <- A+
6501 GET_OPB(a3) # a3 <- B
6502 GET_VREG_F(fa0, rOBJ)
6503 GET_VREG_F(fa1, a3)
6504 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6505
6506 mul.s fv0, fa0, fa1
6507 SET_VREG_F(fv0, rOBJ) # vAA <- result
6508 GET_INST_OPCODE(t0) # extract opcode from rINST
6509 GOTO_OPCODE(t0) # jump to next instruction
6510
6511
6512/* ------------------------------ */
6513 .balign 128
6514.L_op_div_float_2addr: /* 0xc9 */
6515/* File: mips/op_div_float_2addr.S */
6516/* File: mips/fbinop2addr.S */
6517 /*
6518 * Generic 32-bit "/2addr" binary operation. Provide an "instr"
6519 * that specifies an instruction that performs "result = a0 op a1".
6520 * This could be an MIPS instruction or a function call.
6521 *
6522 * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
6523 * div-float/2addr, rem-float/2addr
6524 */
6525 /* binop/2addr vA, vB */
6526 GET_OPA4(rOBJ) # t1 <- A+
6527 GET_OPB(a3) # a3 <- B
6528 GET_VREG_F(fa0, rOBJ)
6529 GET_VREG_F(fa1, a3)
6530 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6531
6532 div.s fv0, fa0, fa1
6533 SET_VREG_F(fv0, rOBJ) # vAA <- result
6534 GET_INST_OPCODE(t0) # extract opcode from rINST
6535 GOTO_OPCODE(t0) # jump to next instruction
6536
6537
6538/* ------------------------------ */
6539 .balign 128
6540.L_op_rem_float_2addr: /* 0xca */
6541/* File: mips/op_rem_float_2addr.S */
6542/* File: mips/fbinop2addr.S */
6543 /*
6544 * Generic 32-bit "/2addr" binary operation. Provide an "instr"
6545 * that specifies an instruction that performs "result = a0 op a1".
6546 * This could be an MIPS instruction or a function call.
6547 *
6548 * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
6549 * div-float/2addr, rem-float/2addr
6550 */
6551 /* binop/2addr vA, vB */
6552 GET_OPA4(rOBJ) # t1 <- A+
6553 GET_OPB(a3) # a3 <- B
6554 GET_VREG_F(fa0, rOBJ)
6555 GET_VREG_F(fa1, a3)
6556 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6557
6558 JAL(fmodf)
6559 SET_VREG_F(fv0, rOBJ) # vAA <- result
6560 GET_INST_OPCODE(t0) # extract opcode from rINST
6561 GOTO_OPCODE(t0) # jump to next instruction
6562
6563
6564/* ------------------------------ */
6565 .balign 128
6566.L_op_add_double_2addr: /* 0xcb */
6567/* File: mips/op_add_double_2addr.S */
6568/* File: mips/fbinopWide2addr.S */
6569 /*
6570 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6571 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6572 * This could be an MIPS instruction or a function call.
6573 *
6574 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6575 * div-double/2addr, rem-double/2addr
6576 */
6577 /* binop/2addr vA, vB */
6578 GET_OPA4(rOBJ) # rOBJ <- A+
6579 GET_OPB(a1) # a1 <- B
6580 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6581 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6582 LOAD64_F(fa0, fa0f, t0)
6583 LOAD64_F(fa1, fa1f, a1)
6584
6585 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6586 add.d fv0, fa0, fa1
6587 SET_VREG64_F(fv0, fv0f, rOBJ)
6588 GET_INST_OPCODE(t0) # extract opcode from rINST
6589 GOTO_OPCODE(t0) # jump to next instruction
6590
6591
6592/* ------------------------------ */
6593 .balign 128
6594.L_op_sub_double_2addr: /* 0xcc */
6595/* File: mips/op_sub_double_2addr.S */
6596/* File: mips/fbinopWide2addr.S */
6597 /*
6598 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6599 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6600 * This could be an MIPS instruction or a function call.
6601 *
6602 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6603 * div-double/2addr, rem-double/2addr
6604 */
6605 /* binop/2addr vA, vB */
6606 GET_OPA4(rOBJ) # rOBJ <- A+
6607 GET_OPB(a1) # a1 <- B
6608 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6609 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6610 LOAD64_F(fa0, fa0f, t0)
6611 LOAD64_F(fa1, fa1f, a1)
6612
6613 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6614 sub.d fv0, fa0, fa1
6615 SET_VREG64_F(fv0, fv0f, rOBJ)
6616 GET_INST_OPCODE(t0) # extract opcode from rINST
6617 GOTO_OPCODE(t0) # jump to next instruction
6618
6619
6620/* ------------------------------ */
6621 .balign 128
6622.L_op_mul_double_2addr: /* 0xcd */
6623/* File: mips/op_mul_double_2addr.S */
6624/* File: mips/fbinopWide2addr.S */
6625 /*
6626 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6627 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6628 * This could be an MIPS instruction or a function call.
6629 *
6630 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6631 * div-double/2addr, rem-double/2addr
6632 */
6633 /* binop/2addr vA, vB */
6634 GET_OPA4(rOBJ) # rOBJ <- A+
6635 GET_OPB(a1) # a1 <- B
6636 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6637 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6638 LOAD64_F(fa0, fa0f, t0)
6639 LOAD64_F(fa1, fa1f, a1)
6640
6641 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6642 mul.d fv0, fa0, fa1
6643 SET_VREG64_F(fv0, fv0f, rOBJ)
6644 GET_INST_OPCODE(t0) # extract opcode from rINST
6645 GOTO_OPCODE(t0) # jump to next instruction
6646
6647
6648/* ------------------------------ */
6649 .balign 128
6650.L_op_div_double_2addr: /* 0xce */
6651/* File: mips/op_div_double_2addr.S */
6652/* File: mips/fbinopWide2addr.S */
6653 /*
6654 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6655 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6656 * This could be an MIPS instruction or a function call.
6657 *
6658 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6659 * div-double/2addr, rem-double/2addr
6660 */
6661 /* binop/2addr vA, vB */
6662 GET_OPA4(rOBJ) # rOBJ <- A+
6663 GET_OPB(a1) # a1 <- B
6664 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6665 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6666 LOAD64_F(fa0, fa0f, t0)
6667 LOAD64_F(fa1, fa1f, a1)
6668
6669 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6670 div.d fv0, fa0, fa1
6671 SET_VREG64_F(fv0, fv0f, rOBJ)
6672 GET_INST_OPCODE(t0) # extract opcode from rINST
6673 GOTO_OPCODE(t0) # jump to next instruction
6674
6675
6676/* ------------------------------ */
6677 .balign 128
6678.L_op_rem_double_2addr: /* 0xcf */
6679/* File: mips/op_rem_double_2addr.S */
6680/* File: mips/fbinopWide2addr.S */
6681 /*
6682 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6683 * that specifies an instruction that performs "result = a0-a1 op a2-a3".
6684 * This could be an MIPS instruction or a function call.
6685 *
6686 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6687 * div-double/2addr, rem-double/2addr
6688 */
6689 /* binop/2addr vA, vB */
6690 GET_OPA4(rOBJ) # rOBJ <- A+
6691 GET_OPB(a1) # a1 <- B
6692 EAS2(a1, rFP, a1) # a1 <- &fp[B]
6693 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A]
6694 LOAD64_F(fa0, fa0f, t0)
6695 LOAD64_F(fa1, fa1f, a1)
6696
6697 FETCH_ADVANCE_INST(1) # advance rPC, load rINST
6698 JAL(fmod)
6699 SET_VREG64_F(fv0, fv0f, rOBJ)
6700 GET_INST_OPCODE(t0) # extract opcode from rINST
6701 GOTO_OPCODE(t0) # jump to next instruction
6702
6703
6704/* ------------------------------ */
6705 .balign 128
6706.L_op_add_int_lit16: /* 0xd0 */
6707/* File: mips/op_add_int_lit16.S */
6708/* File: mips/binopLit16.S */
6709 /*
6710 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6711 * that specifies an instruction that performs "result = a0 op a1".
6712 * This could be an MIPS instruction or a function call. (If the result
6713 * comes back in a register other than a0, you can override "result".)
6714 *
6715 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6716 * vCC (a1). Useful for integer division and modulus.
6717 *
6718 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6719 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6720 */
6721 # binop/lit16 vA, vB, /* +CCCC */
6722 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6723 GET_OPB(a2) # a2 <- B
6724 GET_OPA(rOBJ) # rOBJ <- A+
6725 GET_VREG(a0, a2) # a0 <- vB
6726 and rOBJ, rOBJ, 15
6727 .if 0
6728 # cmp a1, 0; is second operand zero?
6729 beqz a1, common_errDivideByZero
6730 .endif
6731 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6732
6733 # optional op
6734 addu a0, a0, a1 # a0 <- op, a0-a3 changed
6735 GET_INST_OPCODE(t0) # extract opcode from rINST
6736 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6737 /* 10-13 instructions */
6738
6739
6740/* ------------------------------ */
6741 .balign 128
6742.L_op_rsub_int: /* 0xd1 */
6743/* File: mips/op_rsub_int.S */
6744/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6745/* File: mips/binopLit16.S */
6746 /*
6747 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6748 * that specifies an instruction that performs "result = a0 op a1".
6749 * This could be an MIPS instruction or a function call. (If the result
6750 * comes back in a register other than a0, you can override "result".)
6751 *
6752 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6753 * vCC (a1). Useful for integer division and modulus.
6754 *
6755 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6756 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6757 */
6758 # binop/lit16 vA, vB, /* +CCCC */
6759 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6760 GET_OPB(a2) # a2 <- B
6761 GET_OPA(rOBJ) # rOBJ <- A+
6762 GET_VREG(a0, a2) # a0 <- vB
6763 and rOBJ, rOBJ, 15
6764 .if 0
6765 # cmp a1, 0; is second operand zero?
6766 beqz a1, common_errDivideByZero
6767 .endif
6768 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6769
6770 # optional op
6771 subu a0, a1, a0 # a0 <- op, a0-a3 changed
6772 GET_INST_OPCODE(t0) # extract opcode from rINST
6773 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6774 /* 10-13 instructions */
6775
6776
6777/* ------------------------------ */
6778 .balign 128
6779.L_op_mul_int_lit16: /* 0xd2 */
6780/* File: mips/op_mul_int_lit16.S */
6781/* File: mips/binopLit16.S */
6782 /*
6783 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6784 * that specifies an instruction that performs "result = a0 op a1".
6785 * This could be an MIPS instruction or a function call. (If the result
6786 * comes back in a register other than a0, you can override "result".)
6787 *
6788 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6789 * vCC (a1). Useful for integer division and modulus.
6790 *
6791 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6792 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6793 */
6794 # binop/lit16 vA, vB, /* +CCCC */
6795 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6796 GET_OPB(a2) # a2 <- B
6797 GET_OPA(rOBJ) # rOBJ <- A+
6798 GET_VREG(a0, a2) # a0 <- vB
6799 and rOBJ, rOBJ, 15
6800 .if 0
6801 # cmp a1, 0; is second operand zero?
6802 beqz a1, common_errDivideByZero
6803 .endif
6804 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6805
6806 # optional op
6807 mul a0, a0, a1 # a0 <- op, a0-a3 changed
6808 GET_INST_OPCODE(t0) # extract opcode from rINST
6809 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6810 /* 10-13 instructions */
6811
6812
6813/* ------------------------------ */
6814 .balign 128
6815.L_op_div_int_lit16: /* 0xd3 */
6816/* File: mips/op_div_int_lit16.S */
6817#ifdef MIPS32REVGE6
6818/* File: mips/binopLit16.S */
6819 /*
6820 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6821 * that specifies an instruction that performs "result = a0 op a1".
6822 * This could be an MIPS instruction or a function call. (If the result
6823 * comes back in a register other than a0, you can override "result".)
6824 *
6825 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6826 * vCC (a1). Useful for integer division and modulus.
6827 *
6828 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6829 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6830 */
6831 # binop/lit16 vA, vB, /* +CCCC */
6832 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6833 GET_OPB(a2) # a2 <- B
6834 GET_OPA(rOBJ) # rOBJ <- A+
6835 GET_VREG(a0, a2) # a0 <- vB
6836 and rOBJ, rOBJ, 15
6837 .if 1
6838 # cmp a1, 0; is second operand zero?
6839 beqz a1, common_errDivideByZero
6840 .endif
6841 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6842
6843 # optional op
6844 div a0, a0, a1 # a0 <- op, a0-a3 changed
6845 GET_INST_OPCODE(t0) # extract opcode from rINST
6846 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6847 /* 10-13 instructions */
6848
6849#else
6850/* File: mips/binopLit16.S */
6851 /*
6852 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6853 * that specifies an instruction that performs "result = a0 op a1".
6854 * This could be an MIPS instruction or a function call. (If the result
6855 * comes back in a register other than a0, you can override "result".)
6856 *
6857 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6858 * vCC (a1). Useful for integer division and modulus.
6859 *
6860 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6861 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6862 */
6863 # binop/lit16 vA, vB, /* +CCCC */
6864 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6865 GET_OPB(a2) # a2 <- B
6866 GET_OPA(rOBJ) # rOBJ <- A+
6867 GET_VREG(a0, a2) # a0 <- vB
6868 and rOBJ, rOBJ, 15
6869 .if 1
6870 # cmp a1, 0; is second operand zero?
6871 beqz a1, common_errDivideByZero
6872 .endif
6873 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6874
6875 div zero, a0, a1 # optional op
6876 mflo a0 # a0 <- op, a0-a3 changed
6877 GET_INST_OPCODE(t0) # extract opcode from rINST
6878 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6879 /* 10-13 instructions */
6880
6881#endif
6882
6883/* ------------------------------ */
6884 .balign 128
6885.L_op_rem_int_lit16: /* 0xd4 */
6886/* File: mips/op_rem_int_lit16.S */
6887#ifdef MIPS32REVGE6
6888/* File: mips/binopLit16.S */
6889 /*
6890 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6891 * that specifies an instruction that performs "result = a0 op a1".
6892 * This could be an MIPS instruction or a function call. (If the result
6893 * comes back in a register other than a0, you can override "result".)
6894 *
6895 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6896 * vCC (a1). Useful for integer division and modulus.
6897 *
6898 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6899 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6900 */
6901 # binop/lit16 vA, vB, /* +CCCC */
6902 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6903 GET_OPB(a2) # a2 <- B
6904 GET_OPA(rOBJ) # rOBJ <- A+
6905 GET_VREG(a0, a2) # a0 <- vB
6906 and rOBJ, rOBJ, 15
6907 .if 1
6908 # cmp a1, 0; is second operand zero?
6909 beqz a1, common_errDivideByZero
6910 .endif
6911 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6912
6913 # optional op
6914 mod a0, a0, a1 # a0 <- op, a0-a3 changed
6915 GET_INST_OPCODE(t0) # extract opcode from rINST
6916 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6917 /* 10-13 instructions */
6918
6919#else
6920/* File: mips/binopLit16.S */
6921 /*
6922 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6923 * that specifies an instruction that performs "result = a0 op a1".
6924 * This could be an MIPS instruction or a function call. (If the result
6925 * comes back in a register other than a0, you can override "result".)
6926 *
6927 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6928 * vCC (a1). Useful for integer division and modulus.
6929 *
6930 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6931 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6932 */
6933 # binop/lit16 vA, vB, /* +CCCC */
6934 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6935 GET_OPB(a2) # a2 <- B
6936 GET_OPA(rOBJ) # rOBJ <- A+
6937 GET_VREG(a0, a2) # a0 <- vB
6938 and rOBJ, rOBJ, 15
6939 .if 1
6940 # cmp a1, 0; is second operand zero?
6941 beqz a1, common_errDivideByZero
6942 .endif
6943 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6944
6945 div zero, a0, a1 # optional op
6946 mfhi a0 # a0 <- op, a0-a3 changed
6947 GET_INST_OPCODE(t0) # extract opcode from rINST
6948 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6949 /* 10-13 instructions */
6950
6951#endif
6952
6953/* ------------------------------ */
6954 .balign 128
6955.L_op_and_int_lit16: /* 0xd5 */
6956/* File: mips/op_and_int_lit16.S */
6957/* File: mips/binopLit16.S */
6958 /*
6959 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6960 * that specifies an instruction that performs "result = a0 op a1".
6961 * This could be an MIPS instruction or a function call. (If the result
6962 * comes back in a register other than a0, you can override "result".)
6963 *
6964 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6965 * vCC (a1). Useful for integer division and modulus.
6966 *
6967 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6968 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6969 */
6970 # binop/lit16 vA, vB, /* +CCCC */
6971 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
6972 GET_OPB(a2) # a2 <- B
6973 GET_OPA(rOBJ) # rOBJ <- A+
6974 GET_VREG(a0, a2) # a0 <- vB
6975 and rOBJ, rOBJ, 15
6976 .if 0
6977 # cmp a1, 0; is second operand zero?
6978 beqz a1, common_errDivideByZero
6979 .endif
6980 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
6981
6982 # optional op
6983 and a0, a0, a1 # a0 <- op, a0-a3 changed
6984 GET_INST_OPCODE(t0) # extract opcode from rINST
6985 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
6986 /* 10-13 instructions */
6987
6988
6989/* ------------------------------ */
6990 .balign 128
6991.L_op_or_int_lit16: /* 0xd6 */
6992/* File: mips/op_or_int_lit16.S */
6993/* File: mips/binopLit16.S */
6994 /*
6995 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6996 * that specifies an instruction that performs "result = a0 op a1".
6997 * This could be an MIPS instruction or a function call. (If the result
6998 * comes back in a register other than a0, you can override "result".)
6999 *
7000 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7001 * vCC (a1). Useful for integer division and modulus.
7002 *
7003 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
7004 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
7005 */
7006 # binop/lit16 vA, vB, /* +CCCC */
7007 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
7008 GET_OPB(a2) # a2 <- B
7009 GET_OPA(rOBJ) # rOBJ <- A+
7010 GET_VREG(a0, a2) # a0 <- vB
7011 and rOBJ, rOBJ, 15
7012 .if 0
7013 # cmp a1, 0; is second operand zero?
7014 beqz a1, common_errDivideByZero
7015 .endif
7016 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7017
7018 # optional op
7019 or a0, a0, a1 # a0 <- op, a0-a3 changed
7020 GET_INST_OPCODE(t0) # extract opcode from rINST
7021 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7022 /* 10-13 instructions */
7023
7024
7025/* ------------------------------ */
7026 .balign 128
7027.L_op_xor_int_lit16: /* 0xd7 */
7028/* File: mips/op_xor_int_lit16.S */
7029/* File: mips/binopLit16.S */
7030 /*
7031 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
7032 * that specifies an instruction that performs "result = a0 op a1".
7033 * This could be an MIPS instruction or a function call. (If the result
7034 * comes back in a register other than a0, you can override "result".)
7035 *
7036 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7037 * vCC (a1). Useful for integer division and modulus.
7038 *
7039 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
7040 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
7041 */
7042 # binop/lit16 vA, vB, /* +CCCC */
7043 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended)
7044 GET_OPB(a2) # a2 <- B
7045 GET_OPA(rOBJ) # rOBJ <- A+
7046 GET_VREG(a0, a2) # a0 <- vB
7047 and rOBJ, rOBJ, 15
7048 .if 0
7049 # cmp a1, 0; is second operand zero?
7050 beqz a1, common_errDivideByZero
7051 .endif
7052 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7053
7054 # optional op
7055 xor a0, a0, a1 # a0 <- op, a0-a3 changed
7056 GET_INST_OPCODE(t0) # extract opcode from rINST
7057 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7058 /* 10-13 instructions */
7059
7060
7061/* ------------------------------ */
7062 .balign 128
7063.L_op_add_int_lit8: /* 0xd8 */
7064/* File: mips/op_add_int_lit8.S */
7065/* File: mips/binopLit8.S */
7066 /*
7067 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7068 * that specifies an instruction that performs "result = a0 op a1".
7069 * This could be an MIPS instruction or a function call. (If the result
7070 * comes back in a register other than a0, you can override "result".)
7071 *
7072 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7073 * vCC (a1). Useful for integer division and modulus.
7074 *
7075 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7076 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7077 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7078 */
7079 # binop/lit8 vAA, vBB, /* +CC */
7080 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7081 GET_OPA(rOBJ) # rOBJ <- AA
7082 and a2, a3, 255 # a2 <- BB
7083 GET_VREG(a0, a2) # a0 <- vBB
7084 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7085 .if 0
7086 # is second operand zero?
7087 beqz a1, common_errDivideByZero
7088 .endif
7089 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7090
7091 # optional op
7092 addu a0, a0, a1 # a0 <- op, a0-a3 changed
7093 GET_INST_OPCODE(t0) # extract opcode from rINST
7094 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7095 /* 10-12 instructions */
7096
7097
7098/* ------------------------------ */
7099 .balign 128
7100.L_op_rsub_int_lit8: /* 0xd9 */
7101/* File: mips/op_rsub_int_lit8.S */
7102/* File: mips/binopLit8.S */
7103 /*
7104 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7105 * that specifies an instruction that performs "result = a0 op a1".
7106 * This could be an MIPS instruction or a function call. (If the result
7107 * comes back in a register other than a0, you can override "result".)
7108 *
7109 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7110 * vCC (a1). Useful for integer division and modulus.
7111 *
7112 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7113 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7114 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7115 */
7116 # binop/lit8 vAA, vBB, /* +CC */
7117 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7118 GET_OPA(rOBJ) # rOBJ <- AA
7119 and a2, a3, 255 # a2 <- BB
7120 GET_VREG(a0, a2) # a0 <- vBB
7121 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7122 .if 0
7123 # is second operand zero?
7124 beqz a1, common_errDivideByZero
7125 .endif
7126 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7127
7128 # optional op
7129 subu a0, a1, a0 # a0 <- op, a0-a3 changed
7130 GET_INST_OPCODE(t0) # extract opcode from rINST
7131 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7132 /* 10-12 instructions */
7133
7134
7135/* ------------------------------ */
7136 .balign 128
7137.L_op_mul_int_lit8: /* 0xda */
7138/* File: mips/op_mul_int_lit8.S */
7139/* File: mips/binopLit8.S */
7140 /*
7141 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7142 * that specifies an instruction that performs "result = a0 op a1".
7143 * This could be an MIPS instruction or a function call. (If the result
7144 * comes back in a register other than a0, you can override "result".)
7145 *
7146 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7147 * vCC (a1). Useful for integer division and modulus.
7148 *
7149 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7150 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7151 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7152 */
7153 # binop/lit8 vAA, vBB, /* +CC */
7154 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7155 GET_OPA(rOBJ) # rOBJ <- AA
7156 and a2, a3, 255 # a2 <- BB
7157 GET_VREG(a0, a2) # a0 <- vBB
7158 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7159 .if 0
7160 # is second operand zero?
7161 beqz a1, common_errDivideByZero
7162 .endif
7163 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7164
7165 # optional op
7166 mul a0, a0, a1 # a0 <- op, a0-a3 changed
7167 GET_INST_OPCODE(t0) # extract opcode from rINST
7168 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7169 /* 10-12 instructions */
7170
7171
7172/* ------------------------------ */
7173 .balign 128
7174.L_op_div_int_lit8: /* 0xdb */
7175/* File: mips/op_div_int_lit8.S */
7176#ifdef MIPS32REVGE6
7177/* File: mips/binopLit8.S */
7178 /*
7179 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7180 * that specifies an instruction that performs "result = a0 op a1".
7181 * This could be an MIPS instruction or a function call. (If the result
7182 * comes back in a register other than a0, you can override "result".)
7183 *
7184 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7185 * vCC (a1). Useful for integer division and modulus.
7186 *
7187 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7188 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7189 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7190 */
7191 # binop/lit8 vAA, vBB, /* +CC */
7192 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7193 GET_OPA(rOBJ) # rOBJ <- AA
7194 and a2, a3, 255 # a2 <- BB
7195 GET_VREG(a0, a2) # a0 <- vBB
7196 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7197 .if 1
7198 # is second operand zero?
7199 beqz a1, common_errDivideByZero
7200 .endif
7201 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7202
7203 # optional op
7204 div a0, a0, a1 # a0 <- op, a0-a3 changed
7205 GET_INST_OPCODE(t0) # extract opcode from rINST
7206 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7207 /* 10-12 instructions */
7208
7209#else
7210/* File: mips/binopLit8.S */
7211 /*
7212 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7213 * that specifies an instruction that performs "result = a0 op a1".
7214 * This could be an MIPS instruction or a function call. (If the result
7215 * comes back in a register other than a0, you can override "result".)
7216 *
7217 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7218 * vCC (a1). Useful for integer division and modulus.
7219 *
7220 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7221 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7222 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7223 */
7224 # binop/lit8 vAA, vBB, /* +CC */
7225 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7226 GET_OPA(rOBJ) # rOBJ <- AA
7227 and a2, a3, 255 # a2 <- BB
7228 GET_VREG(a0, a2) # a0 <- vBB
7229 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7230 .if 1
7231 # is second operand zero?
7232 beqz a1, common_errDivideByZero
7233 .endif
7234 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7235
7236 div zero, a0, a1 # optional op
7237 mflo a0 # a0 <- op, a0-a3 changed
7238 GET_INST_OPCODE(t0) # extract opcode from rINST
7239 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7240 /* 10-12 instructions */
7241
7242#endif
7243
7244/* ------------------------------ */
7245 .balign 128
7246.L_op_rem_int_lit8: /* 0xdc */
7247/* File: mips/op_rem_int_lit8.S */
7248#ifdef MIPS32REVGE6
7249/* File: mips/binopLit8.S */
7250 /*
7251 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7252 * that specifies an instruction that performs "result = a0 op a1".
7253 * This could be an MIPS instruction or a function call. (If the result
7254 * comes back in a register other than a0, you can override "result".)
7255 *
7256 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7257 * vCC (a1). Useful for integer division and modulus.
7258 *
7259 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7260 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7261 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7262 */
7263 # binop/lit8 vAA, vBB, /* +CC */
7264 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7265 GET_OPA(rOBJ) # rOBJ <- AA
7266 and a2, a3, 255 # a2 <- BB
7267 GET_VREG(a0, a2) # a0 <- vBB
7268 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7269 .if 1
7270 # is second operand zero?
7271 beqz a1, common_errDivideByZero
7272 .endif
7273 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7274
7275 # optional op
7276 mod a0, a0, a1 # a0 <- op, a0-a3 changed
7277 GET_INST_OPCODE(t0) # extract opcode from rINST
7278 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7279 /* 10-12 instructions */
7280
7281#else
7282/* File: mips/binopLit8.S */
7283 /*
7284 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7285 * that specifies an instruction that performs "result = a0 op a1".
7286 * This could be an MIPS instruction or a function call. (If the result
7287 * comes back in a register other than a0, you can override "result".)
7288 *
7289 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7290 * vCC (a1). Useful for integer division and modulus.
7291 *
7292 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7293 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7294 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7295 */
7296 # binop/lit8 vAA, vBB, /* +CC */
7297 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7298 GET_OPA(rOBJ) # rOBJ <- AA
7299 and a2, a3, 255 # a2 <- BB
7300 GET_VREG(a0, a2) # a0 <- vBB
7301 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7302 .if 1
7303 # is second operand zero?
7304 beqz a1, common_errDivideByZero
7305 .endif
7306 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7307
7308 div zero, a0, a1 # optional op
7309 mfhi a0 # a0 <- op, a0-a3 changed
7310 GET_INST_OPCODE(t0) # extract opcode from rINST
7311 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7312 /* 10-12 instructions */
7313
7314#endif
7315
7316/* ------------------------------ */
7317 .balign 128
7318.L_op_and_int_lit8: /* 0xdd */
7319/* File: mips/op_and_int_lit8.S */
7320/* File: mips/binopLit8.S */
7321 /*
7322 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7323 * that specifies an instruction that performs "result = a0 op a1".
7324 * This could be an MIPS instruction or a function call. (If the result
7325 * comes back in a register other than a0, you can override "result".)
7326 *
7327 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7328 * vCC (a1). Useful for integer division and modulus.
7329 *
7330 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7331 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7332 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7333 */
7334 # binop/lit8 vAA, vBB, /* +CC */
7335 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7336 GET_OPA(rOBJ) # rOBJ <- AA
7337 and a2, a3, 255 # a2 <- BB
7338 GET_VREG(a0, a2) # a0 <- vBB
7339 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7340 .if 0
7341 # is second operand zero?
7342 beqz a1, common_errDivideByZero
7343 .endif
7344 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7345
7346 # optional op
7347 and a0, a0, a1 # a0 <- op, a0-a3 changed
7348 GET_INST_OPCODE(t0) # extract opcode from rINST
7349 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7350 /* 10-12 instructions */
7351
7352
7353/* ------------------------------ */
7354 .balign 128
7355.L_op_or_int_lit8: /* 0xde */
7356/* File: mips/op_or_int_lit8.S */
7357/* File: mips/binopLit8.S */
7358 /*
7359 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7360 * that specifies an instruction that performs "result = a0 op a1".
7361 * This could be an MIPS instruction or a function call. (If the result
7362 * comes back in a register other than a0, you can override "result".)
7363 *
7364 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7365 * vCC (a1). Useful for integer division and modulus.
7366 *
7367 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7368 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7369 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7370 */
7371 # binop/lit8 vAA, vBB, /* +CC */
7372 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7373 GET_OPA(rOBJ) # rOBJ <- AA
7374 and a2, a3, 255 # a2 <- BB
7375 GET_VREG(a0, a2) # a0 <- vBB
7376 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7377 .if 0
7378 # is second operand zero?
7379 beqz a1, common_errDivideByZero
7380 .endif
7381 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7382
7383 # optional op
7384 or a0, a0, a1 # a0 <- op, a0-a3 changed
7385 GET_INST_OPCODE(t0) # extract opcode from rINST
7386 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7387 /* 10-12 instructions */
7388
7389
7390/* ------------------------------ */
7391 .balign 128
7392.L_op_xor_int_lit8: /* 0xdf */
7393/* File: mips/op_xor_int_lit8.S */
7394/* File: mips/binopLit8.S */
7395 /*
7396 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7397 * that specifies an instruction that performs "result = a0 op a1".
7398 * This could be an MIPS instruction or a function call. (If the result
7399 * comes back in a register other than a0, you can override "result".)
7400 *
7401 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7402 * vCC (a1). Useful for integer division and modulus.
7403 *
7404 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7405 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7406 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7407 */
7408 # binop/lit8 vAA, vBB, /* +CC */
7409 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7410 GET_OPA(rOBJ) # rOBJ <- AA
7411 and a2, a3, 255 # a2 <- BB
7412 GET_VREG(a0, a2) # a0 <- vBB
7413 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7414 .if 0
7415 # is second operand zero?
7416 beqz a1, common_errDivideByZero
7417 .endif
7418 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7419
7420 # optional op
7421 xor a0, a0, a1 # a0 <- op, a0-a3 changed
7422 GET_INST_OPCODE(t0) # extract opcode from rINST
7423 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7424 /* 10-12 instructions */
7425
7426
7427/* ------------------------------ */
7428 .balign 128
7429.L_op_shl_int_lit8: /* 0xe0 */
7430/* File: mips/op_shl_int_lit8.S */
7431/* File: mips/binopLit8.S */
7432 /*
7433 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7434 * that specifies an instruction that performs "result = a0 op a1".
7435 * This could be an MIPS instruction or a function call. (If the result
7436 * comes back in a register other than a0, you can override "result".)
7437 *
7438 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7439 * vCC (a1). Useful for integer division and modulus.
7440 *
7441 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7442 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7443 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7444 */
7445 # binop/lit8 vAA, vBB, /* +CC */
7446 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7447 GET_OPA(rOBJ) # rOBJ <- AA
7448 and a2, a3, 255 # a2 <- BB
7449 GET_VREG(a0, a2) # a0 <- vBB
7450 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7451 .if 0
7452 # is second operand zero?
7453 beqz a1, common_errDivideByZero
7454 .endif
7455 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7456
7457 # optional op
7458 sll a0, a0, a1 # a0 <- op, a0-a3 changed
7459 GET_INST_OPCODE(t0) # extract opcode from rINST
7460 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7461 /* 10-12 instructions */
7462
7463
7464/* ------------------------------ */
7465 .balign 128
7466.L_op_shr_int_lit8: /* 0xe1 */
7467/* File: mips/op_shr_int_lit8.S */
7468/* File: mips/binopLit8.S */
7469 /*
7470 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7471 * that specifies an instruction that performs "result = a0 op a1".
7472 * This could be an MIPS instruction or a function call. (If the result
7473 * comes back in a register other than a0, you can override "result".)
7474 *
7475 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7476 * vCC (a1). Useful for integer division and modulus.
7477 *
7478 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7479 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7480 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7481 */
7482 # binop/lit8 vAA, vBB, /* +CC */
7483 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7484 GET_OPA(rOBJ) # rOBJ <- AA
7485 and a2, a3, 255 # a2 <- BB
7486 GET_VREG(a0, a2) # a0 <- vBB
7487 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7488 .if 0
7489 # is second operand zero?
7490 beqz a1, common_errDivideByZero
7491 .endif
7492 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7493
7494 # optional op
7495 sra a0, a0, a1 # a0 <- op, a0-a3 changed
7496 GET_INST_OPCODE(t0) # extract opcode from rINST
7497 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7498 /* 10-12 instructions */
7499
7500
7501/* ------------------------------ */
7502 .balign 128
7503.L_op_ushr_int_lit8: /* 0xe2 */
7504/* File: mips/op_ushr_int_lit8.S */
7505/* File: mips/binopLit8.S */
7506 /*
7507 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7508 * that specifies an instruction that performs "result = a0 op a1".
7509 * This could be an MIPS instruction or a function call. (If the result
7510 * comes back in a register other than a0, you can override "result".)
7511 *
7512 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7513 * vCC (a1). Useful for integer division and modulus.
7514 *
7515 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7516 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7517 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7518 */
7519 # binop/lit8 vAA, vBB, /* +CC */
7520 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC)
7521 GET_OPA(rOBJ) # rOBJ <- AA
7522 and a2, a3, 255 # a2 <- BB
7523 GET_VREG(a0, a2) # a0 <- vBB
7524 sra a1, a3, 8 # a1 <- ssssssCC (sign extended)
7525 .if 0
7526 # is second operand zero?
7527 beqz a1, common_errDivideByZero
7528 .endif
7529 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7530
7531 # optional op
7532 srl a0, a0, a1 # a0 <- op, a0-a3 changed
7533 GET_INST_OPCODE(t0) # extract opcode from rINST
7534 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0
7535 /* 10-12 instructions */
7536
7537
7538/* ------------------------------ */
7539 .balign 128
7540.L_op_iget_quick: /* 0xe3 */
7541/* File: mips/op_iget_quick.S */
7542 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7543 # op vA, vB, offset /* CCCC */
7544 GET_OPB(a2) # a2 <- B
7545 GET_VREG(a3, a2) # a3 <- object we're operating on
7546 FETCH(a1, 1) # a1 <- field byte offset
7547 GET_OPA4(a2) # a2 <- A(+)
7548 # check object for null
7549 beqz a3, common_errNullObject # object was null
7550 addu t0, a3, a1
7551 lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7552 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7553 GET_INST_OPCODE(t0) # extract opcode from rINST
7554 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7555
7556/* ------------------------------ */
7557 .balign 128
7558.L_op_iget_wide_quick: /* 0xe4 */
7559/* File: mips/op_iget_wide_quick.S */
7560 # iget-wide-quick vA, vB, offset /* CCCC */
7561 GET_OPB(a2) # a2 <- B
7562 GET_VREG(a3, a2) # a3 <- object we're operating on
7563 FETCH(a1, 1) # a1 <- field byte offset
7564 GET_OPA4(a2) # a2 <- A(+)
7565 # check object for null
7566 beqz a3, common_errNullObject # object was null
7567 addu t0, a3, a1 # t0 <- a3 + a1
7568 LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned)
7569 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7570 GET_INST_OPCODE(t0) # extract opcode from rINST
7571 SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1
7572 GOTO_OPCODE(t0) # jump to next instruction
7573
7574/* ------------------------------ */
7575 .balign 128
7576.L_op_iget_object_quick: /* 0xe5 */
7577/* File: mips/op_iget_object_quick.S */
7578 /* For: iget-object-quick */
7579 /* op vA, vB, offset@CCCC */
7580 GET_OPB(a2) # a2 <- B
7581 FETCH(a1, 1) # a1 <- field byte offset
7582 EXPORT_PC()
7583 GET_VREG(a0, a2) # a0 <- object we're operating on
7584 JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset)
7585 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
7586 GET_OPA4(a2) # a2<- A+
7587 PREFETCH_INST(2) # load rINST
7588 bnez a3, MterpPossibleException # bail out
7589 SET_VREG_OBJECT(v0, a2) # fp[A] <- v0
7590 ADVANCE(2) # advance rPC
7591 GET_INST_OPCODE(t0) # extract opcode from rINST
7592 GOTO_OPCODE(t0) # jump to next instruction
7593
7594/* ------------------------------ */
7595 .balign 128
7596.L_op_iput_quick: /* 0xe6 */
7597/* File: mips/op_iput_quick.S */
7598 /* For: iput-quick, iput-object-quick */
7599 # op vA, vB, offset /* CCCC */
7600 GET_OPB(a2) # a2 <- B
7601 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer
7602 FETCH(a1, 1) # a1 <- field byte offset
7603 GET_OPA4(a2) # a2 <- A(+)
7604 beqz a3, common_errNullObject # object was null
7605 GET_VREG(a0, a2) # a0 <- fp[A]
7606 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7607 addu t0, a3, a1
7608 sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7609 GET_INST_OPCODE(t0) # extract opcode from rINST
7610 GOTO_OPCODE(t0) # jump to next instruction
7611
7612/* ------------------------------ */
7613 .balign 128
7614.L_op_iput_wide_quick: /* 0xe7 */
7615/* File: mips/op_iput_wide_quick.S */
7616 # iput-wide-quick vA, vB, offset /* CCCC */
7617 GET_OPA4(a0) # a0 <- A(+)
7618 GET_OPB(a1) # a1 <- B
7619 GET_VREG(a2, a1) # a2 <- fp[B], the object pointer
7620 # check object for null
7621 beqz a2, common_errNullObject # object was null
7622 EAS2(a3, rFP, a0) # a3 <- &fp[A]
7623 LOAD64(a0, a1, a3) # a0/a1 <- fp[A]
7624 FETCH(a3, 1) # a3 <- field byte offset
7625 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7626 addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1
7627 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1
7628 GET_INST_OPCODE(t0) # extract opcode from rINST
7629 GOTO_OPCODE(t0) # jump to next instruction
7630
7631/* ------------------------------ */
7632 .balign 128
7633.L_op_iput_object_quick: /* 0xe8 */
7634/* File: mips/op_iput_object_quick.S */
7635 /* For: iput-object-quick */
7636 # op vA, vB, offset /* CCCC */
7637 EXPORT_PC()
7638 addu a0, rFP, OFF_FP_SHADOWFRAME
7639 move a1, rPC
7640 move a2, rINST
7641 JAL(MterpIputObjectQuick)
7642 beqz v0, MterpException
7643 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7644 GET_INST_OPCODE(t0) # extract opcode from rINST
7645 GOTO_OPCODE(t0) # jump to next instruction
7646
7647/* ------------------------------ */
7648 .balign 128
7649.L_op_invoke_virtual_quick: /* 0xe9 */
7650/* File: mips/op_invoke_virtual_quick.S */
7651/* File: mips/invoke.S */
7652 /*
7653 * Generic invoke handler wrapper.
7654 */
7655 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
7656 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
7657 .extern MterpInvokeVirtualQuick
7658 EXPORT_PC()
7659 move a0, rSELF
7660 addu a1, rFP, OFF_FP_SHADOWFRAME
7661 move a2, rPC
7662 move a3, rINST
7663 JAL(MterpInvokeVirtualQuick)
7664 beqz v0, MterpException
7665 FETCH_ADVANCE_INST(3)
7666 JAL(MterpShouldSwitchInterpreters)
7667 bnez v0, MterpFallback
7668 GET_INST_OPCODE(t0)
7669 GOTO_OPCODE(t0)
7670
7671
7672/* ------------------------------ */
7673 .balign 128
7674.L_op_invoke_virtual_range_quick: /* 0xea */
7675/* File: mips/op_invoke_virtual_range_quick.S */
7676/* File: mips/invoke.S */
7677 /*
7678 * Generic invoke handler wrapper.
7679 */
7680 # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */
7681 # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */
7682 .extern MterpInvokeVirtualQuickRange
7683 EXPORT_PC()
7684 move a0, rSELF
7685 addu a1, rFP, OFF_FP_SHADOWFRAME
7686 move a2, rPC
7687 move a3, rINST
7688 JAL(MterpInvokeVirtualQuickRange)
7689 beqz v0, MterpException
7690 FETCH_ADVANCE_INST(3)
7691 JAL(MterpShouldSwitchInterpreters)
7692 bnez v0, MterpFallback
7693 GET_INST_OPCODE(t0)
7694 GOTO_OPCODE(t0)
7695
7696
7697/* ------------------------------ */
7698 .balign 128
7699.L_op_iput_boolean_quick: /* 0xeb */
7700/* File: mips/op_iput_boolean_quick.S */
7701/* File: mips/op_iput_quick.S */
7702 /* For: iput-quick, iput-object-quick */
7703 # op vA, vB, offset /* CCCC */
7704 GET_OPB(a2) # a2 <- B
7705 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer
7706 FETCH(a1, 1) # a1 <- field byte offset
7707 GET_OPA4(a2) # a2 <- A(+)
7708 beqz a3, common_errNullObject # object was null
7709 GET_VREG(a0, a2) # a0 <- fp[A]
7710 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7711 addu t0, a3, a1
7712 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7713 GET_INST_OPCODE(t0) # extract opcode from rINST
7714 GOTO_OPCODE(t0) # jump to next instruction
7715
7716
7717/* ------------------------------ */
7718 .balign 128
7719.L_op_iput_byte_quick: /* 0xec */
7720/* File: mips/op_iput_byte_quick.S */
7721/* File: mips/op_iput_quick.S */
7722 /* For: iput-quick, iput-object-quick */
7723 # op vA, vB, offset /* CCCC */
7724 GET_OPB(a2) # a2 <- B
7725 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer
7726 FETCH(a1, 1) # a1 <- field byte offset
7727 GET_OPA4(a2) # a2 <- A(+)
7728 beqz a3, common_errNullObject # object was null
7729 GET_VREG(a0, a2) # a0 <- fp[A]
7730 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7731 addu t0, a3, a1
7732 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7733 GET_INST_OPCODE(t0) # extract opcode from rINST
7734 GOTO_OPCODE(t0) # jump to next instruction
7735
7736
7737/* ------------------------------ */
7738 .balign 128
7739.L_op_iput_char_quick: /* 0xed */
7740/* File: mips/op_iput_char_quick.S */
7741/* File: mips/op_iput_quick.S */
7742 /* For: iput-quick, iput-object-quick */
7743 # op vA, vB, offset /* CCCC */
7744 GET_OPB(a2) # a2 <- B
7745 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer
7746 FETCH(a1, 1) # a1 <- field byte offset
7747 GET_OPA4(a2) # a2 <- A(+)
7748 beqz a3, common_errNullObject # object was null
7749 GET_VREG(a0, a2) # a0 <- fp[A]
7750 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7751 addu t0, a3, a1
7752 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7753 GET_INST_OPCODE(t0) # extract opcode from rINST
7754 GOTO_OPCODE(t0) # jump to next instruction
7755
7756
7757/* ------------------------------ */
7758 .balign 128
7759.L_op_iput_short_quick: /* 0xee */
7760/* File: mips/op_iput_short_quick.S */
7761/* File: mips/op_iput_quick.S */
7762 /* For: iput-quick, iput-object-quick */
7763 # op vA, vB, offset /* CCCC */
7764 GET_OPB(a2) # a2 <- B
7765 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer
7766 FETCH(a1, 1) # a1 <- field byte offset
7767 GET_OPA4(a2) # a2 <- A(+)
7768 beqz a3, common_errNullObject # object was null
7769 GET_VREG(a0, a2) # a0 <- fp[A]
7770 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7771 addu t0, a3, a1
7772 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0
7773 GET_INST_OPCODE(t0) # extract opcode from rINST
7774 GOTO_OPCODE(t0) # jump to next instruction
7775
7776
7777/* ------------------------------ */
7778 .balign 128
7779.L_op_iget_boolean_quick: /* 0xef */
7780/* File: mips/op_iget_boolean_quick.S */
7781/* File: mips/op_iget_quick.S */
7782 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7783 # op vA, vB, offset /* CCCC */
7784 GET_OPB(a2) # a2 <- B
7785 GET_VREG(a3, a2) # a3 <- object we're operating on
7786 FETCH(a1, 1) # a1 <- field byte offset
7787 GET_OPA4(a2) # a2 <- A(+)
7788 # check object for null
7789 beqz a3, common_errNullObject # object was null
7790 addu t0, a3, a1
7791 lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7792 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7793 GET_INST_OPCODE(t0) # extract opcode from rINST
7794 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7795
7796
7797/* ------------------------------ */
7798 .balign 128
7799.L_op_iget_byte_quick: /* 0xf0 */
7800/* File: mips/op_iget_byte_quick.S */
7801/* File: mips/op_iget_quick.S */
7802 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7803 # op vA, vB, offset /* CCCC */
7804 GET_OPB(a2) # a2 <- B
7805 GET_VREG(a3, a2) # a3 <- object we're operating on
7806 FETCH(a1, 1) # a1 <- field byte offset
7807 GET_OPA4(a2) # a2 <- A(+)
7808 # check object for null
7809 beqz a3, common_errNullObject # object was null
7810 addu t0, a3, a1
7811 lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7812 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7813 GET_INST_OPCODE(t0) # extract opcode from rINST
7814 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7815
7816
7817/* ------------------------------ */
7818 .balign 128
7819.L_op_iget_char_quick: /* 0xf1 */
7820/* File: mips/op_iget_char_quick.S */
7821/* File: mips/op_iget_quick.S */
7822 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7823 # op vA, vB, offset /* CCCC */
7824 GET_OPB(a2) # a2 <- B
7825 GET_VREG(a3, a2) # a3 <- object we're operating on
7826 FETCH(a1, 1) # a1 <- field byte offset
7827 GET_OPA4(a2) # a2 <- A(+)
7828 # check object for null
7829 beqz a3, common_errNullObject # object was null
7830 addu t0, a3, a1
7831 lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7832 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7833 GET_INST_OPCODE(t0) # extract opcode from rINST
7834 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7835
7836
7837/* ------------------------------ */
7838 .balign 128
7839.L_op_iget_short_quick: /* 0xf2 */
7840/* File: mips/op_iget_short_quick.S */
7841/* File: mips/op_iget_quick.S */
7842 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7843 # op vA, vB, offset /* CCCC */
7844 GET_OPB(a2) # a2 <- B
7845 GET_VREG(a3, a2) # a3 <- object we're operating on
7846 FETCH(a1, 1) # a1 <- field byte offset
7847 GET_OPA4(a2) # a2 <- A(+)
7848 # check object for null
7849 beqz a3, common_errNullObject # object was null
7850 addu t0, a3, a1
7851 lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits)
7852 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
7853 GET_INST_OPCODE(t0) # extract opcode from rINST
7854 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0
7855
7856
7857/* ------------------------------ */
7858 .balign 128
7859.L_op_invoke_lambda: /* 0xf3 */
7860/* Transfer stub to alternate interpreter */
7861 b MterpFallback
7862
7863/* ------------------------------ */
7864 .balign 128
7865.L_op_unused_f4: /* 0xf4 */
7866/* File: mips/op_unused_f4.S */
7867/* File: mips/unused.S */
7868/*
7869 * Bail to reference interpreter to throw.
7870 */
7871 b MterpFallback
7872
7873
7874/* ------------------------------ */
7875 .balign 128
7876.L_op_capture_variable: /* 0xf5 */
7877/* Transfer stub to alternate interpreter */
7878 b MterpFallback
7879
7880/* ------------------------------ */
7881 .balign 128
7882.L_op_create_lambda: /* 0xf6 */
7883/* Transfer stub to alternate interpreter */
7884 b MterpFallback
7885
7886/* ------------------------------ */
7887 .balign 128
7888.L_op_liberate_variable: /* 0xf7 */
7889/* Transfer stub to alternate interpreter */
7890 b MterpFallback
7891
7892/* ------------------------------ */
7893 .balign 128
7894.L_op_box_lambda: /* 0xf8 */
7895/* Transfer stub to alternate interpreter */
7896 b MterpFallback
7897
7898/* ------------------------------ */
7899 .balign 128
7900.L_op_unbox_lambda: /* 0xf9 */
7901/* Transfer stub to alternate interpreter */
7902 b MterpFallback
7903
7904/* ------------------------------ */
7905 .balign 128
7906.L_op_unused_fa: /* 0xfa */
7907/* File: mips/op_unused_fa.S */
7908/* File: mips/unused.S */
7909/*
7910 * Bail to reference interpreter to throw.
7911 */
7912 b MterpFallback
7913
7914
7915/* ------------------------------ */
7916 .balign 128
7917.L_op_unused_fb: /* 0xfb */
7918/* File: mips/op_unused_fb.S */
7919/* File: mips/unused.S */
7920/*
7921 * Bail to reference interpreter to throw.
7922 */
7923 b MterpFallback
7924
7925
7926/* ------------------------------ */
7927 .balign 128
7928.L_op_unused_fc: /* 0xfc */
7929/* File: mips/op_unused_fc.S */
7930/* File: mips/unused.S */
7931/*
7932 * Bail to reference interpreter to throw.
7933 */
7934 b MterpFallback
7935
7936
7937/* ------------------------------ */
7938 .balign 128
7939.L_op_unused_fd: /* 0xfd */
7940/* File: mips/op_unused_fd.S */
7941/* File: mips/unused.S */
7942/*
7943 * Bail to reference interpreter to throw.
7944 */
7945 b MterpFallback
7946
7947
7948/* ------------------------------ */
7949 .balign 128
7950.L_op_unused_fe: /* 0xfe */
7951/* File: mips/op_unused_fe.S */
7952/* File: mips/unused.S */
7953/*
7954 * Bail to reference interpreter to throw.
7955 */
7956 b MterpFallback
7957
7958
7959/* ------------------------------ */
7960 .balign 128
7961.L_op_unused_ff: /* 0xff */
7962/* File: mips/op_unused_ff.S */
7963/* File: mips/unused.S */
7964/*
7965 * Bail to reference interpreter to throw.
7966 */
7967 b MterpFallback
7968
7969
7970 .balign 128
7971 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart
7972 .global artMterpAsmInstructionEnd
7973artMterpAsmInstructionEnd:
7974
7975/*
7976 * ===========================================================================
7977 * Sister implementations
7978 * ===========================================================================
7979 */
7980 .global artMterpAsmSisterStart
7981 .type artMterpAsmSisterStart, %function
7982 .text
7983 .balign 4
7984artMterpAsmSisterStart:
7985
7986/* continuation for op_packed_switch */
7987
7988.Lop_packed_switch_finish:
7989 GET_INST_OPCODE(t0) # extract opcode from rINST
7990 GOTO_OPCODE(t0) # jump to next instruction
7991
7992/* continuation for op_sparse_switch */
7993
7994.Lop_sparse_switch_finish:
7995 GET_INST_OPCODE(t0) # extract opcode from rINST
7996 GOTO_OPCODE(t0) # jump to next instruction
7997
7998/* continuation for op_cmpl_float */
7999
8000.Lop_cmpl_float_nan:
8001 li rTEMP, -1
8002
8003.Lop_cmpl_float_finish:
8004 GET_OPA(rOBJ)
8005 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
8006 GET_INST_OPCODE(t0) # extract opcode from rINST
8007 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP
8008
8009/* continuation for op_cmpg_float */
8010
8011.Lop_cmpg_float_nan:
8012 li rTEMP, 1
8013
8014.Lop_cmpg_float_finish:
8015 GET_OPA(rOBJ)
8016 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
8017 GET_INST_OPCODE(t0) # extract opcode from rINST
8018 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP
8019
8020/* continuation for op_cmpl_double */
8021
8022.Lop_cmpl_double_nan:
8023 li rTEMP, -1
8024
8025.Lop_cmpl_double_finish:
8026 GET_OPA(rOBJ)
8027 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
8028 GET_INST_OPCODE(t0) # extract opcode from rINST
8029 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP
8030
8031/* continuation for op_cmpg_double */
8032
8033.Lop_cmpg_double_nan:
8034 li rTEMP, 1
8035
8036.Lop_cmpg_double_finish:
8037 GET_OPA(rOBJ)
8038 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
8039 GET_INST_OPCODE(t0) # extract opcode from rINST
8040 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP
8041
8042/* continuation for op_if_eq */
8043
8044.L_op_if_eq_finish:
8045 GET_INST_OPCODE(t0) # extract opcode from rINST
8046 GOTO_OPCODE(t0) # jump to next instruction
8047
8048/* continuation for op_if_ne */
8049
8050.L_op_if_ne_finish:
8051 GET_INST_OPCODE(t0) # extract opcode from rINST
8052 GOTO_OPCODE(t0) # jump to next instruction
8053
8054/* continuation for op_if_lt */
8055
8056.L_op_if_lt_finish:
8057 GET_INST_OPCODE(t0) # extract opcode from rINST
8058 GOTO_OPCODE(t0) # jump to next instruction
8059
8060/* continuation for op_if_ge */
8061
8062.L_op_if_ge_finish:
8063 GET_INST_OPCODE(t0) # extract opcode from rINST
8064 GOTO_OPCODE(t0) # jump to next instruction
8065
8066/* continuation for op_if_gt */
8067
8068.L_op_if_gt_finish:
8069 GET_INST_OPCODE(t0) # extract opcode from rINST
8070 GOTO_OPCODE(t0) # jump to next instruction
8071
8072/* continuation for op_if_le */
8073
8074.L_op_if_le_finish:
8075 GET_INST_OPCODE(t0) # extract opcode from rINST
8076 GOTO_OPCODE(t0) # jump to next instruction
8077
8078/* continuation for op_float_to_int */
8079
8080/*
8081 * Not an entry point as it is used only once !!
8082 */
8083f2i_doconv:
8084#ifdef MIPS32REVGE6
8085 l.s fa1, .LFLOAT_TO_INT_max
8086 cmp.ule.s ft2, fa1, fa0
8087 l.s fv0, .LFLOAT_TO_INT_ret_max
8088 bc1nez ft2, .Lop_float_to_int_set_vreg_f
8089
8090 l.s fa1, .LFLOAT_TO_INT_min
8091 cmp.ule.s ft2, fa0, fa1
8092 l.s fv0, .LFLOAT_TO_INT_ret_min
8093 bc1nez ft2, .Lop_float_to_int_set_vreg_f
8094
8095 mov.s fa1, fa0
8096 cmp.un.s ft2, fa0, fa1
8097 li.s fv0, 0
8098 bc1nez ft2, .Lop_float_to_int_set_vreg_f
8099#else
8100 l.s fa1, .LFLOAT_TO_INT_max
8101 c.ole.s fcc0, fa1, fa0
8102 l.s fv0, .LFLOAT_TO_INT_ret_max
8103 bc1t .Lop_float_to_int_set_vreg_f
8104
8105 l.s fa1, .LFLOAT_TO_INT_min
8106 c.ole.s fcc0, fa0, fa1
8107 l.s fv0, .LFLOAT_TO_INT_ret_min
8108 bc1t .Lop_float_to_int_set_vreg_f
8109
8110 mov.s fa1, fa0
8111 c.un.s fcc0, fa0, fa1
8112 li.s fv0, 0
8113 bc1t .Lop_float_to_int_set_vreg_f
8114#endif
8115
8116 trunc.w.s fv0, fa0
8117 b .Lop_float_to_int_set_vreg_f
8118
8119.LFLOAT_TO_INT_max:
8120 .word 0x4f000000
8121.LFLOAT_TO_INT_min:
8122 .word 0xcf000000
8123.LFLOAT_TO_INT_ret_max:
8124 .word 0x7fffffff
8125.LFLOAT_TO_INT_ret_min:
8126 .word 0x80000000
8127
8128/* continuation for op_float_to_long */
8129
8130f2l_doconv:
8131#ifdef MIPS32REVGE6
8132 l.s fa1, .LLONG_TO_max
8133 cmp.ule.s ft2, fa1, fa0
8134 li rRESULT0, ~0
8135 li rRESULT1, ~0x80000000
8136 bc1nez ft2, .Lop_float_to_long_set_vreg
8137
8138 l.s fa1, .LLONG_TO_min
8139 cmp.ule.s ft2, fa0, fa1
8140 li rRESULT0, 0
8141 li rRESULT1, 0x80000000
8142 bc1nez ft2, .Lop_float_to_long_set_vreg
8143
8144 mov.s fa1, fa0
8145 cmp.un.s ft2, fa0, fa1
8146 li rRESULT0, 0
8147 li rRESULT1, 0
8148 bc1nez ft2, .Lop_float_to_long_set_vreg
8149#else
8150 l.s fa1, .LLONG_TO_max
8151 c.ole.s fcc0, fa1, fa0
8152 li rRESULT0, ~0
8153 li rRESULT1, ~0x80000000
8154 bc1t .Lop_float_to_long_set_vreg
8155
8156 l.s fa1, .LLONG_TO_min
8157 c.ole.s fcc0, fa0, fa1
8158 li rRESULT0, 0
8159 li rRESULT1, 0x80000000
8160 bc1t .Lop_float_to_long_set_vreg
8161
8162 mov.s fa1, fa0
8163 c.un.s fcc0, fa0, fa1
8164 li rRESULT0, 0
8165 li rRESULT1, 0
8166 bc1t .Lop_float_to_long_set_vreg
8167#endif
8168
8169 JAL(__fixsfdi)
8170
8171 b .Lop_float_to_long_set_vreg
8172
8173.LLONG_TO_max:
8174 .word 0x5f000000
8175
8176.LLONG_TO_min:
8177 .word 0xdf000000
8178
8179/* continuation for op_double_to_int */
8180
8181d2i_doconv:
8182#ifdef MIPS32REVGE6
8183 la t0, .LDOUBLE_TO_INT_max
8184 LOAD64_F(fa1, fa1f, t0)
8185 cmp.ule.d ft2, fa1, fa0
8186 l.s fv0, .LDOUBLE_TO_INT_maxret
8187 bc1nez ft2, .Lop_double_to_int_set_vreg_f
8188
8189 la t0, .LDOUBLE_TO_INT_min
8190 LOAD64_F(fa1, fa1f, t0)
8191 cmp.ule.d ft2, fa0, fa1
8192 l.s fv0, .LDOUBLE_TO_INT_minret
8193 bc1nez ft2, .Lop_double_to_int_set_vreg_f
8194
8195 mov.d fa1, fa0
8196 cmp.un.d ft2, fa0, fa1
8197 li.s fv0, 0
8198 bc1nez ft2, .Lop_double_to_int_set_vreg_f
8199#else
8200 la t0, .LDOUBLE_TO_INT_max
8201 LOAD64_F(fa1, fa1f, t0)
8202 c.ole.d fcc0, fa1, fa0
8203 l.s fv0, .LDOUBLE_TO_INT_maxret
8204 bc1t .Lop_double_to_int_set_vreg_f
8205
8206 la t0, .LDOUBLE_TO_INT_min
8207 LOAD64_F(fa1, fa1f, t0)
8208 c.ole.d fcc0, fa0, fa1
8209 l.s fv0, .LDOUBLE_TO_INT_minret
8210 bc1t .Lop_double_to_int_set_vreg_f
8211
8212 mov.d fa1, fa0
8213 c.un.d fcc0, fa0, fa1
8214 li.s fv0, 0
8215 bc1t .Lop_double_to_int_set_vreg_f
8216#endif
8217
8218 trunc.w.d fv0, fa0
8219 b .Lop_double_to_int_set_vreg_f
8220
8221.LDOUBLE_TO_INT_max:
8222 .dword 0x41dfffffffc00000
8223.LDOUBLE_TO_INT_min:
8224 .dword 0xc1e0000000000000 # minint, as a double (high word)
8225.LDOUBLE_TO_INT_maxret:
8226 .word 0x7fffffff
8227.LDOUBLE_TO_INT_minret:
8228 .word 0x80000000
8229
8230/* continuation for op_double_to_long */
8231
8232d2l_doconv:
8233#ifdef MIPS32REVGE6
8234 la t0, .LDOUBLE_TO_LONG_max
8235 LOAD64_F(fa1, fa1f, t0)
8236 cmp.ule.d ft2, fa1, fa0
8237 la t0, .LDOUBLE_TO_LONG_ret_max
8238 LOAD64(rRESULT0, rRESULT1, t0)
8239 bc1nez ft2, .Lop_double_to_long_set_vreg
8240
8241 la t0, .LDOUBLE_TO_LONG_min
8242 LOAD64_F(fa1, fa1f, t0)
8243 cmp.ule.d ft2, fa0, fa1
8244 la t0, .LDOUBLE_TO_LONG_ret_min
8245 LOAD64(rRESULT0, rRESULT1, t0)
8246 bc1nez ft2, .Lop_double_to_long_set_vreg
8247
8248 mov.d fa1, fa0
8249 cmp.un.d ft2, fa0, fa1
8250 li rRESULT0, 0
8251 li rRESULT1, 0
8252 bc1nez ft2, .Lop_double_to_long_set_vreg
8253#else
8254 la t0, .LDOUBLE_TO_LONG_max
8255 LOAD64_F(fa1, fa1f, t0)
8256 c.ole.d fcc0, fa1, fa0
8257 la t0, .LDOUBLE_TO_LONG_ret_max
8258 LOAD64(rRESULT0, rRESULT1, t0)
8259 bc1t .Lop_double_to_long_set_vreg
8260
8261 la t0, .LDOUBLE_TO_LONG_min
8262 LOAD64_F(fa1, fa1f, t0)
8263 c.ole.d fcc0, fa0, fa1
8264 la t0, .LDOUBLE_TO_LONG_ret_min
8265 LOAD64(rRESULT0, rRESULT1, t0)
8266 bc1t .Lop_double_to_long_set_vreg
8267
8268 mov.d fa1, fa0
8269 c.un.d fcc0, fa0, fa1
8270 li rRESULT0, 0
8271 li rRESULT1, 0
8272 bc1t .Lop_double_to_long_set_vreg
8273#endif
8274 JAL(__fixdfdi)
8275 b .Lop_double_to_long_set_vreg
8276
8277.LDOUBLE_TO_LONG_max:
8278 .dword 0x43e0000000000000 # maxlong, as a double (high word)
8279.LDOUBLE_TO_LONG_min:
8280 .dword 0xc3e0000000000000 # minlong, as a double (high word)
8281.LDOUBLE_TO_LONG_ret_max:
8282 .dword 0x7fffffffffffffff
8283.LDOUBLE_TO_LONG_ret_min:
8284 .dword 0x8000000000000000
8285
8286/* continuation for op_mul_long */
8287
8288.Lop_mul_long_finish:
8289 GET_INST_OPCODE(t0) # extract opcode from rINST
8290 SET_VREG64(v0, v1, a0) # vAA::vAA+1 <- v0(low) :: v1(high)
8291 GOTO_OPCODE(t0) # jump to next instruction
8292
8293/* continuation for op_shl_long */
8294
8295.Lop_shl_long_finish:
8296 SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi
8297
8298/* continuation for op_shr_long */
8299
8300.Lop_shr_long_finish:
8301 sra a3, a1, 31 # a3<- sign(ah)
8302 SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi
8303
8304/* continuation for op_ushr_long */
8305
8306.Lop_ushr_long_finish:
8307 SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi
8308
8309/* continuation for op_add_double */
8310
8311.Lop_add_double_finish:
8312 GET_INST_OPCODE(t0) # extract opcode from rINST
8313 GOTO_OPCODE(t0) # jump to next instruction
8314
8315/* continuation for op_sub_double */
8316
8317.Lop_sub_double_finish:
8318 GET_INST_OPCODE(t0) # extract opcode from rINST
8319 GOTO_OPCODE(t0) # jump to next instruction
8320
8321/* continuation for op_mul_double */
8322
8323.Lop_mul_double_finish:
8324 GET_INST_OPCODE(t0) # extract opcode from rINST
8325 GOTO_OPCODE(t0) # jump to next instruction
8326
8327/* continuation for op_div_double */
8328
8329.Lop_div_double_finish:
8330 GET_INST_OPCODE(t0) # extract opcode from rINST
8331 GOTO_OPCODE(t0) # jump to next instruction
8332
8333/* continuation for op_rem_double */
8334
8335.Lop_rem_double_finish:
8336 GET_INST_OPCODE(t0) # extract opcode from rINST
8337 GOTO_OPCODE(t0) # jump to next instruction
8338
8339/* continuation for op_shl_long_2addr */
8340
8341.Lop_shl_long_2addr_finish:
8342 SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi
8343
8344/* continuation for op_shr_long_2addr */
8345
8346.Lop_shr_long_2addr_finish:
8347 sra a3, a1, 31 # a3<- sign(ah)
8348 SET_VREG64_GOTO(v1, a3, t2, t0) # vAA/vAA+1 <- rlo/rhi
8349
8350/* continuation for op_ushr_long_2addr */
8351
8352.Lop_ushr_long_2addr_finish:
8353 SET_VREG64_GOTO(v1, zero, t3, t0) # vAA/vAA+1 <- rlo/rhi
8354
8355 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart
8356 .global artMterpAsmSisterEnd
8357artMterpAsmSisterEnd:
8358
8359
8360 .global artMterpAsmAltInstructionStart
8361 .type artMterpAsmAltInstructionStart, %function
8362 .text
8363
8364artMterpAsmAltInstructionStart = .L_ALT_op_nop
8365/* ------------------------------ */
8366 .balign 128
8367.L_ALT_op_nop: /* 0x00 */
8368/* File: mips/alt_stub.S */
8369/*
8370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8371 * any interesting requests and then jump to the real instruction
8372 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8373 */
8374 .extern MterpCheckBefore
8375 EXPORT_PC()
8376 la ra, artMterpAsmInstructionStart + (0 * 128) # Addr of primary handler
8377 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8378 move a0, rSELF # arg0
8379 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8380 la a2, MterpCheckBefore
8381 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8382
8383/* ------------------------------ */
8384 .balign 128
8385.L_ALT_op_move: /* 0x01 */
8386/* File: mips/alt_stub.S */
8387/*
8388 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8389 * any interesting requests and then jump to the real instruction
8390 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8391 */
8392 .extern MterpCheckBefore
8393 EXPORT_PC()
8394 la ra, artMterpAsmInstructionStart + (1 * 128) # Addr of primary handler
8395 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8396 move a0, rSELF # arg0
8397 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8398 la a2, MterpCheckBefore
8399 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8400
8401/* ------------------------------ */
8402 .balign 128
8403.L_ALT_op_move_from16: /* 0x02 */
8404/* File: mips/alt_stub.S */
8405/*
8406 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8407 * any interesting requests and then jump to the real instruction
8408 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8409 */
8410 .extern MterpCheckBefore
8411 EXPORT_PC()
8412 la ra, artMterpAsmInstructionStart + (2 * 128) # Addr of primary handler
8413 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8414 move a0, rSELF # arg0
8415 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8416 la a2, MterpCheckBefore
8417 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8418
8419/* ------------------------------ */
8420 .balign 128
8421.L_ALT_op_move_16: /* 0x03 */
8422/* File: mips/alt_stub.S */
8423/*
8424 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8425 * any interesting requests and then jump to the real instruction
8426 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8427 */
8428 .extern MterpCheckBefore
8429 EXPORT_PC()
8430 la ra, artMterpAsmInstructionStart + (3 * 128) # Addr of primary handler
8431 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8432 move a0, rSELF # arg0
8433 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8434 la a2, MterpCheckBefore
8435 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8436
8437/* ------------------------------ */
8438 .balign 128
8439.L_ALT_op_move_wide: /* 0x04 */
8440/* File: mips/alt_stub.S */
8441/*
8442 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8443 * any interesting requests and then jump to the real instruction
8444 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8445 */
8446 .extern MterpCheckBefore
8447 EXPORT_PC()
8448 la ra, artMterpAsmInstructionStart + (4 * 128) # Addr of primary handler
8449 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8450 move a0, rSELF # arg0
8451 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8452 la a2, MterpCheckBefore
8453 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8454
8455/* ------------------------------ */
8456 .balign 128
8457.L_ALT_op_move_wide_from16: /* 0x05 */
8458/* File: mips/alt_stub.S */
8459/*
8460 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8461 * any interesting requests and then jump to the real instruction
8462 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8463 */
8464 .extern MterpCheckBefore
8465 EXPORT_PC()
8466 la ra, artMterpAsmInstructionStart + (5 * 128) # Addr of primary handler
8467 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8468 move a0, rSELF # arg0
8469 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8470 la a2, MterpCheckBefore
8471 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8472
8473/* ------------------------------ */
8474 .balign 128
8475.L_ALT_op_move_wide_16: /* 0x06 */
8476/* File: mips/alt_stub.S */
8477/*
8478 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8479 * any interesting requests and then jump to the real instruction
8480 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8481 */
8482 .extern MterpCheckBefore
8483 EXPORT_PC()
8484 la ra, artMterpAsmInstructionStart + (6 * 128) # Addr of primary handler
8485 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8486 move a0, rSELF # arg0
8487 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8488 la a2, MterpCheckBefore
8489 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8490
8491/* ------------------------------ */
8492 .balign 128
8493.L_ALT_op_move_object: /* 0x07 */
8494/* File: mips/alt_stub.S */
8495/*
8496 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8497 * any interesting requests and then jump to the real instruction
8498 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8499 */
8500 .extern MterpCheckBefore
8501 EXPORT_PC()
8502 la ra, artMterpAsmInstructionStart + (7 * 128) # Addr of primary handler
8503 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8504 move a0, rSELF # arg0
8505 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8506 la a2, MterpCheckBefore
8507 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8508
8509/* ------------------------------ */
8510 .balign 128
8511.L_ALT_op_move_object_from16: /* 0x08 */
8512/* File: mips/alt_stub.S */
8513/*
8514 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8515 * any interesting requests and then jump to the real instruction
8516 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8517 */
8518 .extern MterpCheckBefore
8519 EXPORT_PC()
8520 la ra, artMterpAsmInstructionStart + (8 * 128) # Addr of primary handler
8521 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8522 move a0, rSELF # arg0
8523 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8524 la a2, MterpCheckBefore
8525 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8526
8527/* ------------------------------ */
8528 .balign 128
8529.L_ALT_op_move_object_16: /* 0x09 */
8530/* File: mips/alt_stub.S */
8531/*
8532 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8533 * any interesting requests and then jump to the real instruction
8534 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8535 */
8536 .extern MterpCheckBefore
8537 EXPORT_PC()
8538 la ra, artMterpAsmInstructionStart + (9 * 128) # Addr of primary handler
8539 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8540 move a0, rSELF # arg0
8541 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8542 la a2, MterpCheckBefore
8543 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8544
8545/* ------------------------------ */
8546 .balign 128
8547.L_ALT_op_move_result: /* 0x0a */
8548/* File: mips/alt_stub.S */
8549/*
8550 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8551 * any interesting requests and then jump to the real instruction
8552 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8553 */
8554 .extern MterpCheckBefore
8555 EXPORT_PC()
8556 la ra, artMterpAsmInstructionStart + (10 * 128) # Addr of primary handler
8557 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8558 move a0, rSELF # arg0
8559 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8560 la a2, MterpCheckBefore
8561 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8562
8563/* ------------------------------ */
8564 .balign 128
8565.L_ALT_op_move_result_wide: /* 0x0b */
8566/* File: mips/alt_stub.S */
8567/*
8568 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8569 * any interesting requests and then jump to the real instruction
8570 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8571 */
8572 .extern MterpCheckBefore
8573 EXPORT_PC()
8574 la ra, artMterpAsmInstructionStart + (11 * 128) # Addr of primary handler
8575 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8576 move a0, rSELF # arg0
8577 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8578 la a2, MterpCheckBefore
8579 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8580
8581/* ------------------------------ */
8582 .balign 128
8583.L_ALT_op_move_result_object: /* 0x0c */
8584/* File: mips/alt_stub.S */
8585/*
8586 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8587 * any interesting requests and then jump to the real instruction
8588 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8589 */
8590 .extern MterpCheckBefore
8591 EXPORT_PC()
8592 la ra, artMterpAsmInstructionStart + (12 * 128) # Addr of primary handler
8593 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8594 move a0, rSELF # arg0
8595 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8596 la a2, MterpCheckBefore
8597 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8598
8599/* ------------------------------ */
8600 .balign 128
8601.L_ALT_op_move_exception: /* 0x0d */
8602/* File: mips/alt_stub.S */
8603/*
8604 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8605 * any interesting requests and then jump to the real instruction
8606 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8607 */
8608 .extern MterpCheckBefore
8609 EXPORT_PC()
8610 la ra, artMterpAsmInstructionStart + (13 * 128) # Addr of primary handler
8611 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8612 move a0, rSELF # arg0
8613 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8614 la a2, MterpCheckBefore
8615 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8616
8617/* ------------------------------ */
8618 .balign 128
8619.L_ALT_op_return_void: /* 0x0e */
8620/* File: mips/alt_stub.S */
8621/*
8622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8623 * any interesting requests and then jump to the real instruction
8624 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8625 */
8626 .extern MterpCheckBefore
8627 EXPORT_PC()
8628 la ra, artMterpAsmInstructionStart + (14 * 128) # Addr of primary handler
8629 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8630 move a0, rSELF # arg0
8631 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8632 la a2, MterpCheckBefore
8633 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8634
8635/* ------------------------------ */
8636 .balign 128
8637.L_ALT_op_return: /* 0x0f */
8638/* File: mips/alt_stub.S */
8639/*
8640 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8641 * any interesting requests and then jump to the real instruction
8642 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8643 */
8644 .extern MterpCheckBefore
8645 EXPORT_PC()
8646 la ra, artMterpAsmInstructionStart + (15 * 128) # Addr of primary handler
8647 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8648 move a0, rSELF # arg0
8649 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8650 la a2, MterpCheckBefore
8651 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8652
8653/* ------------------------------ */
8654 .balign 128
8655.L_ALT_op_return_wide: /* 0x10 */
8656/* File: mips/alt_stub.S */
8657/*
8658 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8659 * any interesting requests and then jump to the real instruction
8660 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8661 */
8662 .extern MterpCheckBefore
8663 EXPORT_PC()
8664 la ra, artMterpAsmInstructionStart + (16 * 128) # Addr of primary handler
8665 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8666 move a0, rSELF # arg0
8667 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8668 la a2, MterpCheckBefore
8669 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8670
8671/* ------------------------------ */
8672 .balign 128
8673.L_ALT_op_return_object: /* 0x11 */
8674/* File: mips/alt_stub.S */
8675/*
8676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8677 * any interesting requests and then jump to the real instruction
8678 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8679 */
8680 .extern MterpCheckBefore
8681 EXPORT_PC()
8682 la ra, artMterpAsmInstructionStart + (17 * 128) # Addr of primary handler
8683 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8684 move a0, rSELF # arg0
8685 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8686 la a2, MterpCheckBefore
8687 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8688
8689/* ------------------------------ */
8690 .balign 128
8691.L_ALT_op_const_4: /* 0x12 */
8692/* File: mips/alt_stub.S */
8693/*
8694 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8695 * any interesting requests and then jump to the real instruction
8696 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8697 */
8698 .extern MterpCheckBefore
8699 EXPORT_PC()
8700 la ra, artMterpAsmInstructionStart + (18 * 128) # Addr of primary handler
8701 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8702 move a0, rSELF # arg0
8703 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8704 la a2, MterpCheckBefore
8705 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8706
8707/* ------------------------------ */
8708 .balign 128
8709.L_ALT_op_const_16: /* 0x13 */
8710/* File: mips/alt_stub.S */
8711/*
8712 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8713 * any interesting requests and then jump to the real instruction
8714 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8715 */
8716 .extern MterpCheckBefore
8717 EXPORT_PC()
8718 la ra, artMterpAsmInstructionStart + (19 * 128) # Addr of primary handler
8719 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8720 move a0, rSELF # arg0
8721 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8722 la a2, MterpCheckBefore
8723 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8724
8725/* ------------------------------ */
8726 .balign 128
8727.L_ALT_op_const: /* 0x14 */
8728/* File: mips/alt_stub.S */
8729/*
8730 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8731 * any interesting requests and then jump to the real instruction
8732 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8733 */
8734 .extern MterpCheckBefore
8735 EXPORT_PC()
8736 la ra, artMterpAsmInstructionStart + (20 * 128) # Addr of primary handler
8737 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8738 move a0, rSELF # arg0
8739 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8740 la a2, MterpCheckBefore
8741 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8742
8743/* ------------------------------ */
8744 .balign 128
8745.L_ALT_op_const_high16: /* 0x15 */
8746/* File: mips/alt_stub.S */
8747/*
8748 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8749 * any interesting requests and then jump to the real instruction
8750 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8751 */
8752 .extern MterpCheckBefore
8753 EXPORT_PC()
8754 la ra, artMterpAsmInstructionStart + (21 * 128) # Addr of primary handler
8755 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8756 move a0, rSELF # arg0
8757 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8758 la a2, MterpCheckBefore
8759 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8760
8761/* ------------------------------ */
8762 .balign 128
8763.L_ALT_op_const_wide_16: /* 0x16 */
8764/* File: mips/alt_stub.S */
8765/*
8766 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8767 * any interesting requests and then jump to the real instruction
8768 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8769 */
8770 .extern MterpCheckBefore
8771 EXPORT_PC()
8772 la ra, artMterpAsmInstructionStart + (22 * 128) # Addr of primary handler
8773 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8774 move a0, rSELF # arg0
8775 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8776 la a2, MterpCheckBefore
8777 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8778
8779/* ------------------------------ */
8780 .balign 128
8781.L_ALT_op_const_wide_32: /* 0x17 */
8782/* File: mips/alt_stub.S */
8783/*
8784 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8785 * any interesting requests and then jump to the real instruction
8786 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8787 */
8788 .extern MterpCheckBefore
8789 EXPORT_PC()
8790 la ra, artMterpAsmInstructionStart + (23 * 128) # Addr of primary handler
8791 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8792 move a0, rSELF # arg0
8793 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8794 la a2, MterpCheckBefore
8795 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8796
8797/* ------------------------------ */
8798 .balign 128
8799.L_ALT_op_const_wide: /* 0x18 */
8800/* File: mips/alt_stub.S */
8801/*
8802 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8803 * any interesting requests and then jump to the real instruction
8804 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8805 */
8806 .extern MterpCheckBefore
8807 EXPORT_PC()
8808 la ra, artMterpAsmInstructionStart + (24 * 128) # Addr of primary handler
8809 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8810 move a0, rSELF # arg0
8811 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8812 la a2, MterpCheckBefore
8813 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8814
8815/* ------------------------------ */
8816 .balign 128
8817.L_ALT_op_const_wide_high16: /* 0x19 */
8818/* File: mips/alt_stub.S */
8819/*
8820 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8821 * any interesting requests and then jump to the real instruction
8822 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8823 */
8824 .extern MterpCheckBefore
8825 EXPORT_PC()
8826 la ra, artMterpAsmInstructionStart + (25 * 128) # Addr of primary handler
8827 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8828 move a0, rSELF # arg0
8829 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8830 la a2, MterpCheckBefore
8831 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8832
8833/* ------------------------------ */
8834 .balign 128
8835.L_ALT_op_const_string: /* 0x1a */
8836/* File: mips/alt_stub.S */
8837/*
8838 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8839 * any interesting requests and then jump to the real instruction
8840 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8841 */
8842 .extern MterpCheckBefore
8843 EXPORT_PC()
8844 la ra, artMterpAsmInstructionStart + (26 * 128) # Addr of primary handler
8845 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8846 move a0, rSELF # arg0
8847 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8848 la a2, MterpCheckBefore
8849 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8850
8851/* ------------------------------ */
8852 .balign 128
8853.L_ALT_op_const_string_jumbo: /* 0x1b */
8854/* File: mips/alt_stub.S */
8855/*
8856 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8857 * any interesting requests and then jump to the real instruction
8858 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8859 */
8860 .extern MterpCheckBefore
8861 EXPORT_PC()
8862 la ra, artMterpAsmInstructionStart + (27 * 128) # Addr of primary handler
8863 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8864 move a0, rSELF # arg0
8865 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8866 la a2, MterpCheckBefore
8867 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8868
8869/* ------------------------------ */
8870 .balign 128
8871.L_ALT_op_const_class: /* 0x1c */
8872/* File: mips/alt_stub.S */
8873/*
8874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8875 * any interesting requests and then jump to the real instruction
8876 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8877 */
8878 .extern MterpCheckBefore
8879 EXPORT_PC()
8880 la ra, artMterpAsmInstructionStart + (28 * 128) # Addr of primary handler
8881 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8882 move a0, rSELF # arg0
8883 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8884 la a2, MterpCheckBefore
8885 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8886
8887/* ------------------------------ */
8888 .balign 128
8889.L_ALT_op_monitor_enter: /* 0x1d */
8890/* File: mips/alt_stub.S */
8891/*
8892 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8893 * any interesting requests and then jump to the real instruction
8894 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8895 */
8896 .extern MterpCheckBefore
8897 EXPORT_PC()
8898 la ra, artMterpAsmInstructionStart + (29 * 128) # Addr of primary handler
8899 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8900 move a0, rSELF # arg0
8901 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8902 la a2, MterpCheckBefore
8903 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8904
8905/* ------------------------------ */
8906 .balign 128
8907.L_ALT_op_monitor_exit: /* 0x1e */
8908/* File: mips/alt_stub.S */
8909/*
8910 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8911 * any interesting requests and then jump to the real instruction
8912 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8913 */
8914 .extern MterpCheckBefore
8915 EXPORT_PC()
8916 la ra, artMterpAsmInstructionStart + (30 * 128) # Addr of primary handler
8917 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8918 move a0, rSELF # arg0
8919 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8920 la a2, MterpCheckBefore
8921 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8922
8923/* ------------------------------ */
8924 .balign 128
8925.L_ALT_op_check_cast: /* 0x1f */
8926/* File: mips/alt_stub.S */
8927/*
8928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8929 * any interesting requests and then jump to the real instruction
8930 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8931 */
8932 .extern MterpCheckBefore
8933 EXPORT_PC()
8934 la ra, artMterpAsmInstructionStart + (31 * 128) # Addr of primary handler
8935 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8936 move a0, rSELF # arg0
8937 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8938 la a2, MterpCheckBefore
8939 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8940
8941/* ------------------------------ */
8942 .balign 128
8943.L_ALT_op_instance_of: /* 0x20 */
8944/* File: mips/alt_stub.S */
8945/*
8946 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8947 * any interesting requests and then jump to the real instruction
8948 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8949 */
8950 .extern MterpCheckBefore
8951 EXPORT_PC()
8952 la ra, artMterpAsmInstructionStart + (32 * 128) # Addr of primary handler
8953 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8954 move a0, rSELF # arg0
8955 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8956 la a2, MterpCheckBefore
8957 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8958
8959/* ------------------------------ */
8960 .balign 128
8961.L_ALT_op_array_length: /* 0x21 */
8962/* File: mips/alt_stub.S */
8963/*
8964 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8965 * any interesting requests and then jump to the real instruction
8966 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8967 */
8968 .extern MterpCheckBefore
8969 EXPORT_PC()
8970 la ra, artMterpAsmInstructionStart + (33 * 128) # Addr of primary handler
8971 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8972 move a0, rSELF # arg0
8973 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8974 la a2, MterpCheckBefore
8975 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8976
8977/* ------------------------------ */
8978 .balign 128
8979.L_ALT_op_new_instance: /* 0x22 */
8980/* File: mips/alt_stub.S */
8981/*
8982 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8983 * any interesting requests and then jump to the real instruction
8984 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8985 */
8986 .extern MterpCheckBefore
8987 EXPORT_PC()
8988 la ra, artMterpAsmInstructionStart + (34 * 128) # Addr of primary handler
8989 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
8990 move a0, rSELF # arg0
8991 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
8992 la a2, MterpCheckBefore
8993 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
8994
8995/* ------------------------------ */
8996 .balign 128
8997.L_ALT_op_new_array: /* 0x23 */
8998/* File: mips/alt_stub.S */
8999/*
9000 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9001 * any interesting requests and then jump to the real instruction
9002 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9003 */
9004 .extern MterpCheckBefore
9005 EXPORT_PC()
9006 la ra, artMterpAsmInstructionStart + (35 * 128) # Addr of primary handler
9007 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9008 move a0, rSELF # arg0
9009 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9010 la a2, MterpCheckBefore
9011 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9012
9013/* ------------------------------ */
9014 .balign 128
9015.L_ALT_op_filled_new_array: /* 0x24 */
9016/* File: mips/alt_stub.S */
9017/*
9018 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9019 * any interesting requests and then jump to the real instruction
9020 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9021 */
9022 .extern MterpCheckBefore
9023 EXPORT_PC()
9024 la ra, artMterpAsmInstructionStart + (36 * 128) # Addr of primary handler
9025 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9026 move a0, rSELF # arg0
9027 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9028 la a2, MterpCheckBefore
9029 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9030
9031/* ------------------------------ */
9032 .balign 128
9033.L_ALT_op_filled_new_array_range: /* 0x25 */
9034/* File: mips/alt_stub.S */
9035/*
9036 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9037 * any interesting requests and then jump to the real instruction
9038 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9039 */
9040 .extern MterpCheckBefore
9041 EXPORT_PC()
9042 la ra, artMterpAsmInstructionStart + (37 * 128) # Addr of primary handler
9043 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9044 move a0, rSELF # arg0
9045 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9046 la a2, MterpCheckBefore
9047 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9048
9049/* ------------------------------ */
9050 .balign 128
9051.L_ALT_op_fill_array_data: /* 0x26 */
9052/* File: mips/alt_stub.S */
9053/*
9054 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9055 * any interesting requests and then jump to the real instruction
9056 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9057 */
9058 .extern MterpCheckBefore
9059 EXPORT_PC()
9060 la ra, artMterpAsmInstructionStart + (38 * 128) # Addr of primary handler
9061 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9062 move a0, rSELF # arg0
9063 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9064 la a2, MterpCheckBefore
9065 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9066
9067/* ------------------------------ */
9068 .balign 128
9069.L_ALT_op_throw: /* 0x27 */
9070/* File: mips/alt_stub.S */
9071/*
9072 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9073 * any interesting requests and then jump to the real instruction
9074 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9075 */
9076 .extern MterpCheckBefore
9077 EXPORT_PC()
9078 la ra, artMterpAsmInstructionStart + (39 * 128) # Addr of primary handler
9079 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9080 move a0, rSELF # arg0
9081 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9082 la a2, MterpCheckBefore
9083 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9084
9085/* ------------------------------ */
9086 .balign 128
9087.L_ALT_op_goto: /* 0x28 */
9088/* File: mips/alt_stub.S */
9089/*
9090 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9091 * any interesting requests and then jump to the real instruction
9092 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9093 */
9094 .extern MterpCheckBefore
9095 EXPORT_PC()
9096 la ra, artMterpAsmInstructionStart + (40 * 128) # Addr of primary handler
9097 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9098 move a0, rSELF # arg0
9099 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9100 la a2, MterpCheckBefore
9101 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9102
9103/* ------------------------------ */
9104 .balign 128
9105.L_ALT_op_goto_16: /* 0x29 */
9106/* File: mips/alt_stub.S */
9107/*
9108 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9109 * any interesting requests and then jump to the real instruction
9110 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9111 */
9112 .extern MterpCheckBefore
9113 EXPORT_PC()
9114 la ra, artMterpAsmInstructionStart + (41 * 128) # Addr of primary handler
9115 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9116 move a0, rSELF # arg0
9117 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9118 la a2, MterpCheckBefore
9119 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9120
9121/* ------------------------------ */
9122 .balign 128
9123.L_ALT_op_goto_32: /* 0x2a */
9124/* File: mips/alt_stub.S */
9125/*
9126 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9127 * any interesting requests and then jump to the real instruction
9128 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9129 */
9130 .extern MterpCheckBefore
9131 EXPORT_PC()
9132 la ra, artMterpAsmInstructionStart + (42 * 128) # Addr of primary handler
9133 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9134 move a0, rSELF # arg0
9135 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9136 la a2, MterpCheckBefore
9137 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9138
9139/* ------------------------------ */
9140 .balign 128
9141.L_ALT_op_packed_switch: /* 0x2b */
9142/* File: mips/alt_stub.S */
9143/*
9144 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9145 * any interesting requests and then jump to the real instruction
9146 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9147 */
9148 .extern MterpCheckBefore
9149 EXPORT_PC()
9150 la ra, artMterpAsmInstructionStart + (43 * 128) # Addr of primary handler
9151 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9152 move a0, rSELF # arg0
9153 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9154 la a2, MterpCheckBefore
9155 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9156
9157/* ------------------------------ */
9158 .balign 128
9159.L_ALT_op_sparse_switch: /* 0x2c */
9160/* File: mips/alt_stub.S */
9161/*
9162 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9163 * any interesting requests and then jump to the real instruction
9164 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9165 */
9166 .extern MterpCheckBefore
9167 EXPORT_PC()
9168 la ra, artMterpAsmInstructionStart + (44 * 128) # Addr of primary handler
9169 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9170 move a0, rSELF # arg0
9171 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9172 la a2, MterpCheckBefore
9173 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9174
9175/* ------------------------------ */
9176 .balign 128
9177.L_ALT_op_cmpl_float: /* 0x2d */
9178/* File: mips/alt_stub.S */
9179/*
9180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9181 * any interesting requests and then jump to the real instruction
9182 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9183 */
9184 .extern MterpCheckBefore
9185 EXPORT_PC()
9186 la ra, artMterpAsmInstructionStart + (45 * 128) # Addr of primary handler
9187 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9188 move a0, rSELF # arg0
9189 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9190 la a2, MterpCheckBefore
9191 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9192
9193/* ------------------------------ */
9194 .balign 128
9195.L_ALT_op_cmpg_float: /* 0x2e */
9196/* File: mips/alt_stub.S */
9197/*
9198 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9199 * any interesting requests and then jump to the real instruction
9200 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9201 */
9202 .extern MterpCheckBefore
9203 EXPORT_PC()
9204 la ra, artMterpAsmInstructionStart + (46 * 128) # Addr of primary handler
9205 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9206 move a0, rSELF # arg0
9207 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9208 la a2, MterpCheckBefore
9209 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9210
9211/* ------------------------------ */
9212 .balign 128
9213.L_ALT_op_cmpl_double: /* 0x2f */
9214/* File: mips/alt_stub.S */
9215/*
9216 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9217 * any interesting requests and then jump to the real instruction
9218 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9219 */
9220 .extern MterpCheckBefore
9221 EXPORT_PC()
9222 la ra, artMterpAsmInstructionStart + (47 * 128) # Addr of primary handler
9223 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9224 move a0, rSELF # arg0
9225 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9226 la a2, MterpCheckBefore
9227 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9228
9229/* ------------------------------ */
9230 .balign 128
9231.L_ALT_op_cmpg_double: /* 0x30 */
9232/* File: mips/alt_stub.S */
9233/*
9234 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9235 * any interesting requests and then jump to the real instruction
9236 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9237 */
9238 .extern MterpCheckBefore
9239 EXPORT_PC()
9240 la ra, artMterpAsmInstructionStart + (48 * 128) # Addr of primary handler
9241 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9242 move a0, rSELF # arg0
9243 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9244 la a2, MterpCheckBefore
9245 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9246
9247/* ------------------------------ */
9248 .balign 128
9249.L_ALT_op_cmp_long: /* 0x31 */
9250/* File: mips/alt_stub.S */
9251/*
9252 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9253 * any interesting requests and then jump to the real instruction
9254 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9255 */
9256 .extern MterpCheckBefore
9257 EXPORT_PC()
9258 la ra, artMterpAsmInstructionStart + (49 * 128) # Addr of primary handler
9259 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9260 move a0, rSELF # arg0
9261 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9262 la a2, MterpCheckBefore
9263 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9264
9265/* ------------------------------ */
9266 .balign 128
9267.L_ALT_op_if_eq: /* 0x32 */
9268/* File: mips/alt_stub.S */
9269/*
9270 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9271 * any interesting requests and then jump to the real instruction
9272 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9273 */
9274 .extern MterpCheckBefore
9275 EXPORT_PC()
9276 la ra, artMterpAsmInstructionStart + (50 * 128) # Addr of primary handler
9277 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9278 move a0, rSELF # arg0
9279 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9280 la a2, MterpCheckBefore
9281 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9282
9283/* ------------------------------ */
9284 .balign 128
9285.L_ALT_op_if_ne: /* 0x33 */
9286/* File: mips/alt_stub.S */
9287/*
9288 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9289 * any interesting requests and then jump to the real instruction
9290 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9291 */
9292 .extern MterpCheckBefore
9293 EXPORT_PC()
9294 la ra, artMterpAsmInstructionStart + (51 * 128) # Addr of primary handler
9295 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9296 move a0, rSELF # arg0
9297 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9298 la a2, MterpCheckBefore
9299 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9300
9301/* ------------------------------ */
9302 .balign 128
9303.L_ALT_op_if_lt: /* 0x34 */
9304/* File: mips/alt_stub.S */
9305/*
9306 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9307 * any interesting requests and then jump to the real instruction
9308 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9309 */
9310 .extern MterpCheckBefore
9311 EXPORT_PC()
9312 la ra, artMterpAsmInstructionStart + (52 * 128) # Addr of primary handler
9313 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9314 move a0, rSELF # arg0
9315 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9316 la a2, MterpCheckBefore
9317 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9318
9319/* ------------------------------ */
9320 .balign 128
9321.L_ALT_op_if_ge: /* 0x35 */
9322/* File: mips/alt_stub.S */
9323/*
9324 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9325 * any interesting requests and then jump to the real instruction
9326 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9327 */
9328 .extern MterpCheckBefore
9329 EXPORT_PC()
9330 la ra, artMterpAsmInstructionStart + (53 * 128) # Addr of primary handler
9331 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9332 move a0, rSELF # arg0
9333 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9334 la a2, MterpCheckBefore
9335 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9336
9337/* ------------------------------ */
9338 .balign 128
9339.L_ALT_op_if_gt: /* 0x36 */
9340/* File: mips/alt_stub.S */
9341/*
9342 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9343 * any interesting requests and then jump to the real instruction
9344 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9345 */
9346 .extern MterpCheckBefore
9347 EXPORT_PC()
9348 la ra, artMterpAsmInstructionStart + (54 * 128) # Addr of primary handler
9349 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9350 move a0, rSELF # arg0
9351 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9352 la a2, MterpCheckBefore
9353 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9354
9355/* ------------------------------ */
9356 .balign 128
9357.L_ALT_op_if_le: /* 0x37 */
9358/* File: mips/alt_stub.S */
9359/*
9360 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9361 * any interesting requests and then jump to the real instruction
9362 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9363 */
9364 .extern MterpCheckBefore
9365 EXPORT_PC()
9366 la ra, artMterpAsmInstructionStart + (55 * 128) # Addr of primary handler
9367 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9368 move a0, rSELF # arg0
9369 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9370 la a2, MterpCheckBefore
9371 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9372
9373/* ------------------------------ */
9374 .balign 128
9375.L_ALT_op_if_eqz: /* 0x38 */
9376/* File: mips/alt_stub.S */
9377/*
9378 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9379 * any interesting requests and then jump to the real instruction
9380 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9381 */
9382 .extern MterpCheckBefore
9383 EXPORT_PC()
9384 la ra, artMterpAsmInstructionStart + (56 * 128) # Addr of primary handler
9385 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9386 move a0, rSELF # arg0
9387 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9388 la a2, MterpCheckBefore
9389 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9390
9391/* ------------------------------ */
9392 .balign 128
9393.L_ALT_op_if_nez: /* 0x39 */
9394/* File: mips/alt_stub.S */
9395/*
9396 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9397 * any interesting requests and then jump to the real instruction
9398 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9399 */
9400 .extern MterpCheckBefore
9401 EXPORT_PC()
9402 la ra, artMterpAsmInstructionStart + (57 * 128) # Addr of primary handler
9403 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9404 move a0, rSELF # arg0
9405 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9406 la a2, MterpCheckBefore
9407 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9408
9409/* ------------------------------ */
9410 .balign 128
9411.L_ALT_op_if_ltz: /* 0x3a */
9412/* File: mips/alt_stub.S */
9413/*
9414 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9415 * any interesting requests and then jump to the real instruction
9416 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9417 */
9418 .extern MterpCheckBefore
9419 EXPORT_PC()
9420 la ra, artMterpAsmInstructionStart + (58 * 128) # Addr of primary handler
9421 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9422 move a0, rSELF # arg0
9423 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9424 la a2, MterpCheckBefore
9425 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9426
9427/* ------------------------------ */
9428 .balign 128
9429.L_ALT_op_if_gez: /* 0x3b */
9430/* File: mips/alt_stub.S */
9431/*
9432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9433 * any interesting requests and then jump to the real instruction
9434 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9435 */
9436 .extern MterpCheckBefore
9437 EXPORT_PC()
9438 la ra, artMterpAsmInstructionStart + (59 * 128) # Addr of primary handler
9439 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9440 move a0, rSELF # arg0
9441 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9442 la a2, MterpCheckBefore
9443 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9444
9445/* ------------------------------ */
9446 .balign 128
9447.L_ALT_op_if_gtz: /* 0x3c */
9448/* File: mips/alt_stub.S */
9449/*
9450 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9451 * any interesting requests and then jump to the real instruction
9452 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9453 */
9454 .extern MterpCheckBefore
9455 EXPORT_PC()
9456 la ra, artMterpAsmInstructionStart + (60 * 128) # Addr of primary handler
9457 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9458 move a0, rSELF # arg0
9459 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9460 la a2, MterpCheckBefore
9461 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9462
9463/* ------------------------------ */
9464 .balign 128
9465.L_ALT_op_if_lez: /* 0x3d */
9466/* File: mips/alt_stub.S */
9467/*
9468 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9469 * any interesting requests and then jump to the real instruction
9470 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9471 */
9472 .extern MterpCheckBefore
9473 EXPORT_PC()
9474 la ra, artMterpAsmInstructionStart + (61 * 128) # Addr of primary handler
9475 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9476 move a0, rSELF # arg0
9477 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9478 la a2, MterpCheckBefore
9479 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9480
9481/* ------------------------------ */
9482 .balign 128
9483.L_ALT_op_unused_3e: /* 0x3e */
9484/* File: mips/alt_stub.S */
9485/*
9486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9487 * any interesting requests and then jump to the real instruction
9488 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9489 */
9490 .extern MterpCheckBefore
9491 EXPORT_PC()
9492 la ra, artMterpAsmInstructionStart + (62 * 128) # Addr of primary handler
9493 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9494 move a0, rSELF # arg0
9495 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9496 la a2, MterpCheckBefore
9497 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9498
9499/* ------------------------------ */
9500 .balign 128
9501.L_ALT_op_unused_3f: /* 0x3f */
9502/* File: mips/alt_stub.S */
9503/*
9504 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9505 * any interesting requests and then jump to the real instruction
9506 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9507 */
9508 .extern MterpCheckBefore
9509 EXPORT_PC()
9510 la ra, artMterpAsmInstructionStart + (63 * 128) # Addr of primary handler
9511 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9512 move a0, rSELF # arg0
9513 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9514 la a2, MterpCheckBefore
9515 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9516
9517/* ------------------------------ */
9518 .balign 128
9519.L_ALT_op_unused_40: /* 0x40 */
9520/* File: mips/alt_stub.S */
9521/*
9522 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9523 * any interesting requests and then jump to the real instruction
9524 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9525 */
9526 .extern MterpCheckBefore
9527 EXPORT_PC()
9528 la ra, artMterpAsmInstructionStart + (64 * 128) # Addr of primary handler
9529 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9530 move a0, rSELF # arg0
9531 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9532 la a2, MterpCheckBefore
9533 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9534
9535/* ------------------------------ */
9536 .balign 128
9537.L_ALT_op_unused_41: /* 0x41 */
9538/* File: mips/alt_stub.S */
9539/*
9540 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9541 * any interesting requests and then jump to the real instruction
9542 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9543 */
9544 .extern MterpCheckBefore
9545 EXPORT_PC()
9546 la ra, artMterpAsmInstructionStart + (65 * 128) # Addr of primary handler
9547 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9548 move a0, rSELF # arg0
9549 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9550 la a2, MterpCheckBefore
9551 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9552
9553/* ------------------------------ */
9554 .balign 128
9555.L_ALT_op_unused_42: /* 0x42 */
9556/* File: mips/alt_stub.S */
9557/*
9558 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9559 * any interesting requests and then jump to the real instruction
9560 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9561 */
9562 .extern MterpCheckBefore
9563 EXPORT_PC()
9564 la ra, artMterpAsmInstructionStart + (66 * 128) # Addr of primary handler
9565 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9566 move a0, rSELF # arg0
9567 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9568 la a2, MterpCheckBefore
9569 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9570
9571/* ------------------------------ */
9572 .balign 128
9573.L_ALT_op_unused_43: /* 0x43 */
9574/* File: mips/alt_stub.S */
9575/*
9576 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9577 * any interesting requests and then jump to the real instruction
9578 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9579 */
9580 .extern MterpCheckBefore
9581 EXPORT_PC()
9582 la ra, artMterpAsmInstructionStart + (67 * 128) # Addr of primary handler
9583 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9584 move a0, rSELF # arg0
9585 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9586 la a2, MterpCheckBefore
9587 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9588
9589/* ------------------------------ */
9590 .balign 128
9591.L_ALT_op_aget: /* 0x44 */
9592/* File: mips/alt_stub.S */
9593/*
9594 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9595 * any interesting requests and then jump to the real instruction
9596 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9597 */
9598 .extern MterpCheckBefore
9599 EXPORT_PC()
9600 la ra, artMterpAsmInstructionStart + (68 * 128) # Addr of primary handler
9601 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9602 move a0, rSELF # arg0
9603 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9604 la a2, MterpCheckBefore
9605 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9606
9607/* ------------------------------ */
9608 .balign 128
9609.L_ALT_op_aget_wide: /* 0x45 */
9610/* File: mips/alt_stub.S */
9611/*
9612 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9613 * any interesting requests and then jump to the real instruction
9614 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9615 */
9616 .extern MterpCheckBefore
9617 EXPORT_PC()
9618 la ra, artMterpAsmInstructionStart + (69 * 128) # Addr of primary handler
9619 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9620 move a0, rSELF # arg0
9621 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9622 la a2, MterpCheckBefore
9623 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9624
9625/* ------------------------------ */
9626 .balign 128
9627.L_ALT_op_aget_object: /* 0x46 */
9628/* File: mips/alt_stub.S */
9629/*
9630 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9631 * any interesting requests and then jump to the real instruction
9632 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9633 */
9634 .extern MterpCheckBefore
9635 EXPORT_PC()
9636 la ra, artMterpAsmInstructionStart + (70 * 128) # Addr of primary handler
9637 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9638 move a0, rSELF # arg0
9639 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9640 la a2, MterpCheckBefore
9641 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9642
9643/* ------------------------------ */
9644 .balign 128
9645.L_ALT_op_aget_boolean: /* 0x47 */
9646/* File: mips/alt_stub.S */
9647/*
9648 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9649 * any interesting requests and then jump to the real instruction
9650 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9651 */
9652 .extern MterpCheckBefore
9653 EXPORT_PC()
9654 la ra, artMterpAsmInstructionStart + (71 * 128) # Addr of primary handler
9655 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9656 move a0, rSELF # arg0
9657 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9658 la a2, MterpCheckBefore
9659 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9660
9661/* ------------------------------ */
9662 .balign 128
9663.L_ALT_op_aget_byte: /* 0x48 */
9664/* File: mips/alt_stub.S */
9665/*
9666 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9667 * any interesting requests and then jump to the real instruction
9668 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9669 */
9670 .extern MterpCheckBefore
9671 EXPORT_PC()
9672 la ra, artMterpAsmInstructionStart + (72 * 128) # Addr of primary handler
9673 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9674 move a0, rSELF # arg0
9675 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9676 la a2, MterpCheckBefore
9677 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9678
9679/* ------------------------------ */
9680 .balign 128
9681.L_ALT_op_aget_char: /* 0x49 */
9682/* File: mips/alt_stub.S */
9683/*
9684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9685 * any interesting requests and then jump to the real instruction
9686 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9687 */
9688 .extern MterpCheckBefore
9689 EXPORT_PC()
9690 la ra, artMterpAsmInstructionStart + (73 * 128) # Addr of primary handler
9691 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9692 move a0, rSELF # arg0
9693 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9694 la a2, MterpCheckBefore
9695 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9696
9697/* ------------------------------ */
9698 .balign 128
9699.L_ALT_op_aget_short: /* 0x4a */
9700/* File: mips/alt_stub.S */
9701/*
9702 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9703 * any interesting requests and then jump to the real instruction
9704 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9705 */
9706 .extern MterpCheckBefore
9707 EXPORT_PC()
9708 la ra, artMterpAsmInstructionStart + (74 * 128) # Addr of primary handler
9709 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9710 move a0, rSELF # arg0
9711 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9712 la a2, MterpCheckBefore
9713 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9714
9715/* ------------------------------ */
9716 .balign 128
9717.L_ALT_op_aput: /* 0x4b */
9718/* File: mips/alt_stub.S */
9719/*
9720 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9721 * any interesting requests and then jump to the real instruction
9722 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9723 */
9724 .extern MterpCheckBefore
9725 EXPORT_PC()
9726 la ra, artMterpAsmInstructionStart + (75 * 128) # Addr of primary handler
9727 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9728 move a0, rSELF # arg0
9729 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9730 la a2, MterpCheckBefore
9731 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9732
9733/* ------------------------------ */
9734 .balign 128
9735.L_ALT_op_aput_wide: /* 0x4c */
9736/* File: mips/alt_stub.S */
9737/*
9738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9739 * any interesting requests and then jump to the real instruction
9740 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9741 */
9742 .extern MterpCheckBefore
9743 EXPORT_PC()
9744 la ra, artMterpAsmInstructionStart + (76 * 128) # Addr of primary handler
9745 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9746 move a0, rSELF # arg0
9747 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9748 la a2, MterpCheckBefore
9749 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9750
9751/* ------------------------------ */
9752 .balign 128
9753.L_ALT_op_aput_object: /* 0x4d */
9754/* File: mips/alt_stub.S */
9755/*
9756 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9757 * any interesting requests and then jump to the real instruction
9758 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9759 */
9760 .extern MterpCheckBefore
9761 EXPORT_PC()
9762 la ra, artMterpAsmInstructionStart + (77 * 128) # Addr of primary handler
9763 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9764 move a0, rSELF # arg0
9765 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9766 la a2, MterpCheckBefore
9767 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9768
9769/* ------------------------------ */
9770 .balign 128
9771.L_ALT_op_aput_boolean: /* 0x4e */
9772/* File: mips/alt_stub.S */
9773/*
9774 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9775 * any interesting requests and then jump to the real instruction
9776 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9777 */
9778 .extern MterpCheckBefore
9779 EXPORT_PC()
9780 la ra, artMterpAsmInstructionStart + (78 * 128) # Addr of primary handler
9781 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9782 move a0, rSELF # arg0
9783 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9784 la a2, MterpCheckBefore
9785 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9786
9787/* ------------------------------ */
9788 .balign 128
9789.L_ALT_op_aput_byte: /* 0x4f */
9790/* File: mips/alt_stub.S */
9791/*
9792 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9793 * any interesting requests and then jump to the real instruction
9794 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9795 */
9796 .extern MterpCheckBefore
9797 EXPORT_PC()
9798 la ra, artMterpAsmInstructionStart + (79 * 128) # Addr of primary handler
9799 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9800 move a0, rSELF # arg0
9801 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9802 la a2, MterpCheckBefore
9803 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9804
9805/* ------------------------------ */
9806 .balign 128
9807.L_ALT_op_aput_char: /* 0x50 */
9808/* File: mips/alt_stub.S */
9809/*
9810 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9811 * any interesting requests and then jump to the real instruction
9812 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9813 */
9814 .extern MterpCheckBefore
9815 EXPORT_PC()
9816 la ra, artMterpAsmInstructionStart + (80 * 128) # Addr of primary handler
9817 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9818 move a0, rSELF # arg0
9819 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9820 la a2, MterpCheckBefore
9821 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9822
9823/* ------------------------------ */
9824 .balign 128
9825.L_ALT_op_aput_short: /* 0x51 */
9826/* File: mips/alt_stub.S */
9827/*
9828 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9829 * any interesting requests and then jump to the real instruction
9830 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9831 */
9832 .extern MterpCheckBefore
9833 EXPORT_PC()
9834 la ra, artMterpAsmInstructionStart + (81 * 128) # Addr of primary handler
9835 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9836 move a0, rSELF # arg0
9837 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9838 la a2, MterpCheckBefore
9839 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9840
9841/* ------------------------------ */
9842 .balign 128
9843.L_ALT_op_iget: /* 0x52 */
9844/* File: mips/alt_stub.S */
9845/*
9846 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9847 * any interesting requests and then jump to the real instruction
9848 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9849 */
9850 .extern MterpCheckBefore
9851 EXPORT_PC()
9852 la ra, artMterpAsmInstructionStart + (82 * 128) # Addr of primary handler
9853 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9854 move a0, rSELF # arg0
9855 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9856 la a2, MterpCheckBefore
9857 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9858
9859/* ------------------------------ */
9860 .balign 128
9861.L_ALT_op_iget_wide: /* 0x53 */
9862/* File: mips/alt_stub.S */
9863/*
9864 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9865 * any interesting requests and then jump to the real instruction
9866 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9867 */
9868 .extern MterpCheckBefore
9869 EXPORT_PC()
9870 la ra, artMterpAsmInstructionStart + (83 * 128) # Addr of primary handler
9871 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9872 move a0, rSELF # arg0
9873 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9874 la a2, MterpCheckBefore
9875 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9876
9877/* ------------------------------ */
9878 .balign 128
9879.L_ALT_op_iget_object: /* 0x54 */
9880/* File: mips/alt_stub.S */
9881/*
9882 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9883 * any interesting requests and then jump to the real instruction
9884 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9885 */
9886 .extern MterpCheckBefore
9887 EXPORT_PC()
9888 la ra, artMterpAsmInstructionStart + (84 * 128) # Addr of primary handler
9889 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9890 move a0, rSELF # arg0
9891 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9892 la a2, MterpCheckBefore
9893 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9894
9895/* ------------------------------ */
9896 .balign 128
9897.L_ALT_op_iget_boolean: /* 0x55 */
9898/* File: mips/alt_stub.S */
9899/*
9900 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9901 * any interesting requests and then jump to the real instruction
9902 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9903 */
9904 .extern MterpCheckBefore
9905 EXPORT_PC()
9906 la ra, artMterpAsmInstructionStart + (85 * 128) # Addr of primary handler
9907 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9908 move a0, rSELF # arg0
9909 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9910 la a2, MterpCheckBefore
9911 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9912
9913/* ------------------------------ */
9914 .balign 128
9915.L_ALT_op_iget_byte: /* 0x56 */
9916/* File: mips/alt_stub.S */
9917/*
9918 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9919 * any interesting requests and then jump to the real instruction
9920 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9921 */
9922 .extern MterpCheckBefore
9923 EXPORT_PC()
9924 la ra, artMterpAsmInstructionStart + (86 * 128) # Addr of primary handler
9925 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9926 move a0, rSELF # arg0
9927 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9928 la a2, MterpCheckBefore
9929 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9930
9931/* ------------------------------ */
9932 .balign 128
9933.L_ALT_op_iget_char: /* 0x57 */
9934/* File: mips/alt_stub.S */
9935/*
9936 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9937 * any interesting requests and then jump to the real instruction
9938 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9939 */
9940 .extern MterpCheckBefore
9941 EXPORT_PC()
9942 la ra, artMterpAsmInstructionStart + (87 * 128) # Addr of primary handler
9943 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9944 move a0, rSELF # arg0
9945 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9946 la a2, MterpCheckBefore
9947 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9948
9949/* ------------------------------ */
9950 .balign 128
9951.L_ALT_op_iget_short: /* 0x58 */
9952/* File: mips/alt_stub.S */
9953/*
9954 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9955 * any interesting requests and then jump to the real instruction
9956 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9957 */
9958 .extern MterpCheckBefore
9959 EXPORT_PC()
9960 la ra, artMterpAsmInstructionStart + (88 * 128) # Addr of primary handler
9961 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9962 move a0, rSELF # arg0
9963 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9964 la a2, MterpCheckBefore
9965 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9966
9967/* ------------------------------ */
9968 .balign 128
9969.L_ALT_op_iput: /* 0x59 */
9970/* File: mips/alt_stub.S */
9971/*
9972 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9973 * any interesting requests and then jump to the real instruction
9974 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9975 */
9976 .extern MterpCheckBefore
9977 EXPORT_PC()
9978 la ra, artMterpAsmInstructionStart + (89 * 128) # Addr of primary handler
9979 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9980 move a0, rSELF # arg0
9981 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
9982 la a2, MterpCheckBefore
9983 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
9984
9985/* ------------------------------ */
9986 .balign 128
9987.L_ALT_op_iput_wide: /* 0x5a */
9988/* File: mips/alt_stub.S */
9989/*
9990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9991 * any interesting requests and then jump to the real instruction
9992 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9993 */
9994 .extern MterpCheckBefore
9995 EXPORT_PC()
9996 la ra, artMterpAsmInstructionStart + (90 * 128) # Addr of primary handler
9997 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
9998 move a0, rSELF # arg0
9999 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10000 la a2, MterpCheckBefore
10001 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10002
10003/* ------------------------------ */
10004 .balign 128
10005.L_ALT_op_iput_object: /* 0x5b */
10006/* File: mips/alt_stub.S */
10007/*
10008 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10009 * any interesting requests and then jump to the real instruction
10010 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10011 */
10012 .extern MterpCheckBefore
10013 EXPORT_PC()
10014 la ra, artMterpAsmInstructionStart + (91 * 128) # Addr of primary handler
10015 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10016 move a0, rSELF # arg0
10017 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10018 la a2, MterpCheckBefore
10019 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10020
10021/* ------------------------------ */
10022 .balign 128
10023.L_ALT_op_iput_boolean: /* 0x5c */
10024/* File: mips/alt_stub.S */
10025/*
10026 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10027 * any interesting requests and then jump to the real instruction
10028 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10029 */
10030 .extern MterpCheckBefore
10031 EXPORT_PC()
10032 la ra, artMterpAsmInstructionStart + (92 * 128) # Addr of primary handler
10033 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10034 move a0, rSELF # arg0
10035 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10036 la a2, MterpCheckBefore
10037 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10038
10039/* ------------------------------ */
10040 .balign 128
10041.L_ALT_op_iput_byte: /* 0x5d */
10042/* File: mips/alt_stub.S */
10043/*
10044 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10045 * any interesting requests and then jump to the real instruction
10046 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10047 */
10048 .extern MterpCheckBefore
10049 EXPORT_PC()
10050 la ra, artMterpAsmInstructionStart + (93 * 128) # Addr of primary handler
10051 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10052 move a0, rSELF # arg0
10053 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10054 la a2, MterpCheckBefore
10055 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10056
10057/* ------------------------------ */
10058 .balign 128
10059.L_ALT_op_iput_char: /* 0x5e */
10060/* File: mips/alt_stub.S */
10061/*
10062 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10063 * any interesting requests and then jump to the real instruction
10064 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10065 */
10066 .extern MterpCheckBefore
10067 EXPORT_PC()
10068 la ra, artMterpAsmInstructionStart + (94 * 128) # Addr of primary handler
10069 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10070 move a0, rSELF # arg0
10071 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10072 la a2, MterpCheckBefore
10073 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10074
10075/* ------------------------------ */
10076 .balign 128
10077.L_ALT_op_iput_short: /* 0x5f */
10078/* File: mips/alt_stub.S */
10079/*
10080 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10081 * any interesting requests and then jump to the real instruction
10082 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10083 */
10084 .extern MterpCheckBefore
10085 EXPORT_PC()
10086 la ra, artMterpAsmInstructionStart + (95 * 128) # Addr of primary handler
10087 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10088 move a0, rSELF # arg0
10089 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10090 la a2, MterpCheckBefore
10091 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10092
10093/* ------------------------------ */
10094 .balign 128
10095.L_ALT_op_sget: /* 0x60 */
10096/* File: mips/alt_stub.S */
10097/*
10098 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10099 * any interesting requests and then jump to the real instruction
10100 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10101 */
10102 .extern MterpCheckBefore
10103 EXPORT_PC()
10104 la ra, artMterpAsmInstructionStart + (96 * 128) # Addr of primary handler
10105 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10106 move a0, rSELF # arg0
10107 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10108 la a2, MterpCheckBefore
10109 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10110
10111/* ------------------------------ */
10112 .balign 128
10113.L_ALT_op_sget_wide: /* 0x61 */
10114/* File: mips/alt_stub.S */
10115/*
10116 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10117 * any interesting requests and then jump to the real instruction
10118 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10119 */
10120 .extern MterpCheckBefore
10121 EXPORT_PC()
10122 la ra, artMterpAsmInstructionStart + (97 * 128) # Addr of primary handler
10123 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10124 move a0, rSELF # arg0
10125 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10126 la a2, MterpCheckBefore
10127 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10128
10129/* ------------------------------ */
10130 .balign 128
10131.L_ALT_op_sget_object: /* 0x62 */
10132/* File: mips/alt_stub.S */
10133/*
10134 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10135 * any interesting requests and then jump to the real instruction
10136 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10137 */
10138 .extern MterpCheckBefore
10139 EXPORT_PC()
10140 la ra, artMterpAsmInstructionStart + (98 * 128) # Addr of primary handler
10141 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10142 move a0, rSELF # arg0
10143 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10144 la a2, MterpCheckBefore
10145 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10146
10147/* ------------------------------ */
10148 .balign 128
10149.L_ALT_op_sget_boolean: /* 0x63 */
10150/* File: mips/alt_stub.S */
10151/*
10152 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10153 * any interesting requests and then jump to the real instruction
10154 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10155 */
10156 .extern MterpCheckBefore
10157 EXPORT_PC()
10158 la ra, artMterpAsmInstructionStart + (99 * 128) # Addr of primary handler
10159 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10160 move a0, rSELF # arg0
10161 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10162 la a2, MterpCheckBefore
10163 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10164
10165/* ------------------------------ */
10166 .balign 128
10167.L_ALT_op_sget_byte: /* 0x64 */
10168/* File: mips/alt_stub.S */
10169/*
10170 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10171 * any interesting requests and then jump to the real instruction
10172 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10173 */
10174 .extern MterpCheckBefore
10175 EXPORT_PC()
10176 la ra, artMterpAsmInstructionStart + (100 * 128) # Addr of primary handler
10177 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10178 move a0, rSELF # arg0
10179 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10180 la a2, MterpCheckBefore
10181 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10182
10183/* ------------------------------ */
10184 .balign 128
10185.L_ALT_op_sget_char: /* 0x65 */
10186/* File: mips/alt_stub.S */
10187/*
10188 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10189 * any interesting requests and then jump to the real instruction
10190 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10191 */
10192 .extern MterpCheckBefore
10193 EXPORT_PC()
10194 la ra, artMterpAsmInstructionStart + (101 * 128) # Addr of primary handler
10195 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10196 move a0, rSELF # arg0
10197 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10198 la a2, MterpCheckBefore
10199 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10200
10201/* ------------------------------ */
10202 .balign 128
10203.L_ALT_op_sget_short: /* 0x66 */
10204/* File: mips/alt_stub.S */
10205/*
10206 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10207 * any interesting requests and then jump to the real instruction
10208 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10209 */
10210 .extern MterpCheckBefore
10211 EXPORT_PC()
10212 la ra, artMterpAsmInstructionStart + (102 * 128) # Addr of primary handler
10213 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10214 move a0, rSELF # arg0
10215 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10216 la a2, MterpCheckBefore
10217 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10218
10219/* ------------------------------ */
10220 .balign 128
10221.L_ALT_op_sput: /* 0x67 */
10222/* File: mips/alt_stub.S */
10223/*
10224 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10225 * any interesting requests and then jump to the real instruction
10226 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10227 */
10228 .extern MterpCheckBefore
10229 EXPORT_PC()
10230 la ra, artMterpAsmInstructionStart + (103 * 128) # Addr of primary handler
10231 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10232 move a0, rSELF # arg0
10233 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10234 la a2, MterpCheckBefore
10235 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10236
10237/* ------------------------------ */
10238 .balign 128
10239.L_ALT_op_sput_wide: /* 0x68 */
10240/* File: mips/alt_stub.S */
10241/*
10242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10243 * any interesting requests and then jump to the real instruction
10244 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10245 */
10246 .extern MterpCheckBefore
10247 EXPORT_PC()
10248 la ra, artMterpAsmInstructionStart + (104 * 128) # Addr of primary handler
10249 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10250 move a0, rSELF # arg0
10251 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10252 la a2, MterpCheckBefore
10253 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10254
10255/* ------------------------------ */
10256 .balign 128
10257.L_ALT_op_sput_object: /* 0x69 */
10258/* File: mips/alt_stub.S */
10259/*
10260 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10261 * any interesting requests and then jump to the real instruction
10262 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10263 */
10264 .extern MterpCheckBefore
10265 EXPORT_PC()
10266 la ra, artMterpAsmInstructionStart + (105 * 128) # Addr of primary handler
10267 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10268 move a0, rSELF # arg0
10269 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10270 la a2, MterpCheckBefore
10271 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10272
10273/* ------------------------------ */
10274 .balign 128
10275.L_ALT_op_sput_boolean: /* 0x6a */
10276/* File: mips/alt_stub.S */
10277/*
10278 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10279 * any interesting requests and then jump to the real instruction
10280 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10281 */
10282 .extern MterpCheckBefore
10283 EXPORT_PC()
10284 la ra, artMterpAsmInstructionStart + (106 * 128) # Addr of primary handler
10285 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10286 move a0, rSELF # arg0
10287 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10288 la a2, MterpCheckBefore
10289 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10290
10291/* ------------------------------ */
10292 .balign 128
10293.L_ALT_op_sput_byte: /* 0x6b */
10294/* File: mips/alt_stub.S */
10295/*
10296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10297 * any interesting requests and then jump to the real instruction
10298 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10299 */
10300 .extern MterpCheckBefore
10301 EXPORT_PC()
10302 la ra, artMterpAsmInstructionStart + (107 * 128) # Addr of primary handler
10303 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10304 move a0, rSELF # arg0
10305 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10306 la a2, MterpCheckBefore
10307 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10308
10309/* ------------------------------ */
10310 .balign 128
10311.L_ALT_op_sput_char: /* 0x6c */
10312/* File: mips/alt_stub.S */
10313/*
10314 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10315 * any interesting requests and then jump to the real instruction
10316 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10317 */
10318 .extern MterpCheckBefore
10319 EXPORT_PC()
10320 la ra, artMterpAsmInstructionStart + (108 * 128) # Addr of primary handler
10321 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10322 move a0, rSELF # arg0
10323 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10324 la a2, MterpCheckBefore
10325 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10326
10327/* ------------------------------ */
10328 .balign 128
10329.L_ALT_op_sput_short: /* 0x6d */
10330/* File: mips/alt_stub.S */
10331/*
10332 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10333 * any interesting requests and then jump to the real instruction
10334 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10335 */
10336 .extern MterpCheckBefore
10337 EXPORT_PC()
10338 la ra, artMterpAsmInstructionStart + (109 * 128) # Addr of primary handler
10339 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10340 move a0, rSELF # arg0
10341 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10342 la a2, MterpCheckBefore
10343 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10344
10345/* ------------------------------ */
10346 .balign 128
10347.L_ALT_op_invoke_virtual: /* 0x6e */
10348/* File: mips/alt_stub.S */
10349/*
10350 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10351 * any interesting requests and then jump to the real instruction
10352 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10353 */
10354 .extern MterpCheckBefore
10355 EXPORT_PC()
10356 la ra, artMterpAsmInstructionStart + (110 * 128) # Addr of primary handler
10357 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10358 move a0, rSELF # arg0
10359 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10360 la a2, MterpCheckBefore
10361 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10362
10363/* ------------------------------ */
10364 .balign 128
10365.L_ALT_op_invoke_super: /* 0x6f */
10366/* File: mips/alt_stub.S */
10367/*
10368 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10369 * any interesting requests and then jump to the real instruction
10370 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10371 */
10372 .extern MterpCheckBefore
10373 EXPORT_PC()
10374 la ra, artMterpAsmInstructionStart + (111 * 128) # Addr of primary handler
10375 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10376 move a0, rSELF # arg0
10377 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10378 la a2, MterpCheckBefore
10379 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10380
10381/* ------------------------------ */
10382 .balign 128
10383.L_ALT_op_invoke_direct: /* 0x70 */
10384/* File: mips/alt_stub.S */
10385/*
10386 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10387 * any interesting requests and then jump to the real instruction
10388 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10389 */
10390 .extern MterpCheckBefore
10391 EXPORT_PC()
10392 la ra, artMterpAsmInstructionStart + (112 * 128) # Addr of primary handler
10393 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10394 move a0, rSELF # arg0
10395 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10396 la a2, MterpCheckBefore
10397 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10398
10399/* ------------------------------ */
10400 .balign 128
10401.L_ALT_op_invoke_static: /* 0x71 */
10402/* File: mips/alt_stub.S */
10403/*
10404 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10405 * any interesting requests and then jump to the real instruction
10406 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10407 */
10408 .extern MterpCheckBefore
10409 EXPORT_PC()
10410 la ra, artMterpAsmInstructionStart + (113 * 128) # Addr of primary handler
10411 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10412 move a0, rSELF # arg0
10413 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10414 la a2, MterpCheckBefore
10415 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10416
10417/* ------------------------------ */
10418 .balign 128
10419.L_ALT_op_invoke_interface: /* 0x72 */
10420/* File: mips/alt_stub.S */
10421/*
10422 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10423 * any interesting requests and then jump to the real instruction
10424 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10425 */
10426 .extern MterpCheckBefore
10427 EXPORT_PC()
10428 la ra, artMterpAsmInstructionStart + (114 * 128) # Addr of primary handler
10429 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10430 move a0, rSELF # arg0
10431 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10432 la a2, MterpCheckBefore
10433 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10434
10435/* ------------------------------ */
10436 .balign 128
10437.L_ALT_op_return_void_no_barrier: /* 0x73 */
10438/* File: mips/alt_stub.S */
10439/*
10440 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10441 * any interesting requests and then jump to the real instruction
10442 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10443 */
10444 .extern MterpCheckBefore
10445 EXPORT_PC()
10446 la ra, artMterpAsmInstructionStart + (115 * 128) # Addr of primary handler
10447 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10448 move a0, rSELF # arg0
10449 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10450 la a2, MterpCheckBefore
10451 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10452
10453/* ------------------------------ */
10454 .balign 128
10455.L_ALT_op_invoke_virtual_range: /* 0x74 */
10456/* File: mips/alt_stub.S */
10457/*
10458 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10459 * any interesting requests and then jump to the real instruction
10460 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10461 */
10462 .extern MterpCheckBefore
10463 EXPORT_PC()
10464 la ra, artMterpAsmInstructionStart + (116 * 128) # Addr of primary handler
10465 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10466 move a0, rSELF # arg0
10467 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10468 la a2, MterpCheckBefore
10469 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10470
10471/* ------------------------------ */
10472 .balign 128
10473.L_ALT_op_invoke_super_range: /* 0x75 */
10474/* File: mips/alt_stub.S */
10475/*
10476 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10477 * any interesting requests and then jump to the real instruction
10478 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10479 */
10480 .extern MterpCheckBefore
10481 EXPORT_PC()
10482 la ra, artMterpAsmInstructionStart + (117 * 128) # Addr of primary handler
10483 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10484 move a0, rSELF # arg0
10485 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10486 la a2, MterpCheckBefore
10487 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10488
10489/* ------------------------------ */
10490 .balign 128
10491.L_ALT_op_invoke_direct_range: /* 0x76 */
10492/* File: mips/alt_stub.S */
10493/*
10494 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10495 * any interesting requests and then jump to the real instruction
10496 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10497 */
10498 .extern MterpCheckBefore
10499 EXPORT_PC()
10500 la ra, artMterpAsmInstructionStart + (118 * 128) # Addr of primary handler
10501 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10502 move a0, rSELF # arg0
10503 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10504 la a2, MterpCheckBefore
10505 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10506
10507/* ------------------------------ */
10508 .balign 128
10509.L_ALT_op_invoke_static_range: /* 0x77 */
10510/* File: mips/alt_stub.S */
10511/*
10512 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10513 * any interesting requests and then jump to the real instruction
10514 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10515 */
10516 .extern MterpCheckBefore
10517 EXPORT_PC()
10518 la ra, artMterpAsmInstructionStart + (119 * 128) # Addr of primary handler
10519 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10520 move a0, rSELF # arg0
10521 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10522 la a2, MterpCheckBefore
10523 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10524
10525/* ------------------------------ */
10526 .balign 128
10527.L_ALT_op_invoke_interface_range: /* 0x78 */
10528/* File: mips/alt_stub.S */
10529/*
10530 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10531 * any interesting requests and then jump to the real instruction
10532 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10533 */
10534 .extern MterpCheckBefore
10535 EXPORT_PC()
10536 la ra, artMterpAsmInstructionStart + (120 * 128) # Addr of primary handler
10537 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10538 move a0, rSELF # arg0
10539 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10540 la a2, MterpCheckBefore
10541 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10542
10543/* ------------------------------ */
10544 .balign 128
10545.L_ALT_op_unused_79: /* 0x79 */
10546/* File: mips/alt_stub.S */
10547/*
10548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10549 * any interesting requests and then jump to the real instruction
10550 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10551 */
10552 .extern MterpCheckBefore
10553 EXPORT_PC()
10554 la ra, artMterpAsmInstructionStart + (121 * 128) # Addr of primary handler
10555 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10556 move a0, rSELF # arg0
10557 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10558 la a2, MterpCheckBefore
10559 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10560
10561/* ------------------------------ */
10562 .balign 128
10563.L_ALT_op_unused_7a: /* 0x7a */
10564/* File: mips/alt_stub.S */
10565/*
10566 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10567 * any interesting requests and then jump to the real instruction
10568 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10569 */
10570 .extern MterpCheckBefore
10571 EXPORT_PC()
10572 la ra, artMterpAsmInstructionStart + (122 * 128) # Addr of primary handler
10573 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10574 move a0, rSELF # arg0
10575 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10576 la a2, MterpCheckBefore
10577 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10578
10579/* ------------------------------ */
10580 .balign 128
10581.L_ALT_op_neg_int: /* 0x7b */
10582/* File: mips/alt_stub.S */
10583/*
10584 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10585 * any interesting requests and then jump to the real instruction
10586 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10587 */
10588 .extern MterpCheckBefore
10589 EXPORT_PC()
10590 la ra, artMterpAsmInstructionStart + (123 * 128) # Addr of primary handler
10591 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10592 move a0, rSELF # arg0
10593 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10594 la a2, MterpCheckBefore
10595 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10596
10597/* ------------------------------ */
10598 .balign 128
10599.L_ALT_op_not_int: /* 0x7c */
10600/* File: mips/alt_stub.S */
10601/*
10602 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10603 * any interesting requests and then jump to the real instruction
10604 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10605 */
10606 .extern MterpCheckBefore
10607 EXPORT_PC()
10608 la ra, artMterpAsmInstructionStart + (124 * 128) # Addr of primary handler
10609 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10610 move a0, rSELF # arg0
10611 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10612 la a2, MterpCheckBefore
10613 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10614
10615/* ------------------------------ */
10616 .balign 128
10617.L_ALT_op_neg_long: /* 0x7d */
10618/* File: mips/alt_stub.S */
10619/*
10620 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10621 * any interesting requests and then jump to the real instruction
10622 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10623 */
10624 .extern MterpCheckBefore
10625 EXPORT_PC()
10626 la ra, artMterpAsmInstructionStart + (125 * 128) # Addr of primary handler
10627 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10628 move a0, rSELF # arg0
10629 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10630 la a2, MterpCheckBefore
10631 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10632
10633/* ------------------------------ */
10634 .balign 128
10635.L_ALT_op_not_long: /* 0x7e */
10636/* File: mips/alt_stub.S */
10637/*
10638 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10639 * any interesting requests and then jump to the real instruction
10640 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10641 */
10642 .extern MterpCheckBefore
10643 EXPORT_PC()
10644 la ra, artMterpAsmInstructionStart + (126 * 128) # Addr of primary handler
10645 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10646 move a0, rSELF # arg0
10647 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10648 la a2, MterpCheckBefore
10649 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10650
10651/* ------------------------------ */
10652 .balign 128
10653.L_ALT_op_neg_float: /* 0x7f */
10654/* File: mips/alt_stub.S */
10655/*
10656 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10657 * any interesting requests and then jump to the real instruction
10658 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10659 */
10660 .extern MterpCheckBefore
10661 EXPORT_PC()
10662 la ra, artMterpAsmInstructionStart + (127 * 128) # Addr of primary handler
10663 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10664 move a0, rSELF # arg0
10665 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10666 la a2, MterpCheckBefore
10667 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10668
10669/* ------------------------------ */
10670 .balign 128
10671.L_ALT_op_neg_double: /* 0x80 */
10672/* File: mips/alt_stub.S */
10673/*
10674 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10675 * any interesting requests and then jump to the real instruction
10676 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10677 */
10678 .extern MterpCheckBefore
10679 EXPORT_PC()
10680 la ra, artMterpAsmInstructionStart + (128 * 128) # Addr of primary handler
10681 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10682 move a0, rSELF # arg0
10683 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10684 la a2, MterpCheckBefore
10685 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10686
10687/* ------------------------------ */
10688 .balign 128
10689.L_ALT_op_int_to_long: /* 0x81 */
10690/* File: mips/alt_stub.S */
10691/*
10692 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10693 * any interesting requests and then jump to the real instruction
10694 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10695 */
10696 .extern MterpCheckBefore
10697 EXPORT_PC()
10698 la ra, artMterpAsmInstructionStart + (129 * 128) # Addr of primary handler
10699 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10700 move a0, rSELF # arg0
10701 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10702 la a2, MterpCheckBefore
10703 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10704
10705/* ------------------------------ */
10706 .balign 128
10707.L_ALT_op_int_to_float: /* 0x82 */
10708/* File: mips/alt_stub.S */
10709/*
10710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10711 * any interesting requests and then jump to the real instruction
10712 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10713 */
10714 .extern MterpCheckBefore
10715 EXPORT_PC()
10716 la ra, artMterpAsmInstructionStart + (130 * 128) # Addr of primary handler
10717 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10718 move a0, rSELF # arg0
10719 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10720 la a2, MterpCheckBefore
10721 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10722
10723/* ------------------------------ */
10724 .balign 128
10725.L_ALT_op_int_to_double: /* 0x83 */
10726/* File: mips/alt_stub.S */
10727/*
10728 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10729 * any interesting requests and then jump to the real instruction
10730 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10731 */
10732 .extern MterpCheckBefore
10733 EXPORT_PC()
10734 la ra, artMterpAsmInstructionStart + (131 * 128) # Addr of primary handler
10735 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10736 move a0, rSELF # arg0
10737 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10738 la a2, MterpCheckBefore
10739 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10740
10741/* ------------------------------ */
10742 .balign 128
10743.L_ALT_op_long_to_int: /* 0x84 */
10744/* File: mips/alt_stub.S */
10745/*
10746 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10747 * any interesting requests and then jump to the real instruction
10748 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10749 */
10750 .extern MterpCheckBefore
10751 EXPORT_PC()
10752 la ra, artMterpAsmInstructionStart + (132 * 128) # Addr of primary handler
10753 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10754 move a0, rSELF # arg0
10755 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10756 la a2, MterpCheckBefore
10757 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10758
10759/* ------------------------------ */
10760 .balign 128
10761.L_ALT_op_long_to_float: /* 0x85 */
10762/* File: mips/alt_stub.S */
10763/*
10764 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10765 * any interesting requests and then jump to the real instruction
10766 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10767 */
10768 .extern MterpCheckBefore
10769 EXPORT_PC()
10770 la ra, artMterpAsmInstructionStart + (133 * 128) # Addr of primary handler
10771 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10772 move a0, rSELF # arg0
10773 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10774 la a2, MterpCheckBefore
10775 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10776
10777/* ------------------------------ */
10778 .balign 128
10779.L_ALT_op_long_to_double: /* 0x86 */
10780/* File: mips/alt_stub.S */
10781/*
10782 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10783 * any interesting requests and then jump to the real instruction
10784 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10785 */
10786 .extern MterpCheckBefore
10787 EXPORT_PC()
10788 la ra, artMterpAsmInstructionStart + (134 * 128) # Addr of primary handler
10789 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10790 move a0, rSELF # arg0
10791 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10792 la a2, MterpCheckBefore
10793 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10794
10795/* ------------------------------ */
10796 .balign 128
10797.L_ALT_op_float_to_int: /* 0x87 */
10798/* File: mips/alt_stub.S */
10799/*
10800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10801 * any interesting requests and then jump to the real instruction
10802 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10803 */
10804 .extern MterpCheckBefore
10805 EXPORT_PC()
10806 la ra, artMterpAsmInstructionStart + (135 * 128) # Addr of primary handler
10807 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10808 move a0, rSELF # arg0
10809 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10810 la a2, MterpCheckBefore
10811 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10812
10813/* ------------------------------ */
10814 .balign 128
10815.L_ALT_op_float_to_long: /* 0x88 */
10816/* File: mips/alt_stub.S */
10817/*
10818 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10819 * any interesting requests and then jump to the real instruction
10820 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10821 */
10822 .extern MterpCheckBefore
10823 EXPORT_PC()
10824 la ra, artMterpAsmInstructionStart + (136 * 128) # Addr of primary handler
10825 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10826 move a0, rSELF # arg0
10827 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10828 la a2, MterpCheckBefore
10829 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10830
10831/* ------------------------------ */
10832 .balign 128
10833.L_ALT_op_float_to_double: /* 0x89 */
10834/* File: mips/alt_stub.S */
10835/*
10836 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10837 * any interesting requests and then jump to the real instruction
10838 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10839 */
10840 .extern MterpCheckBefore
10841 EXPORT_PC()
10842 la ra, artMterpAsmInstructionStart + (137 * 128) # Addr of primary handler
10843 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10844 move a0, rSELF # arg0
10845 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10846 la a2, MterpCheckBefore
10847 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10848
10849/* ------------------------------ */
10850 .balign 128
10851.L_ALT_op_double_to_int: /* 0x8a */
10852/* File: mips/alt_stub.S */
10853/*
10854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10855 * any interesting requests and then jump to the real instruction
10856 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10857 */
10858 .extern MterpCheckBefore
10859 EXPORT_PC()
10860 la ra, artMterpAsmInstructionStart + (138 * 128) # Addr of primary handler
10861 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10862 move a0, rSELF # arg0
10863 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10864 la a2, MterpCheckBefore
10865 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10866
10867/* ------------------------------ */
10868 .balign 128
10869.L_ALT_op_double_to_long: /* 0x8b */
10870/* File: mips/alt_stub.S */
10871/*
10872 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10873 * any interesting requests and then jump to the real instruction
10874 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10875 */
10876 .extern MterpCheckBefore
10877 EXPORT_PC()
10878 la ra, artMterpAsmInstructionStart + (139 * 128) # Addr of primary handler
10879 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10880 move a0, rSELF # arg0
10881 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10882 la a2, MterpCheckBefore
10883 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10884
10885/* ------------------------------ */
10886 .balign 128
10887.L_ALT_op_double_to_float: /* 0x8c */
10888/* File: mips/alt_stub.S */
10889/*
10890 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10891 * any interesting requests and then jump to the real instruction
10892 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10893 */
10894 .extern MterpCheckBefore
10895 EXPORT_PC()
10896 la ra, artMterpAsmInstructionStart + (140 * 128) # Addr of primary handler
10897 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10898 move a0, rSELF # arg0
10899 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10900 la a2, MterpCheckBefore
10901 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10902
10903/* ------------------------------ */
10904 .balign 128
10905.L_ALT_op_int_to_byte: /* 0x8d */
10906/* File: mips/alt_stub.S */
10907/*
10908 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10909 * any interesting requests and then jump to the real instruction
10910 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10911 */
10912 .extern MterpCheckBefore
10913 EXPORT_PC()
10914 la ra, artMterpAsmInstructionStart + (141 * 128) # Addr of primary handler
10915 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10916 move a0, rSELF # arg0
10917 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10918 la a2, MterpCheckBefore
10919 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10920
10921/* ------------------------------ */
10922 .balign 128
10923.L_ALT_op_int_to_char: /* 0x8e */
10924/* File: mips/alt_stub.S */
10925/*
10926 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10927 * any interesting requests and then jump to the real instruction
10928 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10929 */
10930 .extern MterpCheckBefore
10931 EXPORT_PC()
10932 la ra, artMterpAsmInstructionStart + (142 * 128) # Addr of primary handler
10933 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10934 move a0, rSELF # arg0
10935 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10936 la a2, MterpCheckBefore
10937 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10938
10939/* ------------------------------ */
10940 .balign 128
10941.L_ALT_op_int_to_short: /* 0x8f */
10942/* File: mips/alt_stub.S */
10943/*
10944 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10945 * any interesting requests and then jump to the real instruction
10946 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10947 */
10948 .extern MterpCheckBefore
10949 EXPORT_PC()
10950 la ra, artMterpAsmInstructionStart + (143 * 128) # Addr of primary handler
10951 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10952 move a0, rSELF # arg0
10953 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10954 la a2, MterpCheckBefore
10955 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10956
10957/* ------------------------------ */
10958 .balign 128
10959.L_ALT_op_add_int: /* 0x90 */
10960/* File: mips/alt_stub.S */
10961/*
10962 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10963 * any interesting requests and then jump to the real instruction
10964 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10965 */
10966 .extern MterpCheckBefore
10967 EXPORT_PC()
10968 la ra, artMterpAsmInstructionStart + (144 * 128) # Addr of primary handler
10969 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10970 move a0, rSELF # arg0
10971 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10972 la a2, MterpCheckBefore
10973 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10974
10975/* ------------------------------ */
10976 .balign 128
10977.L_ALT_op_sub_int: /* 0x91 */
10978/* File: mips/alt_stub.S */
10979/*
10980 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10981 * any interesting requests and then jump to the real instruction
10982 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10983 */
10984 .extern MterpCheckBefore
10985 EXPORT_PC()
10986 la ra, artMterpAsmInstructionStart + (145 * 128) # Addr of primary handler
10987 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
10988 move a0, rSELF # arg0
10989 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
10990 la a2, MterpCheckBefore
10991 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
10992
10993/* ------------------------------ */
10994 .balign 128
10995.L_ALT_op_mul_int: /* 0x92 */
10996/* File: mips/alt_stub.S */
10997/*
10998 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10999 * any interesting requests and then jump to the real instruction
11000 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11001 */
11002 .extern MterpCheckBefore
11003 EXPORT_PC()
11004 la ra, artMterpAsmInstructionStart + (146 * 128) # Addr of primary handler
11005 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11006 move a0, rSELF # arg0
11007 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11008 la a2, MterpCheckBefore
11009 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11010
11011/* ------------------------------ */
11012 .balign 128
11013.L_ALT_op_div_int: /* 0x93 */
11014/* File: mips/alt_stub.S */
11015/*
11016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11017 * any interesting requests and then jump to the real instruction
11018 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11019 */
11020 .extern MterpCheckBefore
11021 EXPORT_PC()
11022 la ra, artMterpAsmInstructionStart + (147 * 128) # Addr of primary handler
11023 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11024 move a0, rSELF # arg0
11025 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11026 la a2, MterpCheckBefore
11027 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11028
11029/* ------------------------------ */
11030 .balign 128
11031.L_ALT_op_rem_int: /* 0x94 */
11032/* File: mips/alt_stub.S */
11033/*
11034 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11035 * any interesting requests and then jump to the real instruction
11036 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11037 */
11038 .extern MterpCheckBefore
11039 EXPORT_PC()
11040 la ra, artMterpAsmInstructionStart + (148 * 128) # Addr of primary handler
11041 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11042 move a0, rSELF # arg0
11043 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11044 la a2, MterpCheckBefore
11045 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11046
11047/* ------------------------------ */
11048 .balign 128
11049.L_ALT_op_and_int: /* 0x95 */
11050/* File: mips/alt_stub.S */
11051/*
11052 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11053 * any interesting requests and then jump to the real instruction
11054 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11055 */
11056 .extern MterpCheckBefore
11057 EXPORT_PC()
11058 la ra, artMterpAsmInstructionStart + (149 * 128) # Addr of primary handler
11059 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11060 move a0, rSELF # arg0
11061 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11062 la a2, MterpCheckBefore
11063 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11064
11065/* ------------------------------ */
11066 .balign 128
11067.L_ALT_op_or_int: /* 0x96 */
11068/* File: mips/alt_stub.S */
11069/*
11070 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11071 * any interesting requests and then jump to the real instruction
11072 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11073 */
11074 .extern MterpCheckBefore
11075 EXPORT_PC()
11076 la ra, artMterpAsmInstructionStart + (150 * 128) # Addr of primary handler
11077 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11078 move a0, rSELF # arg0
11079 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11080 la a2, MterpCheckBefore
11081 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11082
11083/* ------------------------------ */
11084 .balign 128
11085.L_ALT_op_xor_int: /* 0x97 */
11086/* File: mips/alt_stub.S */
11087/*
11088 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11089 * any interesting requests and then jump to the real instruction
11090 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11091 */
11092 .extern MterpCheckBefore
11093 EXPORT_PC()
11094 la ra, artMterpAsmInstructionStart + (151 * 128) # Addr of primary handler
11095 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11096 move a0, rSELF # arg0
11097 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11098 la a2, MterpCheckBefore
11099 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11100
11101/* ------------------------------ */
11102 .balign 128
11103.L_ALT_op_shl_int: /* 0x98 */
11104/* File: mips/alt_stub.S */
11105/*
11106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11107 * any interesting requests and then jump to the real instruction
11108 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11109 */
11110 .extern MterpCheckBefore
11111 EXPORT_PC()
11112 la ra, artMterpAsmInstructionStart + (152 * 128) # Addr of primary handler
11113 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11114 move a0, rSELF # arg0
11115 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11116 la a2, MterpCheckBefore
11117 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11118
11119/* ------------------------------ */
11120 .balign 128
11121.L_ALT_op_shr_int: /* 0x99 */
11122/* File: mips/alt_stub.S */
11123/*
11124 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11125 * any interesting requests and then jump to the real instruction
11126 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11127 */
11128 .extern MterpCheckBefore
11129 EXPORT_PC()
11130 la ra, artMterpAsmInstructionStart + (153 * 128) # Addr of primary handler
11131 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11132 move a0, rSELF # arg0
11133 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11134 la a2, MterpCheckBefore
11135 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11136
11137/* ------------------------------ */
11138 .balign 128
11139.L_ALT_op_ushr_int: /* 0x9a */
11140/* File: mips/alt_stub.S */
11141/*
11142 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11143 * any interesting requests and then jump to the real instruction
11144 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11145 */
11146 .extern MterpCheckBefore
11147 EXPORT_PC()
11148 la ra, artMterpAsmInstructionStart + (154 * 128) # Addr of primary handler
11149 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11150 move a0, rSELF # arg0
11151 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11152 la a2, MterpCheckBefore
11153 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11154
11155/* ------------------------------ */
11156 .balign 128
11157.L_ALT_op_add_long: /* 0x9b */
11158/* File: mips/alt_stub.S */
11159/*
11160 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11161 * any interesting requests and then jump to the real instruction
11162 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11163 */
11164 .extern MterpCheckBefore
11165 EXPORT_PC()
11166 la ra, artMterpAsmInstructionStart + (155 * 128) # Addr of primary handler
11167 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11168 move a0, rSELF # arg0
11169 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11170 la a2, MterpCheckBefore
11171 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11172
11173/* ------------------------------ */
11174 .balign 128
11175.L_ALT_op_sub_long: /* 0x9c */
11176/* File: mips/alt_stub.S */
11177/*
11178 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11179 * any interesting requests and then jump to the real instruction
11180 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11181 */
11182 .extern MterpCheckBefore
11183 EXPORT_PC()
11184 la ra, artMterpAsmInstructionStart + (156 * 128) # Addr of primary handler
11185 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11186 move a0, rSELF # arg0
11187 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11188 la a2, MterpCheckBefore
11189 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11190
11191/* ------------------------------ */
11192 .balign 128
11193.L_ALT_op_mul_long: /* 0x9d */
11194/* File: mips/alt_stub.S */
11195/*
11196 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11197 * any interesting requests and then jump to the real instruction
11198 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11199 */
11200 .extern MterpCheckBefore
11201 EXPORT_PC()
11202 la ra, artMterpAsmInstructionStart + (157 * 128) # Addr of primary handler
11203 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11204 move a0, rSELF # arg0
11205 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11206 la a2, MterpCheckBefore
11207 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11208
11209/* ------------------------------ */
11210 .balign 128
11211.L_ALT_op_div_long: /* 0x9e */
11212/* File: mips/alt_stub.S */
11213/*
11214 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11215 * any interesting requests and then jump to the real instruction
11216 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11217 */
11218 .extern MterpCheckBefore
11219 EXPORT_PC()
11220 la ra, artMterpAsmInstructionStart + (158 * 128) # Addr of primary handler
11221 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11222 move a0, rSELF # arg0
11223 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11224 la a2, MterpCheckBefore
11225 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11226
11227/* ------------------------------ */
11228 .balign 128
11229.L_ALT_op_rem_long: /* 0x9f */
11230/* File: mips/alt_stub.S */
11231/*
11232 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11233 * any interesting requests and then jump to the real instruction
11234 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11235 */
11236 .extern MterpCheckBefore
11237 EXPORT_PC()
11238 la ra, artMterpAsmInstructionStart + (159 * 128) # Addr of primary handler
11239 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11240 move a0, rSELF # arg0
11241 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11242 la a2, MterpCheckBefore
11243 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11244
11245/* ------------------------------ */
11246 .balign 128
11247.L_ALT_op_and_long: /* 0xa0 */
11248/* File: mips/alt_stub.S */
11249/*
11250 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11251 * any interesting requests and then jump to the real instruction
11252 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11253 */
11254 .extern MterpCheckBefore
11255 EXPORT_PC()
11256 la ra, artMterpAsmInstructionStart + (160 * 128) # Addr of primary handler
11257 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11258 move a0, rSELF # arg0
11259 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11260 la a2, MterpCheckBefore
11261 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11262
11263/* ------------------------------ */
11264 .balign 128
11265.L_ALT_op_or_long: /* 0xa1 */
11266/* File: mips/alt_stub.S */
11267/*
11268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11269 * any interesting requests and then jump to the real instruction
11270 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11271 */
11272 .extern MterpCheckBefore
11273 EXPORT_PC()
11274 la ra, artMterpAsmInstructionStart + (161 * 128) # Addr of primary handler
11275 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11276 move a0, rSELF # arg0
11277 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11278 la a2, MterpCheckBefore
11279 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11280
11281/* ------------------------------ */
11282 .balign 128
11283.L_ALT_op_xor_long: /* 0xa2 */
11284/* File: mips/alt_stub.S */
11285/*
11286 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11287 * any interesting requests and then jump to the real instruction
11288 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11289 */
11290 .extern MterpCheckBefore
11291 EXPORT_PC()
11292 la ra, artMterpAsmInstructionStart + (162 * 128) # Addr of primary handler
11293 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11294 move a0, rSELF # arg0
11295 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11296 la a2, MterpCheckBefore
11297 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11298
11299/* ------------------------------ */
11300 .balign 128
11301.L_ALT_op_shl_long: /* 0xa3 */
11302/* File: mips/alt_stub.S */
11303/*
11304 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11305 * any interesting requests and then jump to the real instruction
11306 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11307 */
11308 .extern MterpCheckBefore
11309 EXPORT_PC()
11310 la ra, artMterpAsmInstructionStart + (163 * 128) # Addr of primary handler
11311 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11312 move a0, rSELF # arg0
11313 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11314 la a2, MterpCheckBefore
11315 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11316
11317/* ------------------------------ */
11318 .balign 128
11319.L_ALT_op_shr_long: /* 0xa4 */
11320/* File: mips/alt_stub.S */
11321/*
11322 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11323 * any interesting requests and then jump to the real instruction
11324 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11325 */
11326 .extern MterpCheckBefore
11327 EXPORT_PC()
11328 la ra, artMterpAsmInstructionStart + (164 * 128) # Addr of primary handler
11329 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11330 move a0, rSELF # arg0
11331 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11332 la a2, MterpCheckBefore
11333 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11334
11335/* ------------------------------ */
11336 .balign 128
11337.L_ALT_op_ushr_long: /* 0xa5 */
11338/* File: mips/alt_stub.S */
11339/*
11340 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11341 * any interesting requests and then jump to the real instruction
11342 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11343 */
11344 .extern MterpCheckBefore
11345 EXPORT_PC()
11346 la ra, artMterpAsmInstructionStart + (165 * 128) # Addr of primary handler
11347 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11348 move a0, rSELF # arg0
11349 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11350 la a2, MterpCheckBefore
11351 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11352
11353/* ------------------------------ */
11354 .balign 128
11355.L_ALT_op_add_float: /* 0xa6 */
11356/* File: mips/alt_stub.S */
11357/*
11358 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11359 * any interesting requests and then jump to the real instruction
11360 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11361 */
11362 .extern MterpCheckBefore
11363 EXPORT_PC()
11364 la ra, artMterpAsmInstructionStart + (166 * 128) # Addr of primary handler
11365 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11366 move a0, rSELF # arg0
11367 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11368 la a2, MterpCheckBefore
11369 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11370
11371/* ------------------------------ */
11372 .balign 128
11373.L_ALT_op_sub_float: /* 0xa7 */
11374/* File: mips/alt_stub.S */
11375/*
11376 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11377 * any interesting requests and then jump to the real instruction
11378 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11379 */
11380 .extern MterpCheckBefore
11381 EXPORT_PC()
11382 la ra, artMterpAsmInstructionStart + (167 * 128) # Addr of primary handler
11383 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11384 move a0, rSELF # arg0
11385 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11386 la a2, MterpCheckBefore
11387 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11388
11389/* ------------------------------ */
11390 .balign 128
11391.L_ALT_op_mul_float: /* 0xa8 */
11392/* File: mips/alt_stub.S */
11393/*
11394 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11395 * any interesting requests and then jump to the real instruction
11396 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11397 */
11398 .extern MterpCheckBefore
11399 EXPORT_PC()
11400 la ra, artMterpAsmInstructionStart + (168 * 128) # Addr of primary handler
11401 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11402 move a0, rSELF # arg0
11403 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11404 la a2, MterpCheckBefore
11405 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11406
11407/* ------------------------------ */
11408 .balign 128
11409.L_ALT_op_div_float: /* 0xa9 */
11410/* File: mips/alt_stub.S */
11411/*
11412 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11413 * any interesting requests and then jump to the real instruction
11414 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11415 */
11416 .extern MterpCheckBefore
11417 EXPORT_PC()
11418 la ra, artMterpAsmInstructionStart + (169 * 128) # Addr of primary handler
11419 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11420 move a0, rSELF # arg0
11421 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11422 la a2, MterpCheckBefore
11423 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11424
11425/* ------------------------------ */
11426 .balign 128
11427.L_ALT_op_rem_float: /* 0xaa */
11428/* File: mips/alt_stub.S */
11429/*
11430 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11431 * any interesting requests and then jump to the real instruction
11432 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11433 */
11434 .extern MterpCheckBefore
11435 EXPORT_PC()
11436 la ra, artMterpAsmInstructionStart + (170 * 128) # Addr of primary handler
11437 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11438 move a0, rSELF # arg0
11439 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11440 la a2, MterpCheckBefore
11441 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11442
11443/* ------------------------------ */
11444 .balign 128
11445.L_ALT_op_add_double: /* 0xab */
11446/* File: mips/alt_stub.S */
11447/*
11448 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11449 * any interesting requests and then jump to the real instruction
11450 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11451 */
11452 .extern MterpCheckBefore
11453 EXPORT_PC()
11454 la ra, artMterpAsmInstructionStart + (171 * 128) # Addr of primary handler
11455 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11456 move a0, rSELF # arg0
11457 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11458 la a2, MterpCheckBefore
11459 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11460
11461/* ------------------------------ */
11462 .balign 128
11463.L_ALT_op_sub_double: /* 0xac */
11464/* File: mips/alt_stub.S */
11465/*
11466 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11467 * any interesting requests and then jump to the real instruction
11468 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11469 */
11470 .extern MterpCheckBefore
11471 EXPORT_PC()
11472 la ra, artMterpAsmInstructionStart + (172 * 128) # Addr of primary handler
11473 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11474 move a0, rSELF # arg0
11475 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11476 la a2, MterpCheckBefore
11477 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11478
11479/* ------------------------------ */
11480 .balign 128
11481.L_ALT_op_mul_double: /* 0xad */
11482/* File: mips/alt_stub.S */
11483/*
11484 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11485 * any interesting requests and then jump to the real instruction
11486 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11487 */
11488 .extern MterpCheckBefore
11489 EXPORT_PC()
11490 la ra, artMterpAsmInstructionStart + (173 * 128) # Addr of primary handler
11491 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11492 move a0, rSELF # arg0
11493 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11494 la a2, MterpCheckBefore
11495 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11496
11497/* ------------------------------ */
11498 .balign 128
11499.L_ALT_op_div_double: /* 0xae */
11500/* File: mips/alt_stub.S */
11501/*
11502 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11503 * any interesting requests and then jump to the real instruction
11504 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11505 */
11506 .extern MterpCheckBefore
11507 EXPORT_PC()
11508 la ra, artMterpAsmInstructionStart + (174 * 128) # Addr of primary handler
11509 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11510 move a0, rSELF # arg0
11511 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11512 la a2, MterpCheckBefore
11513 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11514
11515/* ------------------------------ */
11516 .balign 128
11517.L_ALT_op_rem_double: /* 0xaf */
11518/* File: mips/alt_stub.S */
11519/*
11520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11521 * any interesting requests and then jump to the real instruction
11522 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11523 */
11524 .extern MterpCheckBefore
11525 EXPORT_PC()
11526 la ra, artMterpAsmInstructionStart + (175 * 128) # Addr of primary handler
11527 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11528 move a0, rSELF # arg0
11529 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11530 la a2, MterpCheckBefore
11531 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11532
11533/* ------------------------------ */
11534 .balign 128
11535.L_ALT_op_add_int_2addr: /* 0xb0 */
11536/* File: mips/alt_stub.S */
11537/*
11538 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11539 * any interesting requests and then jump to the real instruction
11540 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11541 */
11542 .extern MterpCheckBefore
11543 EXPORT_PC()
11544 la ra, artMterpAsmInstructionStart + (176 * 128) # Addr of primary handler
11545 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11546 move a0, rSELF # arg0
11547 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11548 la a2, MterpCheckBefore
11549 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11550
11551/* ------------------------------ */
11552 .balign 128
11553.L_ALT_op_sub_int_2addr: /* 0xb1 */
11554/* File: mips/alt_stub.S */
11555/*
11556 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11557 * any interesting requests and then jump to the real instruction
11558 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11559 */
11560 .extern MterpCheckBefore
11561 EXPORT_PC()
11562 la ra, artMterpAsmInstructionStart + (177 * 128) # Addr of primary handler
11563 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11564 move a0, rSELF # arg0
11565 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11566 la a2, MterpCheckBefore
11567 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11568
11569/* ------------------------------ */
11570 .balign 128
11571.L_ALT_op_mul_int_2addr: /* 0xb2 */
11572/* File: mips/alt_stub.S */
11573/*
11574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11575 * any interesting requests and then jump to the real instruction
11576 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11577 */
11578 .extern MterpCheckBefore
11579 EXPORT_PC()
11580 la ra, artMterpAsmInstructionStart + (178 * 128) # Addr of primary handler
11581 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11582 move a0, rSELF # arg0
11583 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11584 la a2, MterpCheckBefore
11585 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11586
11587/* ------------------------------ */
11588 .balign 128
11589.L_ALT_op_div_int_2addr: /* 0xb3 */
11590/* File: mips/alt_stub.S */
11591/*
11592 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11593 * any interesting requests and then jump to the real instruction
11594 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11595 */
11596 .extern MterpCheckBefore
11597 EXPORT_PC()
11598 la ra, artMterpAsmInstructionStart + (179 * 128) # Addr of primary handler
11599 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11600 move a0, rSELF # arg0
11601 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11602 la a2, MterpCheckBefore
11603 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11604
11605/* ------------------------------ */
11606 .balign 128
11607.L_ALT_op_rem_int_2addr: /* 0xb4 */
11608/* File: mips/alt_stub.S */
11609/*
11610 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11611 * any interesting requests and then jump to the real instruction
11612 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11613 */
11614 .extern MterpCheckBefore
11615 EXPORT_PC()
11616 la ra, artMterpAsmInstructionStart + (180 * 128) # Addr of primary handler
11617 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11618 move a0, rSELF # arg0
11619 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11620 la a2, MterpCheckBefore
11621 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11622
11623/* ------------------------------ */
11624 .balign 128
11625.L_ALT_op_and_int_2addr: /* 0xb5 */
11626/* File: mips/alt_stub.S */
11627/*
11628 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11629 * any interesting requests and then jump to the real instruction
11630 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11631 */
11632 .extern MterpCheckBefore
11633 EXPORT_PC()
11634 la ra, artMterpAsmInstructionStart + (181 * 128) # Addr of primary handler
11635 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11636 move a0, rSELF # arg0
11637 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11638 la a2, MterpCheckBefore
11639 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11640
11641/* ------------------------------ */
11642 .balign 128
11643.L_ALT_op_or_int_2addr: /* 0xb6 */
11644/* File: mips/alt_stub.S */
11645/*
11646 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11647 * any interesting requests and then jump to the real instruction
11648 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11649 */
11650 .extern MterpCheckBefore
11651 EXPORT_PC()
11652 la ra, artMterpAsmInstructionStart + (182 * 128) # Addr of primary handler
11653 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11654 move a0, rSELF # arg0
11655 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11656 la a2, MterpCheckBefore
11657 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11658
11659/* ------------------------------ */
11660 .balign 128
11661.L_ALT_op_xor_int_2addr: /* 0xb7 */
11662/* File: mips/alt_stub.S */
11663/*
11664 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11665 * any interesting requests and then jump to the real instruction
11666 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11667 */
11668 .extern MterpCheckBefore
11669 EXPORT_PC()
11670 la ra, artMterpAsmInstructionStart + (183 * 128) # Addr of primary handler
11671 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11672 move a0, rSELF # arg0
11673 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11674 la a2, MterpCheckBefore
11675 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11676
11677/* ------------------------------ */
11678 .balign 128
11679.L_ALT_op_shl_int_2addr: /* 0xb8 */
11680/* File: mips/alt_stub.S */
11681/*
11682 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11683 * any interesting requests and then jump to the real instruction
11684 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11685 */
11686 .extern MterpCheckBefore
11687 EXPORT_PC()
11688 la ra, artMterpAsmInstructionStart + (184 * 128) # Addr of primary handler
11689 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11690 move a0, rSELF # arg0
11691 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11692 la a2, MterpCheckBefore
11693 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11694
11695/* ------------------------------ */
11696 .balign 128
11697.L_ALT_op_shr_int_2addr: /* 0xb9 */
11698/* File: mips/alt_stub.S */
11699/*
11700 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11701 * any interesting requests and then jump to the real instruction
11702 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11703 */
11704 .extern MterpCheckBefore
11705 EXPORT_PC()
11706 la ra, artMterpAsmInstructionStart + (185 * 128) # Addr of primary handler
11707 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11708 move a0, rSELF # arg0
11709 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11710 la a2, MterpCheckBefore
11711 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11712
11713/* ------------------------------ */
11714 .balign 128
11715.L_ALT_op_ushr_int_2addr: /* 0xba */
11716/* File: mips/alt_stub.S */
11717/*
11718 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11719 * any interesting requests and then jump to the real instruction
11720 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11721 */
11722 .extern MterpCheckBefore
11723 EXPORT_PC()
11724 la ra, artMterpAsmInstructionStart + (186 * 128) # Addr of primary handler
11725 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11726 move a0, rSELF # arg0
11727 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11728 la a2, MterpCheckBefore
11729 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11730
11731/* ------------------------------ */
11732 .balign 128
11733.L_ALT_op_add_long_2addr: /* 0xbb */
11734/* File: mips/alt_stub.S */
11735/*
11736 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11737 * any interesting requests and then jump to the real instruction
11738 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11739 */
11740 .extern MterpCheckBefore
11741 EXPORT_PC()
11742 la ra, artMterpAsmInstructionStart + (187 * 128) # Addr of primary handler
11743 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11744 move a0, rSELF # arg0
11745 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11746 la a2, MterpCheckBefore
11747 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11748
11749/* ------------------------------ */
11750 .balign 128
11751.L_ALT_op_sub_long_2addr: /* 0xbc */
11752/* File: mips/alt_stub.S */
11753/*
11754 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11755 * any interesting requests and then jump to the real instruction
11756 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11757 */
11758 .extern MterpCheckBefore
11759 EXPORT_PC()
11760 la ra, artMterpAsmInstructionStart + (188 * 128) # Addr of primary handler
11761 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11762 move a0, rSELF # arg0
11763 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11764 la a2, MterpCheckBefore
11765 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11766
11767/* ------------------------------ */
11768 .balign 128
11769.L_ALT_op_mul_long_2addr: /* 0xbd */
11770/* File: mips/alt_stub.S */
11771/*
11772 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11773 * any interesting requests and then jump to the real instruction
11774 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11775 */
11776 .extern MterpCheckBefore
11777 EXPORT_PC()
11778 la ra, artMterpAsmInstructionStart + (189 * 128) # Addr of primary handler
11779 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11780 move a0, rSELF # arg0
11781 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11782 la a2, MterpCheckBefore
11783 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11784
11785/* ------------------------------ */
11786 .balign 128
11787.L_ALT_op_div_long_2addr: /* 0xbe */
11788/* File: mips/alt_stub.S */
11789/*
11790 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11791 * any interesting requests and then jump to the real instruction
11792 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11793 */
11794 .extern MterpCheckBefore
11795 EXPORT_PC()
11796 la ra, artMterpAsmInstructionStart + (190 * 128) # Addr of primary handler
11797 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11798 move a0, rSELF # arg0
11799 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11800 la a2, MterpCheckBefore
11801 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11802
11803/* ------------------------------ */
11804 .balign 128
11805.L_ALT_op_rem_long_2addr: /* 0xbf */
11806/* File: mips/alt_stub.S */
11807/*
11808 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11809 * any interesting requests and then jump to the real instruction
11810 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11811 */
11812 .extern MterpCheckBefore
11813 EXPORT_PC()
11814 la ra, artMterpAsmInstructionStart + (191 * 128) # Addr of primary handler
11815 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11816 move a0, rSELF # arg0
11817 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11818 la a2, MterpCheckBefore
11819 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11820
11821/* ------------------------------ */
11822 .balign 128
11823.L_ALT_op_and_long_2addr: /* 0xc0 */
11824/* File: mips/alt_stub.S */
11825/*
11826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11827 * any interesting requests and then jump to the real instruction
11828 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11829 */
11830 .extern MterpCheckBefore
11831 EXPORT_PC()
11832 la ra, artMterpAsmInstructionStart + (192 * 128) # Addr of primary handler
11833 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11834 move a0, rSELF # arg0
11835 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11836 la a2, MterpCheckBefore
11837 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11838
11839/* ------------------------------ */
11840 .balign 128
11841.L_ALT_op_or_long_2addr: /* 0xc1 */
11842/* File: mips/alt_stub.S */
11843/*
11844 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11845 * any interesting requests and then jump to the real instruction
11846 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11847 */
11848 .extern MterpCheckBefore
11849 EXPORT_PC()
11850 la ra, artMterpAsmInstructionStart + (193 * 128) # Addr of primary handler
11851 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11852 move a0, rSELF # arg0
11853 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11854 la a2, MterpCheckBefore
11855 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11856
11857/* ------------------------------ */
11858 .balign 128
11859.L_ALT_op_xor_long_2addr: /* 0xc2 */
11860/* File: mips/alt_stub.S */
11861/*
11862 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11863 * any interesting requests and then jump to the real instruction
11864 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11865 */
11866 .extern MterpCheckBefore
11867 EXPORT_PC()
11868 la ra, artMterpAsmInstructionStart + (194 * 128) # Addr of primary handler
11869 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11870 move a0, rSELF # arg0
11871 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11872 la a2, MterpCheckBefore
11873 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11874
11875/* ------------------------------ */
11876 .balign 128
11877.L_ALT_op_shl_long_2addr: /* 0xc3 */
11878/* File: mips/alt_stub.S */
11879/*
11880 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11881 * any interesting requests and then jump to the real instruction
11882 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11883 */
11884 .extern MterpCheckBefore
11885 EXPORT_PC()
11886 la ra, artMterpAsmInstructionStart + (195 * 128) # Addr of primary handler
11887 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11888 move a0, rSELF # arg0
11889 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11890 la a2, MterpCheckBefore
11891 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11892
11893/* ------------------------------ */
11894 .balign 128
11895.L_ALT_op_shr_long_2addr: /* 0xc4 */
11896/* File: mips/alt_stub.S */
11897/*
11898 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11899 * any interesting requests and then jump to the real instruction
11900 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11901 */
11902 .extern MterpCheckBefore
11903 EXPORT_PC()
11904 la ra, artMterpAsmInstructionStart + (196 * 128) # Addr of primary handler
11905 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11906 move a0, rSELF # arg0
11907 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11908 la a2, MterpCheckBefore
11909 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11910
11911/* ------------------------------ */
11912 .balign 128
11913.L_ALT_op_ushr_long_2addr: /* 0xc5 */
11914/* File: mips/alt_stub.S */
11915/*
11916 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11917 * any interesting requests and then jump to the real instruction
11918 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11919 */
11920 .extern MterpCheckBefore
11921 EXPORT_PC()
11922 la ra, artMterpAsmInstructionStart + (197 * 128) # Addr of primary handler
11923 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11924 move a0, rSELF # arg0
11925 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11926 la a2, MterpCheckBefore
11927 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11928
11929/* ------------------------------ */
11930 .balign 128
11931.L_ALT_op_add_float_2addr: /* 0xc6 */
11932/* File: mips/alt_stub.S */
11933/*
11934 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11935 * any interesting requests and then jump to the real instruction
11936 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11937 */
11938 .extern MterpCheckBefore
11939 EXPORT_PC()
11940 la ra, artMterpAsmInstructionStart + (198 * 128) # Addr of primary handler
11941 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11942 move a0, rSELF # arg0
11943 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11944 la a2, MterpCheckBefore
11945 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11946
11947/* ------------------------------ */
11948 .balign 128
11949.L_ALT_op_sub_float_2addr: /* 0xc7 */
11950/* File: mips/alt_stub.S */
11951/*
11952 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11953 * any interesting requests and then jump to the real instruction
11954 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11955 */
11956 .extern MterpCheckBefore
11957 EXPORT_PC()
11958 la ra, artMterpAsmInstructionStart + (199 * 128) # Addr of primary handler
11959 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11960 move a0, rSELF # arg0
11961 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11962 la a2, MterpCheckBefore
11963 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11964
11965/* ------------------------------ */
11966 .balign 128
11967.L_ALT_op_mul_float_2addr: /* 0xc8 */
11968/* File: mips/alt_stub.S */
11969/*
11970 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11971 * any interesting requests and then jump to the real instruction
11972 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11973 */
11974 .extern MterpCheckBefore
11975 EXPORT_PC()
11976 la ra, artMterpAsmInstructionStart + (200 * 128) # Addr of primary handler
11977 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11978 move a0, rSELF # arg0
11979 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11980 la a2, MterpCheckBefore
11981 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
11982
11983/* ------------------------------ */
11984 .balign 128
11985.L_ALT_op_div_float_2addr: /* 0xc9 */
11986/* File: mips/alt_stub.S */
11987/*
11988 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11989 * any interesting requests and then jump to the real instruction
11990 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11991 */
11992 .extern MterpCheckBefore
11993 EXPORT_PC()
11994 la ra, artMterpAsmInstructionStart + (201 * 128) # Addr of primary handler
11995 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
11996 move a0, rSELF # arg0
11997 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
11998 la a2, MterpCheckBefore
11999 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12000
12001/* ------------------------------ */
12002 .balign 128
12003.L_ALT_op_rem_float_2addr: /* 0xca */
12004/* File: mips/alt_stub.S */
12005/*
12006 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12007 * any interesting requests and then jump to the real instruction
12008 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12009 */
12010 .extern MterpCheckBefore
12011 EXPORT_PC()
12012 la ra, artMterpAsmInstructionStart + (202 * 128) # Addr of primary handler
12013 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12014 move a0, rSELF # arg0
12015 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12016 la a2, MterpCheckBefore
12017 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12018
12019/* ------------------------------ */
12020 .balign 128
12021.L_ALT_op_add_double_2addr: /* 0xcb */
12022/* File: mips/alt_stub.S */
12023/*
12024 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12025 * any interesting requests and then jump to the real instruction
12026 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12027 */
12028 .extern MterpCheckBefore
12029 EXPORT_PC()
12030 la ra, artMterpAsmInstructionStart + (203 * 128) # Addr of primary handler
12031 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12032 move a0, rSELF # arg0
12033 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12034 la a2, MterpCheckBefore
12035 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12036
12037/* ------------------------------ */
12038 .balign 128
12039.L_ALT_op_sub_double_2addr: /* 0xcc */
12040/* File: mips/alt_stub.S */
12041/*
12042 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12043 * any interesting requests and then jump to the real instruction
12044 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12045 */
12046 .extern MterpCheckBefore
12047 EXPORT_PC()
12048 la ra, artMterpAsmInstructionStart + (204 * 128) # Addr of primary handler
12049 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12050 move a0, rSELF # arg0
12051 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12052 la a2, MterpCheckBefore
12053 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12054
12055/* ------------------------------ */
12056 .balign 128
12057.L_ALT_op_mul_double_2addr: /* 0xcd */
12058/* File: mips/alt_stub.S */
12059/*
12060 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12061 * any interesting requests and then jump to the real instruction
12062 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12063 */
12064 .extern MterpCheckBefore
12065 EXPORT_PC()
12066 la ra, artMterpAsmInstructionStart + (205 * 128) # Addr of primary handler
12067 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12068 move a0, rSELF # arg0
12069 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12070 la a2, MterpCheckBefore
12071 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12072
12073/* ------------------------------ */
12074 .balign 128
12075.L_ALT_op_div_double_2addr: /* 0xce */
12076/* File: mips/alt_stub.S */
12077/*
12078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12079 * any interesting requests and then jump to the real instruction
12080 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12081 */
12082 .extern MterpCheckBefore
12083 EXPORT_PC()
12084 la ra, artMterpAsmInstructionStart + (206 * 128) # Addr of primary handler
12085 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12086 move a0, rSELF # arg0
12087 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12088 la a2, MterpCheckBefore
12089 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12090
12091/* ------------------------------ */
12092 .balign 128
12093.L_ALT_op_rem_double_2addr: /* 0xcf */
12094/* File: mips/alt_stub.S */
12095/*
12096 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12097 * any interesting requests and then jump to the real instruction
12098 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12099 */
12100 .extern MterpCheckBefore
12101 EXPORT_PC()
12102 la ra, artMterpAsmInstructionStart + (207 * 128) # Addr of primary handler
12103 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12104 move a0, rSELF # arg0
12105 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12106 la a2, MterpCheckBefore
12107 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12108
12109/* ------------------------------ */
12110 .balign 128
12111.L_ALT_op_add_int_lit16: /* 0xd0 */
12112/* File: mips/alt_stub.S */
12113/*
12114 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12115 * any interesting requests and then jump to the real instruction
12116 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12117 */
12118 .extern MterpCheckBefore
12119 EXPORT_PC()
12120 la ra, artMterpAsmInstructionStart + (208 * 128) # Addr of primary handler
12121 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12122 move a0, rSELF # arg0
12123 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12124 la a2, MterpCheckBefore
12125 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12126
12127/* ------------------------------ */
12128 .balign 128
12129.L_ALT_op_rsub_int: /* 0xd1 */
12130/* File: mips/alt_stub.S */
12131/*
12132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12133 * any interesting requests and then jump to the real instruction
12134 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12135 */
12136 .extern MterpCheckBefore
12137 EXPORT_PC()
12138 la ra, artMterpAsmInstructionStart + (209 * 128) # Addr of primary handler
12139 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12140 move a0, rSELF # arg0
12141 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12142 la a2, MterpCheckBefore
12143 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12144
12145/* ------------------------------ */
12146 .balign 128
12147.L_ALT_op_mul_int_lit16: /* 0xd2 */
12148/* File: mips/alt_stub.S */
12149/*
12150 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12151 * any interesting requests and then jump to the real instruction
12152 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12153 */
12154 .extern MterpCheckBefore
12155 EXPORT_PC()
12156 la ra, artMterpAsmInstructionStart + (210 * 128) # Addr of primary handler
12157 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12158 move a0, rSELF # arg0
12159 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12160 la a2, MterpCheckBefore
12161 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12162
12163/* ------------------------------ */
12164 .balign 128
12165.L_ALT_op_div_int_lit16: /* 0xd3 */
12166/* File: mips/alt_stub.S */
12167/*
12168 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12169 * any interesting requests and then jump to the real instruction
12170 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12171 */
12172 .extern MterpCheckBefore
12173 EXPORT_PC()
12174 la ra, artMterpAsmInstructionStart + (211 * 128) # Addr of primary handler
12175 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12176 move a0, rSELF # arg0
12177 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12178 la a2, MterpCheckBefore
12179 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12180
12181/* ------------------------------ */
12182 .balign 128
12183.L_ALT_op_rem_int_lit16: /* 0xd4 */
12184/* File: mips/alt_stub.S */
12185/*
12186 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12187 * any interesting requests and then jump to the real instruction
12188 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12189 */
12190 .extern MterpCheckBefore
12191 EXPORT_PC()
12192 la ra, artMterpAsmInstructionStart + (212 * 128) # Addr of primary handler
12193 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12194 move a0, rSELF # arg0
12195 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12196 la a2, MterpCheckBefore
12197 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12198
12199/* ------------------------------ */
12200 .balign 128
12201.L_ALT_op_and_int_lit16: /* 0xd5 */
12202/* File: mips/alt_stub.S */
12203/*
12204 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12205 * any interesting requests and then jump to the real instruction
12206 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12207 */
12208 .extern MterpCheckBefore
12209 EXPORT_PC()
12210 la ra, artMterpAsmInstructionStart + (213 * 128) # Addr of primary handler
12211 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12212 move a0, rSELF # arg0
12213 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12214 la a2, MterpCheckBefore
12215 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12216
12217/* ------------------------------ */
12218 .balign 128
12219.L_ALT_op_or_int_lit16: /* 0xd6 */
12220/* File: mips/alt_stub.S */
12221/*
12222 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12223 * any interesting requests and then jump to the real instruction
12224 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12225 */
12226 .extern MterpCheckBefore
12227 EXPORT_PC()
12228 la ra, artMterpAsmInstructionStart + (214 * 128) # Addr of primary handler
12229 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12230 move a0, rSELF # arg0
12231 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12232 la a2, MterpCheckBefore
12233 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12234
12235/* ------------------------------ */
12236 .balign 128
12237.L_ALT_op_xor_int_lit16: /* 0xd7 */
12238/* File: mips/alt_stub.S */
12239/*
12240 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12241 * any interesting requests and then jump to the real instruction
12242 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12243 */
12244 .extern MterpCheckBefore
12245 EXPORT_PC()
12246 la ra, artMterpAsmInstructionStart + (215 * 128) # Addr of primary handler
12247 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12248 move a0, rSELF # arg0
12249 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12250 la a2, MterpCheckBefore
12251 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12252
12253/* ------------------------------ */
12254 .balign 128
12255.L_ALT_op_add_int_lit8: /* 0xd8 */
12256/* File: mips/alt_stub.S */
12257/*
12258 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12259 * any interesting requests and then jump to the real instruction
12260 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12261 */
12262 .extern MterpCheckBefore
12263 EXPORT_PC()
12264 la ra, artMterpAsmInstructionStart + (216 * 128) # Addr of primary handler
12265 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12266 move a0, rSELF # arg0
12267 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12268 la a2, MterpCheckBefore
12269 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12270
12271/* ------------------------------ */
12272 .balign 128
12273.L_ALT_op_rsub_int_lit8: /* 0xd9 */
12274/* File: mips/alt_stub.S */
12275/*
12276 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12277 * any interesting requests and then jump to the real instruction
12278 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12279 */
12280 .extern MterpCheckBefore
12281 EXPORT_PC()
12282 la ra, artMterpAsmInstructionStart + (217 * 128) # Addr of primary handler
12283 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12284 move a0, rSELF # arg0
12285 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12286 la a2, MterpCheckBefore
12287 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12288
12289/* ------------------------------ */
12290 .balign 128
12291.L_ALT_op_mul_int_lit8: /* 0xda */
12292/* File: mips/alt_stub.S */
12293/*
12294 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12295 * any interesting requests and then jump to the real instruction
12296 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12297 */
12298 .extern MterpCheckBefore
12299 EXPORT_PC()
12300 la ra, artMterpAsmInstructionStart + (218 * 128) # Addr of primary handler
12301 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12302 move a0, rSELF # arg0
12303 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12304 la a2, MterpCheckBefore
12305 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12306
12307/* ------------------------------ */
12308 .balign 128
12309.L_ALT_op_div_int_lit8: /* 0xdb */
12310/* File: mips/alt_stub.S */
12311/*
12312 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12313 * any interesting requests and then jump to the real instruction
12314 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12315 */
12316 .extern MterpCheckBefore
12317 EXPORT_PC()
12318 la ra, artMterpAsmInstructionStart + (219 * 128) # Addr of primary handler
12319 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12320 move a0, rSELF # arg0
12321 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12322 la a2, MterpCheckBefore
12323 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12324
12325/* ------------------------------ */
12326 .balign 128
12327.L_ALT_op_rem_int_lit8: /* 0xdc */
12328/* File: mips/alt_stub.S */
12329/*
12330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12331 * any interesting requests and then jump to the real instruction
12332 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12333 */
12334 .extern MterpCheckBefore
12335 EXPORT_PC()
12336 la ra, artMterpAsmInstructionStart + (220 * 128) # Addr of primary handler
12337 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12338 move a0, rSELF # arg0
12339 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12340 la a2, MterpCheckBefore
12341 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12342
12343/* ------------------------------ */
12344 .balign 128
12345.L_ALT_op_and_int_lit8: /* 0xdd */
12346/* File: mips/alt_stub.S */
12347/*
12348 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12349 * any interesting requests and then jump to the real instruction
12350 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12351 */
12352 .extern MterpCheckBefore
12353 EXPORT_PC()
12354 la ra, artMterpAsmInstructionStart + (221 * 128) # Addr of primary handler
12355 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12356 move a0, rSELF # arg0
12357 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12358 la a2, MterpCheckBefore
12359 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12360
12361/* ------------------------------ */
12362 .balign 128
12363.L_ALT_op_or_int_lit8: /* 0xde */
12364/* File: mips/alt_stub.S */
12365/*
12366 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12367 * any interesting requests and then jump to the real instruction
12368 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12369 */
12370 .extern MterpCheckBefore
12371 EXPORT_PC()
12372 la ra, artMterpAsmInstructionStart + (222 * 128) # Addr of primary handler
12373 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12374 move a0, rSELF # arg0
12375 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12376 la a2, MterpCheckBefore
12377 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12378
12379/* ------------------------------ */
12380 .balign 128
12381.L_ALT_op_xor_int_lit8: /* 0xdf */
12382/* File: mips/alt_stub.S */
12383/*
12384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12385 * any interesting requests and then jump to the real instruction
12386 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12387 */
12388 .extern MterpCheckBefore
12389 EXPORT_PC()
12390 la ra, artMterpAsmInstructionStart + (223 * 128) # Addr of primary handler
12391 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12392 move a0, rSELF # arg0
12393 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12394 la a2, MterpCheckBefore
12395 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12396
12397/* ------------------------------ */
12398 .balign 128
12399.L_ALT_op_shl_int_lit8: /* 0xe0 */
12400/* File: mips/alt_stub.S */
12401/*
12402 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12403 * any interesting requests and then jump to the real instruction
12404 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12405 */
12406 .extern MterpCheckBefore
12407 EXPORT_PC()
12408 la ra, artMterpAsmInstructionStart + (224 * 128) # Addr of primary handler
12409 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12410 move a0, rSELF # arg0
12411 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12412 la a2, MterpCheckBefore
12413 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12414
12415/* ------------------------------ */
12416 .balign 128
12417.L_ALT_op_shr_int_lit8: /* 0xe1 */
12418/* File: mips/alt_stub.S */
12419/*
12420 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12421 * any interesting requests and then jump to the real instruction
12422 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12423 */
12424 .extern MterpCheckBefore
12425 EXPORT_PC()
12426 la ra, artMterpAsmInstructionStart + (225 * 128) # Addr of primary handler
12427 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12428 move a0, rSELF # arg0
12429 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12430 la a2, MterpCheckBefore
12431 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12432
12433/* ------------------------------ */
12434 .balign 128
12435.L_ALT_op_ushr_int_lit8: /* 0xe2 */
12436/* File: mips/alt_stub.S */
12437/*
12438 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12439 * any interesting requests and then jump to the real instruction
12440 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12441 */
12442 .extern MterpCheckBefore
12443 EXPORT_PC()
12444 la ra, artMterpAsmInstructionStart + (226 * 128) # Addr of primary handler
12445 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12446 move a0, rSELF # arg0
12447 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12448 la a2, MterpCheckBefore
12449 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12450
12451/* ------------------------------ */
12452 .balign 128
12453.L_ALT_op_iget_quick: /* 0xe3 */
12454/* File: mips/alt_stub.S */
12455/*
12456 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12457 * any interesting requests and then jump to the real instruction
12458 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12459 */
12460 .extern MterpCheckBefore
12461 EXPORT_PC()
12462 la ra, artMterpAsmInstructionStart + (227 * 128) # Addr of primary handler
12463 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12464 move a0, rSELF # arg0
12465 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12466 la a2, MterpCheckBefore
12467 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12468
12469/* ------------------------------ */
12470 .balign 128
12471.L_ALT_op_iget_wide_quick: /* 0xe4 */
12472/* File: mips/alt_stub.S */
12473/*
12474 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12475 * any interesting requests and then jump to the real instruction
12476 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12477 */
12478 .extern MterpCheckBefore
12479 EXPORT_PC()
12480 la ra, artMterpAsmInstructionStart + (228 * 128) # Addr of primary handler
12481 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12482 move a0, rSELF # arg0
12483 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12484 la a2, MterpCheckBefore
12485 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12486
12487/* ------------------------------ */
12488 .balign 128
12489.L_ALT_op_iget_object_quick: /* 0xe5 */
12490/* File: mips/alt_stub.S */
12491/*
12492 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12493 * any interesting requests and then jump to the real instruction
12494 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12495 */
12496 .extern MterpCheckBefore
12497 EXPORT_PC()
12498 la ra, artMterpAsmInstructionStart + (229 * 128) # Addr of primary handler
12499 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12500 move a0, rSELF # arg0
12501 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12502 la a2, MterpCheckBefore
12503 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12504
12505/* ------------------------------ */
12506 .balign 128
12507.L_ALT_op_iput_quick: /* 0xe6 */
12508/* File: mips/alt_stub.S */
12509/*
12510 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12511 * any interesting requests and then jump to the real instruction
12512 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12513 */
12514 .extern MterpCheckBefore
12515 EXPORT_PC()
12516 la ra, artMterpAsmInstructionStart + (230 * 128) # Addr of primary handler
12517 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12518 move a0, rSELF # arg0
12519 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12520 la a2, MterpCheckBefore
12521 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12522
12523/* ------------------------------ */
12524 .balign 128
12525.L_ALT_op_iput_wide_quick: /* 0xe7 */
12526/* File: mips/alt_stub.S */
12527/*
12528 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12529 * any interesting requests and then jump to the real instruction
12530 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12531 */
12532 .extern MterpCheckBefore
12533 EXPORT_PC()
12534 la ra, artMterpAsmInstructionStart + (231 * 128) # Addr of primary handler
12535 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12536 move a0, rSELF # arg0
12537 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12538 la a2, MterpCheckBefore
12539 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12540
12541/* ------------------------------ */
12542 .balign 128
12543.L_ALT_op_iput_object_quick: /* 0xe8 */
12544/* File: mips/alt_stub.S */
12545/*
12546 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12547 * any interesting requests and then jump to the real instruction
12548 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12549 */
12550 .extern MterpCheckBefore
12551 EXPORT_PC()
12552 la ra, artMterpAsmInstructionStart + (232 * 128) # Addr of primary handler
12553 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12554 move a0, rSELF # arg0
12555 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12556 la a2, MterpCheckBefore
12557 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12558
12559/* ------------------------------ */
12560 .balign 128
12561.L_ALT_op_invoke_virtual_quick: /* 0xe9 */
12562/* File: mips/alt_stub.S */
12563/*
12564 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12565 * any interesting requests and then jump to the real instruction
12566 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12567 */
12568 .extern MterpCheckBefore
12569 EXPORT_PC()
12570 la ra, artMterpAsmInstructionStart + (233 * 128) # Addr of primary handler
12571 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12572 move a0, rSELF # arg0
12573 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12574 la a2, MterpCheckBefore
12575 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12576
12577/* ------------------------------ */
12578 .balign 128
12579.L_ALT_op_invoke_virtual_range_quick: /* 0xea */
12580/* File: mips/alt_stub.S */
12581/*
12582 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12583 * any interesting requests and then jump to the real instruction
12584 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12585 */
12586 .extern MterpCheckBefore
12587 EXPORT_PC()
12588 la ra, artMterpAsmInstructionStart + (234 * 128) # Addr of primary handler
12589 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12590 move a0, rSELF # arg0
12591 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12592 la a2, MterpCheckBefore
12593 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12594
12595/* ------------------------------ */
12596 .balign 128
12597.L_ALT_op_iput_boolean_quick: /* 0xeb */
12598/* File: mips/alt_stub.S */
12599/*
12600 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12601 * any interesting requests and then jump to the real instruction
12602 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12603 */
12604 .extern MterpCheckBefore
12605 EXPORT_PC()
12606 la ra, artMterpAsmInstructionStart + (235 * 128) # Addr of primary handler
12607 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12608 move a0, rSELF # arg0
12609 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12610 la a2, MterpCheckBefore
12611 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12612
12613/* ------------------------------ */
12614 .balign 128
12615.L_ALT_op_iput_byte_quick: /* 0xec */
12616/* File: mips/alt_stub.S */
12617/*
12618 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12619 * any interesting requests and then jump to the real instruction
12620 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12621 */
12622 .extern MterpCheckBefore
12623 EXPORT_PC()
12624 la ra, artMterpAsmInstructionStart + (236 * 128) # Addr of primary handler
12625 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12626 move a0, rSELF # arg0
12627 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12628 la a2, MterpCheckBefore
12629 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12630
12631/* ------------------------------ */
12632 .balign 128
12633.L_ALT_op_iput_char_quick: /* 0xed */
12634/* File: mips/alt_stub.S */
12635/*
12636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12637 * any interesting requests and then jump to the real instruction
12638 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12639 */
12640 .extern MterpCheckBefore
12641 EXPORT_PC()
12642 la ra, artMterpAsmInstructionStart + (237 * 128) # Addr of primary handler
12643 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12644 move a0, rSELF # arg0
12645 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12646 la a2, MterpCheckBefore
12647 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12648
12649/* ------------------------------ */
12650 .balign 128
12651.L_ALT_op_iput_short_quick: /* 0xee */
12652/* File: mips/alt_stub.S */
12653/*
12654 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12655 * any interesting requests and then jump to the real instruction
12656 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12657 */
12658 .extern MterpCheckBefore
12659 EXPORT_PC()
12660 la ra, artMterpAsmInstructionStart + (238 * 128) # Addr of primary handler
12661 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12662 move a0, rSELF # arg0
12663 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12664 la a2, MterpCheckBefore
12665 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12666
12667/* ------------------------------ */
12668 .balign 128
12669.L_ALT_op_iget_boolean_quick: /* 0xef */
12670/* File: mips/alt_stub.S */
12671/*
12672 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12673 * any interesting requests and then jump to the real instruction
12674 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12675 */
12676 .extern MterpCheckBefore
12677 EXPORT_PC()
12678 la ra, artMterpAsmInstructionStart + (239 * 128) # Addr of primary handler
12679 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12680 move a0, rSELF # arg0
12681 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12682 la a2, MterpCheckBefore
12683 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12684
12685/* ------------------------------ */
12686 .balign 128
12687.L_ALT_op_iget_byte_quick: /* 0xf0 */
12688/* File: mips/alt_stub.S */
12689/*
12690 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12691 * any interesting requests and then jump to the real instruction
12692 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12693 */
12694 .extern MterpCheckBefore
12695 EXPORT_PC()
12696 la ra, artMterpAsmInstructionStart + (240 * 128) # Addr of primary handler
12697 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12698 move a0, rSELF # arg0
12699 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12700 la a2, MterpCheckBefore
12701 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12702
12703/* ------------------------------ */
12704 .balign 128
12705.L_ALT_op_iget_char_quick: /* 0xf1 */
12706/* File: mips/alt_stub.S */
12707/*
12708 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12709 * any interesting requests and then jump to the real instruction
12710 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12711 */
12712 .extern MterpCheckBefore
12713 EXPORT_PC()
12714 la ra, artMterpAsmInstructionStart + (241 * 128) # Addr of primary handler
12715 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12716 move a0, rSELF # arg0
12717 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12718 la a2, MterpCheckBefore
12719 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12720
12721/* ------------------------------ */
12722 .balign 128
12723.L_ALT_op_iget_short_quick: /* 0xf2 */
12724/* File: mips/alt_stub.S */
12725/*
12726 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12727 * any interesting requests and then jump to the real instruction
12728 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12729 */
12730 .extern MterpCheckBefore
12731 EXPORT_PC()
12732 la ra, artMterpAsmInstructionStart + (242 * 128) # Addr of primary handler
12733 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12734 move a0, rSELF # arg0
12735 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12736 la a2, MterpCheckBefore
12737 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12738
12739/* ------------------------------ */
12740 .balign 128
12741.L_ALT_op_invoke_lambda: /* 0xf3 */
12742/* File: mips/alt_stub.S */
12743/*
12744 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12745 * any interesting requests and then jump to the real instruction
12746 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12747 */
12748 .extern MterpCheckBefore
12749 EXPORT_PC()
12750 la ra, artMterpAsmInstructionStart + (243 * 128) # Addr of primary handler
12751 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12752 move a0, rSELF # arg0
12753 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12754 la a2, MterpCheckBefore
12755 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12756
12757/* ------------------------------ */
12758 .balign 128
12759.L_ALT_op_unused_f4: /* 0xf4 */
12760/* File: mips/alt_stub.S */
12761/*
12762 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12763 * any interesting requests and then jump to the real instruction
12764 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12765 */
12766 .extern MterpCheckBefore
12767 EXPORT_PC()
12768 la ra, artMterpAsmInstructionStart + (244 * 128) # Addr of primary handler
12769 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12770 move a0, rSELF # arg0
12771 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12772 la a2, MterpCheckBefore
12773 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12774
12775/* ------------------------------ */
12776 .balign 128
12777.L_ALT_op_capture_variable: /* 0xf5 */
12778/* File: mips/alt_stub.S */
12779/*
12780 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12781 * any interesting requests and then jump to the real instruction
12782 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12783 */
12784 .extern MterpCheckBefore
12785 EXPORT_PC()
12786 la ra, artMterpAsmInstructionStart + (245 * 128) # Addr of primary handler
12787 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12788 move a0, rSELF # arg0
12789 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12790 la a2, MterpCheckBefore
12791 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12792
12793/* ------------------------------ */
12794 .balign 128
12795.L_ALT_op_create_lambda: /* 0xf6 */
12796/* File: mips/alt_stub.S */
12797/*
12798 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12799 * any interesting requests and then jump to the real instruction
12800 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12801 */
12802 .extern MterpCheckBefore
12803 EXPORT_PC()
12804 la ra, artMterpAsmInstructionStart + (246 * 128) # Addr of primary handler
12805 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12806 move a0, rSELF # arg0
12807 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12808 la a2, MterpCheckBefore
12809 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12810
12811/* ------------------------------ */
12812 .balign 128
12813.L_ALT_op_liberate_variable: /* 0xf7 */
12814/* File: mips/alt_stub.S */
12815/*
12816 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12817 * any interesting requests and then jump to the real instruction
12818 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12819 */
12820 .extern MterpCheckBefore
12821 EXPORT_PC()
12822 la ra, artMterpAsmInstructionStart + (247 * 128) # Addr of primary handler
12823 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12824 move a0, rSELF # arg0
12825 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12826 la a2, MterpCheckBefore
12827 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12828
12829/* ------------------------------ */
12830 .balign 128
12831.L_ALT_op_box_lambda: /* 0xf8 */
12832/* File: mips/alt_stub.S */
12833/*
12834 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12835 * any interesting requests and then jump to the real instruction
12836 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12837 */
12838 .extern MterpCheckBefore
12839 EXPORT_PC()
12840 la ra, artMterpAsmInstructionStart + (248 * 128) # Addr of primary handler
12841 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12842 move a0, rSELF # arg0
12843 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12844 la a2, MterpCheckBefore
12845 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12846
12847/* ------------------------------ */
12848 .balign 128
12849.L_ALT_op_unbox_lambda: /* 0xf9 */
12850/* File: mips/alt_stub.S */
12851/*
12852 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12853 * any interesting requests and then jump to the real instruction
12854 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12855 */
12856 .extern MterpCheckBefore
12857 EXPORT_PC()
12858 la ra, artMterpAsmInstructionStart + (249 * 128) # Addr of primary handler
12859 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12860 move a0, rSELF # arg0
12861 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12862 la a2, MterpCheckBefore
12863 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12864
12865/* ------------------------------ */
12866 .balign 128
12867.L_ALT_op_unused_fa: /* 0xfa */
12868/* File: mips/alt_stub.S */
12869/*
12870 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12871 * any interesting requests and then jump to the real instruction
12872 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12873 */
12874 .extern MterpCheckBefore
12875 EXPORT_PC()
12876 la ra, artMterpAsmInstructionStart + (250 * 128) # Addr of primary handler
12877 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12878 move a0, rSELF # arg0
12879 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12880 la a2, MterpCheckBefore
12881 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12882
12883/* ------------------------------ */
12884 .balign 128
12885.L_ALT_op_unused_fb: /* 0xfb */
12886/* File: mips/alt_stub.S */
12887/*
12888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12889 * any interesting requests and then jump to the real instruction
12890 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12891 */
12892 .extern MterpCheckBefore
12893 EXPORT_PC()
12894 la ra, artMterpAsmInstructionStart + (251 * 128) # Addr of primary handler
12895 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12896 move a0, rSELF # arg0
12897 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12898 la a2, MterpCheckBefore
12899 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12900
12901/* ------------------------------ */
12902 .balign 128
12903.L_ALT_op_unused_fc: /* 0xfc */
12904/* File: mips/alt_stub.S */
12905/*
12906 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12907 * any interesting requests and then jump to the real instruction
12908 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12909 */
12910 .extern MterpCheckBefore
12911 EXPORT_PC()
12912 la ra, artMterpAsmInstructionStart + (252 * 128) # Addr of primary handler
12913 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12914 move a0, rSELF # arg0
12915 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12916 la a2, MterpCheckBefore
12917 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12918
12919/* ------------------------------ */
12920 .balign 128
12921.L_ALT_op_unused_fd: /* 0xfd */
12922/* File: mips/alt_stub.S */
12923/*
12924 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12925 * any interesting requests and then jump to the real instruction
12926 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12927 */
12928 .extern MterpCheckBefore
12929 EXPORT_PC()
12930 la ra, artMterpAsmInstructionStart + (253 * 128) # Addr of primary handler
12931 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12932 move a0, rSELF # arg0
12933 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12934 la a2, MterpCheckBefore
12935 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12936
12937/* ------------------------------ */
12938 .balign 128
12939.L_ALT_op_unused_fe: /* 0xfe */
12940/* File: mips/alt_stub.S */
12941/*
12942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12943 * any interesting requests and then jump to the real instruction
12944 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12945 */
12946 .extern MterpCheckBefore
12947 EXPORT_PC()
12948 la ra, artMterpAsmInstructionStart + (254 * 128) # Addr of primary handler
12949 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12950 move a0, rSELF # arg0
12951 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12952 la a2, MterpCheckBefore
12953 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12954
12955/* ------------------------------ */
12956 .balign 128
12957.L_ALT_op_unused_ff: /* 0xff */
12958/* File: mips/alt_stub.S */
12959/*
12960 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12961 * any interesting requests and then jump to the real instruction
12962 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12963 */
12964 .extern MterpCheckBefore
12965 EXPORT_PC()
12966 la ra, artMterpAsmInstructionStart + (255 * 128) # Addr of primary handler
12967 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE
12968 move a0, rSELF # arg0
12969 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1
12970 la a2, MterpCheckBefore
12971 jalr zero, a2 # Tail call to Mterp(self, shadow_frame)
12972
12973 .balign 128
12974 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart
12975 .global artMterpAsmAltInstructionEnd
12976artMterpAsmAltInstructionEnd:
12977/* File: mips/footer.S */
12978/*
12979 * ===========================================================================
12980 * Common subroutines and data
12981 * ===========================================================================
12982 */
12983
12984 .text
12985 .align 2
12986
12987/*
12988 * We've detected a condition that will result in an exception, but the exception
12989 * has not yet been thrown. Just bail out to the reference interpreter to deal with it.
12990 * TUNING: for consistency, we may want to just go ahead and handle these here.
12991 */
12992common_errDivideByZero:
12993 EXPORT_PC()
12994#if MTERP_LOGGING
12995 move a0, rSELF
12996 addu a1, rFP, OFF_FP_SHADOWFRAME
12997 JAL(MterpLogDivideByZeroException)
12998#endif
12999 b MterpCommonFallback
13000
13001common_errArrayIndex:
13002 EXPORT_PC()
13003#if MTERP_LOGGING
13004 move a0, rSELF
13005 addu a1, rFP, OFF_FP_SHADOWFRAME
13006 JAL(MterpLogArrayIndexException)
13007#endif
13008 b MterpCommonFallback
13009
13010common_errNegativeArraySize:
13011 EXPORT_PC()
13012#if MTERP_LOGGING
13013 move a0, rSELF
13014 addu a1, rFP, OFF_FP_SHADOWFRAME
13015 JAL(MterpLogNegativeArraySizeException)
13016#endif
13017 b MterpCommonFallback
13018
13019common_errNoSuchMethod:
13020 EXPORT_PC()
13021#if MTERP_LOGGING
13022 move a0, rSELF
13023 addu a1, rFP, OFF_FP_SHADOWFRAME
13024 JAL(MterpLogNoSuchMethodException)
13025#endif
13026 b MterpCommonFallback
13027
13028common_errNullObject:
13029 EXPORT_PC()
13030#if MTERP_LOGGING
13031 move a0, rSELF
13032 addu a1, rFP, OFF_FP_SHADOWFRAME
13033 JAL(MterpLogNullObjectException)
13034#endif
13035 b MterpCommonFallback
13036
13037common_exceptionThrown:
13038 EXPORT_PC()
13039#if MTERP_LOGGING
13040 move a0, rSELF
13041 addu a1, rFP, OFF_FP_SHADOWFRAME
13042 JAL(MterpLogExceptionThrownException)
13043#endif
13044 b MterpCommonFallback
13045
13046MterpSuspendFallback:
13047 EXPORT_PC()
13048#if MTERP_LOGGING
13049 move a0, rSELF
13050 addu a1, rFP, OFF_FP_SHADOWFRAME
13051 lw a2, THREAD_FLAGS_OFFSET(rSELF)
13052 JAL(MterpLogSuspendFallback)
13053#endif
13054 b MterpCommonFallback
13055
13056/*
13057 * If we're here, something is out of the ordinary. If there is a pending
13058 * exception, handle it. Otherwise, roll back and retry with the reference
13059 * interpreter.
13060 */
13061MterpPossibleException:
13062 lw a0, THREAD_EXCEPTION_OFFSET(rSELF)
13063 beqz a0, MterpFallback # If exception, fall back to reference interpreter.
13064 /* intentional fallthrough - handle pending exception. */
13065/*
13066 * On return from a runtime helper routine, we've found a pending exception.
13067 * Can we handle it here - or need to bail out to caller?
13068 *
13069 */
13070MterpException:
13071 move a0, rSELF
13072 addu a1, rFP, OFF_FP_SHADOWFRAME
13073 JAL(MterpHandleException) # (self, shadow_frame)
13074 beqz v0, MterpExceptionReturn # no local catch, back to caller.
13075 lw a0, OFF_FP_CODE_ITEM(rFP)
13076 lw a1, OFF_FP_DEX_PC(rFP)
13077 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
13078 addu rPC, a0, CODEITEM_INSNS_OFFSET
13079 sll a1, a1, 1
13080 addu rPC, rPC, a1 # generate new dex_pc_ptr
13081 /* Do we need to switch interpreters? */
13082 JAL(MterpShouldSwitchInterpreters)
13083 bnez v0, MterpFallback
13084 /* resume execution at catch block */
13085 EXPORT_PC()
13086 FETCH_INST()
13087 GET_INST_OPCODE(t0)
13088 GOTO_OPCODE(t0)
13089 /* NOTE: no fallthrough */
13090
13091/*
13092 * Check for suspend check request. Assumes rINST already loaded, rPC advanced and
13093 * still needs to get the opcode and branch to it, and flags are in lr.
13094 */
13095MterpCheckSuspendAndContinue:
13096 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh rIBASE
13097 and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
13098 bnez ra, 1f
13099 GET_INST_OPCODE(t0) # extract opcode from rINST
13100 GOTO_OPCODE(t0) # jump to next instruction
131011:
13102 EXPORT_PC()
13103 move a0, rSELF
13104 JAL(MterpSuspendCheck) # (self)
13105 bnez v0, MterpFallback
13106 GET_INST_OPCODE(t0) # extract opcode from rINST
13107 GOTO_OPCODE(t0) # jump to next instruction
13108
13109/*
13110 * On-stack replacement has happened, and now we've returned from the compiled method.
13111 */
13112MterpOnStackReplacement:
13113#if MTERP_LOGGING
13114 move a0, rSELF
13115 addu a1, rFP, OFF_FP_SHADOWFRAME
13116 move a2, rINST
13117 JAL(MterpLogOSR)
13118#endif
13119 li v0, 1 # Signal normal return
13120 b MterpDone
13121
13122/*
13123 * Bail out to reference interpreter.
13124 */
13125MterpFallback:
13126 EXPORT_PC()
13127#if MTERP_LOGGING
13128 move a0, rSELF
13129 addu a1, rFP, OFF_FP_SHADOWFRAME
13130 JAL(MterpLogFallback)
13131#endif
13132MterpCommonFallback:
13133 move v0, zero # signal retry with reference interpreter.
13134 b MterpDone
13135/*
13136 * We pushed some registers on the stack in ExecuteMterpImpl, then saved
13137 * SP and LR. Here we restore SP, restore the registers, and then restore
13138 * LR to PC.
13139 *
13140 * On entry:
13141 * uint32_t* rFP (should still be live, pointer to base of vregs)
13142 */
13143MterpExceptionReturn:
13144 li v0, 1 # signal return to caller.
13145 b MterpDone
13146MterpReturn:
13147 lw a2, OFF_FP_RESULT_REGISTER(rFP)
13148 sw v0, 0(a2)
13149 sw v1, 4(a2)
13150 li v0, 1 # signal return to caller.
13151MterpDone:
13152/* Restore from the stack and return. Frame size = STACK_SIZE */
13153 STACK_LOAD_FULL()
13154 jalr zero, ra
13155
13156 .end ExecuteMterpImpl
13157