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Chris Larsen701566a2015-10-27 15:29:13 -07001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "intrinsics_mips.h"
18
19#include "arch/mips/instruction_set_features_mips.h"
20#include "art_method.h"
21#include "code_generator_mips.h"
22#include "entrypoints/quick/quick_entrypoints.h"
23#include "intrinsics.h"
24#include "mirror/array-inl.h"
25#include "mirror/string.h"
26#include "thread.h"
27#include "utils/mips/assembler_mips.h"
28#include "utils/mips/constants_mips.h"
29
30namespace art {
31
32namespace mips {
33
34IntrinsicLocationsBuilderMIPS::IntrinsicLocationsBuilderMIPS(CodeGeneratorMIPS* codegen)
35 : arena_(codegen->GetGraph()->GetArena()) {
36}
37
38MipsAssembler* IntrinsicCodeGeneratorMIPS::GetAssembler() {
39 return reinterpret_cast<MipsAssembler*>(codegen_->GetAssembler());
40}
41
42ArenaAllocator* IntrinsicCodeGeneratorMIPS::GetAllocator() {
43 return codegen_->GetGraph()->GetArena();
44}
45
Alexey Frunzebb9863a2016-01-11 15:51:16 -080046inline bool IntrinsicCodeGeneratorMIPS::IsR2OrNewer() const {
Chris Larsene16ce5a2015-11-18 12:30:20 -080047 return codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2();
48}
49
Alexey Frunzebb9863a2016-01-11 15:51:16 -080050inline bool IntrinsicCodeGeneratorMIPS::IsR6() const {
Chris Larsene16ce5a2015-11-18 12:30:20 -080051 return codegen_->GetInstructionSetFeatures().IsR6();
52}
53
Alexey Frunzebb9863a2016-01-11 15:51:16 -080054inline bool IntrinsicCodeGeneratorMIPS::Is32BitFPU() const {
55 return codegen_->GetInstructionSetFeatures().Is32BitFloatingPoint();
56}
57
Chris Larsen701566a2015-10-27 15:29:13 -070058#define __ codegen->GetAssembler()->
59
60static void MoveFromReturnRegister(Location trg,
61 Primitive::Type type,
62 CodeGeneratorMIPS* codegen) {
63 if (!trg.IsValid()) {
64 DCHECK_EQ(type, Primitive::kPrimVoid);
65 return;
66 }
67
68 DCHECK_NE(type, Primitive::kPrimVoid);
69
70 if (Primitive::IsIntegralType(type) || type == Primitive::kPrimNot) {
71 Register trg_reg = trg.AsRegister<Register>();
72 if (trg_reg != V0) {
73 __ Move(V0, trg_reg);
74 }
75 } else {
76 FRegister trg_reg = trg.AsFpuRegister<FRegister>();
77 if (trg_reg != F0) {
78 if (type == Primitive::kPrimFloat) {
79 __ MovS(F0, trg_reg);
80 } else {
81 __ MovD(F0, trg_reg);
82 }
83 }
84 }
85}
86
87static void MoveArguments(HInvoke* invoke, CodeGeneratorMIPS* codegen) {
88 InvokeDexCallingConventionVisitorMIPS calling_convention_visitor;
89 IntrinsicVisitor::MoveArguments(invoke, codegen, &calling_convention_visitor);
90}
91
92// Slow-path for fallback (calling the managed code to handle the
93// intrinsic) in an intrinsified call. This will copy the arguments
94// into the positions for a regular call.
95//
96// Note: The actual parameters are required to be in the locations
97// given by the invoke's location summary. If an intrinsic
98// modifies those locations before a slowpath call, they must be
99// restored!
100class IntrinsicSlowPathMIPS : public SlowPathCodeMIPS {
101 public:
David Srbecky9cd6d372016-02-09 15:24:47 +0000102 explicit IntrinsicSlowPathMIPS(HInvoke* invoke) : SlowPathCodeMIPS(invoke), invoke_(invoke) { }
Chris Larsen701566a2015-10-27 15:29:13 -0700103
104 void EmitNativeCode(CodeGenerator* codegen_in) OVERRIDE {
105 CodeGeneratorMIPS* codegen = down_cast<CodeGeneratorMIPS*>(codegen_in);
106
107 __ Bind(GetEntryLabel());
108
109 SaveLiveRegisters(codegen, invoke_->GetLocations());
110
111 MoveArguments(invoke_, codegen);
112
113 if (invoke_->IsInvokeStaticOrDirect()) {
114 codegen->GenerateStaticOrDirectCall(invoke_->AsInvokeStaticOrDirect(),
115 Location::RegisterLocation(A0));
Chris Larsen701566a2015-10-27 15:29:13 -0700116 } else {
Chris Larsen3acee732015-11-18 13:31:08 -0800117 codegen->GenerateVirtualCall(invoke_->AsInvokeVirtual(), Location::RegisterLocation(A0));
Chris Larsen701566a2015-10-27 15:29:13 -0700118 }
Chris Larsen3acee732015-11-18 13:31:08 -0800119 codegen->RecordPcInfo(invoke_, invoke_->GetDexPc(), this);
Chris Larsen701566a2015-10-27 15:29:13 -0700120
121 // Copy the result back to the expected output.
122 Location out = invoke_->GetLocations()->Out();
123 if (out.IsValid()) {
124 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
125 DCHECK(!invoke_->GetLocations()->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
126 MoveFromReturnRegister(out, invoke_->GetType(), codegen);
127 }
128
129 RestoreLiveRegisters(codegen, invoke_->GetLocations());
130 __ B(GetExitLabel());
131 }
132
133 const char* GetDescription() const OVERRIDE { return "IntrinsicSlowPathMIPS"; }
134
135 private:
136 // The instruction where this slow path is happening.
137 HInvoke* const invoke_;
138
139 DISALLOW_COPY_AND_ASSIGN(IntrinsicSlowPathMIPS);
140};
141
142#undef __
143
144bool IntrinsicLocationsBuilderMIPS::TryDispatch(HInvoke* invoke) {
145 Dispatch(invoke);
146 LocationSummary* res = invoke->GetLocations();
147 return res != nullptr && res->Intrinsified();
148}
149
150#define __ assembler->
151
Chris Larsen3f8bf652015-10-28 10:08:56 -0700152static void CreateFPToIntLocations(ArenaAllocator* arena, HInvoke* invoke) {
153 LocationSummary* locations = new (arena) LocationSummary(invoke,
154 LocationSummary::kNoCall,
155 kIntrinsified);
156 locations->SetInAt(0, Location::RequiresFpuRegister());
157 locations->SetOut(Location::RequiresRegister());
158}
159
160static void MoveFPToInt(LocationSummary* locations, bool is64bit, MipsAssembler* assembler) {
161 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
162
163 if (is64bit) {
164 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
165 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
166
167 __ Mfc1(out_lo, in);
Alexey Frunzebb9863a2016-01-11 15:51:16 -0800168 __ MoveFromFpuHigh(out_hi, in);
Chris Larsen3f8bf652015-10-28 10:08:56 -0700169 } else {
170 Register out = locations->Out().AsRegister<Register>();
171
172 __ Mfc1(out, in);
173 }
174}
175
176// long java.lang.Double.doubleToRawLongBits(double)
177void IntrinsicLocationsBuilderMIPS::VisitDoubleDoubleToRawLongBits(HInvoke* invoke) {
178 CreateFPToIntLocations(arena_, invoke);
179}
180
181void IntrinsicCodeGeneratorMIPS::VisitDoubleDoubleToRawLongBits(HInvoke* invoke) {
Roland Levillainbf84a3d2015-12-04 14:33:02 +0000182 MoveFPToInt(invoke->GetLocations(), /* is64bit */ true, GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700183}
184
185// int java.lang.Float.floatToRawIntBits(float)
186void IntrinsicLocationsBuilderMIPS::VisitFloatFloatToRawIntBits(HInvoke* invoke) {
187 CreateFPToIntLocations(arena_, invoke);
188}
189
190void IntrinsicCodeGeneratorMIPS::VisitFloatFloatToRawIntBits(HInvoke* invoke) {
Roland Levillainbf84a3d2015-12-04 14:33:02 +0000191 MoveFPToInt(invoke->GetLocations(), /* is64bit */ false, GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700192}
193
194static void CreateIntToFPLocations(ArenaAllocator* arena, HInvoke* invoke) {
195 LocationSummary* locations = new (arena) LocationSummary(invoke,
196 LocationSummary::kNoCall,
197 kIntrinsified);
198 locations->SetInAt(0, Location::RequiresRegister());
199 locations->SetOut(Location::RequiresFpuRegister());
200}
201
202static void MoveIntToFP(LocationSummary* locations, bool is64bit, MipsAssembler* assembler) {
203 FRegister out = locations->Out().AsFpuRegister<FRegister>();
204
205 if (is64bit) {
206 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
207 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
208
209 __ Mtc1(in_lo, out);
Alexey Frunzebb9863a2016-01-11 15:51:16 -0800210 __ MoveToFpuHigh(in_hi, out);
Chris Larsen3f8bf652015-10-28 10:08:56 -0700211 } else {
212 Register in = locations->InAt(0).AsRegister<Register>();
213
214 __ Mtc1(in, out);
215 }
216}
217
218// double java.lang.Double.longBitsToDouble(long)
219void IntrinsicLocationsBuilderMIPS::VisitDoubleLongBitsToDouble(HInvoke* invoke) {
220 CreateIntToFPLocations(arena_, invoke);
221}
222
223void IntrinsicCodeGeneratorMIPS::VisitDoubleLongBitsToDouble(HInvoke* invoke) {
Roland Levillainbf84a3d2015-12-04 14:33:02 +0000224 MoveIntToFP(invoke->GetLocations(), /* is64bit */ true, GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700225}
226
227// float java.lang.Float.intBitsToFloat(int)
228void IntrinsicLocationsBuilderMIPS::VisitFloatIntBitsToFloat(HInvoke* invoke) {
229 CreateIntToFPLocations(arena_, invoke);
230}
231
232void IntrinsicCodeGeneratorMIPS::VisitFloatIntBitsToFloat(HInvoke* invoke) {
Roland Levillainbf84a3d2015-12-04 14:33:02 +0000233 MoveIntToFP(invoke->GetLocations(), /* is64bit */ false, GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700234}
235
Chris Larsen86829602015-11-18 12:27:52 -0800236static void CreateIntToIntLocations(ArenaAllocator* arena,
237 HInvoke* invoke,
238 Location::OutputOverlap overlaps = Location::kNoOutputOverlap) {
Chris Larsen3f8bf652015-10-28 10:08:56 -0700239 LocationSummary* locations = new (arena) LocationSummary(invoke,
240 LocationSummary::kNoCall,
241 kIntrinsified);
242 locations->SetInAt(0, Location::RequiresRegister());
Chris Larsen86829602015-11-18 12:27:52 -0800243 locations->SetOut(Location::RequiresRegister(), overlaps);
Chris Larsen3f8bf652015-10-28 10:08:56 -0700244}
245
Chris Larsen70014c82015-11-18 12:26:08 -0800246static void GenReverse(LocationSummary* locations,
247 Primitive::Type type,
248 bool isR2OrNewer,
249 bool isR6,
250 bool reverseBits,
251 MipsAssembler* assembler) {
Chris Larsen3f8bf652015-10-28 10:08:56 -0700252 DCHECK(type == Primitive::kPrimShort ||
253 type == Primitive::kPrimInt ||
254 type == Primitive::kPrimLong);
Chris Larsen70014c82015-11-18 12:26:08 -0800255 DCHECK(type != Primitive::kPrimShort || !reverseBits);
Chris Larsen3f8bf652015-10-28 10:08:56 -0700256
257 if (type == Primitive::kPrimShort) {
258 Register in = locations->InAt(0).AsRegister<Register>();
259 Register out = locations->Out().AsRegister<Register>();
260
261 if (isR2OrNewer) {
262 __ Wsbh(out, in);
263 __ Seh(out, out);
264 } else {
265 __ Sll(TMP, in, 24);
266 __ Sra(TMP, TMP, 16);
267 __ Sll(out, in, 16);
268 __ Srl(out, out, 24);
269 __ Or(out, out, TMP);
270 }
271 } else if (type == Primitive::kPrimInt) {
272 Register in = locations->InAt(0).AsRegister<Register>();
273 Register out = locations->Out().AsRegister<Register>();
274
275 if (isR2OrNewer) {
276 __ Rotr(out, in, 16);
277 __ Wsbh(out, out);
278 } else {
279 // MIPS32r1
280 // __ Rotr(out, in, 16);
281 __ Sll(TMP, in, 16);
282 __ Srl(out, in, 16);
283 __ Or(out, out, TMP);
284 // __ Wsbh(out, out);
285 __ LoadConst32(AT, 0x00FF00FF);
286 __ And(TMP, out, AT);
287 __ Sll(TMP, TMP, 8);
288 __ Srl(out, out, 8);
289 __ And(out, out, AT);
290 __ Or(out, out, TMP);
291 }
Chris Larsen70014c82015-11-18 12:26:08 -0800292 if (reverseBits) {
293 if (isR6) {
294 __ Bitswap(out, out);
295 } else {
296 __ LoadConst32(AT, 0x0F0F0F0F);
297 __ And(TMP, out, AT);
298 __ Sll(TMP, TMP, 4);
299 __ Srl(out, out, 4);
300 __ And(out, out, AT);
301 __ Or(out, TMP, out);
302 __ LoadConst32(AT, 0x33333333);
303 __ And(TMP, out, AT);
304 __ Sll(TMP, TMP, 2);
305 __ Srl(out, out, 2);
306 __ And(out, out, AT);
307 __ Or(out, TMP, out);
308 __ LoadConst32(AT, 0x55555555);
309 __ And(TMP, out, AT);
310 __ Sll(TMP, TMP, 1);
311 __ Srl(out, out, 1);
312 __ And(out, out, AT);
313 __ Or(out, TMP, out);
314 }
315 }
Chris Larsen3f8bf652015-10-28 10:08:56 -0700316 } else if (type == Primitive::kPrimLong) {
317 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
318 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
319 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
320 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
321
322 if (isR2OrNewer) {
323 __ Rotr(AT, in_hi, 16);
324 __ Rotr(TMP, in_lo, 16);
325 __ Wsbh(out_lo, AT);
326 __ Wsbh(out_hi, TMP);
327 } else {
328 // When calling CreateIntToIntLocations() we promised that the
329 // use of the out_lo/out_hi wouldn't overlap with the use of
330 // in_lo/in_hi. Be very careful not to write to out_lo/out_hi
331 // until we're completely done reading from in_lo/in_hi.
332 // __ Rotr(TMP, in_lo, 16);
333 __ Sll(TMP, in_lo, 16);
334 __ Srl(AT, in_lo, 16);
335 __ Or(TMP, TMP, AT); // Hold in TMP until it's safe
336 // to write to out_hi.
337 // __ Rotr(out_lo, in_hi, 16);
338 __ Sll(AT, in_hi, 16);
339 __ Srl(out_lo, in_hi, 16); // Here we are finally done reading
340 // from in_lo/in_hi so it's okay to
341 // write to out_lo/out_hi.
342 __ Or(out_lo, out_lo, AT);
343 // __ Wsbh(out_hi, out_hi);
344 __ LoadConst32(AT, 0x00FF00FF);
345 __ And(out_hi, TMP, AT);
346 __ Sll(out_hi, out_hi, 8);
347 __ Srl(TMP, TMP, 8);
348 __ And(TMP, TMP, AT);
349 __ Or(out_hi, out_hi, TMP);
350 // __ Wsbh(out_lo, out_lo);
351 __ And(TMP, out_lo, AT); // AT already holds the correct mask value
352 __ Sll(TMP, TMP, 8);
353 __ Srl(out_lo, out_lo, 8);
354 __ And(out_lo, out_lo, AT);
355 __ Or(out_lo, out_lo, TMP);
356 }
Chris Larsen70014c82015-11-18 12:26:08 -0800357 if (reverseBits) {
358 if (isR6) {
359 __ Bitswap(out_hi, out_hi);
360 __ Bitswap(out_lo, out_lo);
361 } else {
362 __ LoadConst32(AT, 0x0F0F0F0F);
363 __ And(TMP, out_hi, AT);
364 __ Sll(TMP, TMP, 4);
365 __ Srl(out_hi, out_hi, 4);
366 __ And(out_hi, out_hi, AT);
367 __ Or(out_hi, TMP, out_hi);
368 __ And(TMP, out_lo, AT);
369 __ Sll(TMP, TMP, 4);
370 __ Srl(out_lo, out_lo, 4);
371 __ And(out_lo, out_lo, AT);
372 __ Or(out_lo, TMP, out_lo);
373 __ LoadConst32(AT, 0x33333333);
374 __ And(TMP, out_hi, AT);
375 __ Sll(TMP, TMP, 2);
376 __ Srl(out_hi, out_hi, 2);
377 __ And(out_hi, out_hi, AT);
378 __ Or(out_hi, TMP, out_hi);
379 __ And(TMP, out_lo, AT);
380 __ Sll(TMP, TMP, 2);
381 __ Srl(out_lo, out_lo, 2);
382 __ And(out_lo, out_lo, AT);
383 __ Or(out_lo, TMP, out_lo);
384 __ LoadConst32(AT, 0x55555555);
385 __ And(TMP, out_hi, AT);
386 __ Sll(TMP, TMP, 1);
387 __ Srl(out_hi, out_hi, 1);
388 __ And(out_hi, out_hi, AT);
389 __ Or(out_hi, TMP, out_hi);
390 __ And(TMP, out_lo, AT);
391 __ Sll(TMP, TMP, 1);
392 __ Srl(out_lo, out_lo, 1);
393 __ And(out_lo, out_lo, AT);
394 __ Or(out_lo, TMP, out_lo);
395 }
396 }
Chris Larsen3f8bf652015-10-28 10:08:56 -0700397 }
398}
399
400// int java.lang.Integer.reverseBytes(int)
401void IntrinsicLocationsBuilderMIPS::VisitIntegerReverseBytes(HInvoke* invoke) {
402 CreateIntToIntLocations(arena_, invoke);
403}
404
405void IntrinsicCodeGeneratorMIPS::VisitIntegerReverseBytes(HInvoke* invoke) {
Chris Larsen70014c82015-11-18 12:26:08 -0800406 GenReverse(invoke->GetLocations(),
407 Primitive::kPrimInt,
Chris Larsene16ce5a2015-11-18 12:30:20 -0800408 IsR2OrNewer(),
409 IsR6(),
Chris Larsenb74353a2015-11-20 09:07:09 -0800410 /* reverseBits */ false,
Chris Larsen70014c82015-11-18 12:26:08 -0800411 GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700412}
413
414// long java.lang.Long.reverseBytes(long)
415void IntrinsicLocationsBuilderMIPS::VisitLongReverseBytes(HInvoke* invoke) {
416 CreateIntToIntLocations(arena_, invoke);
417}
418
419void IntrinsicCodeGeneratorMIPS::VisitLongReverseBytes(HInvoke* invoke) {
Chris Larsen70014c82015-11-18 12:26:08 -0800420 GenReverse(invoke->GetLocations(),
421 Primitive::kPrimLong,
Chris Larsene16ce5a2015-11-18 12:30:20 -0800422 IsR2OrNewer(),
423 IsR6(),
Chris Larsenb74353a2015-11-20 09:07:09 -0800424 /* reverseBits */ false,
Chris Larsen70014c82015-11-18 12:26:08 -0800425 GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700426}
427
428// short java.lang.Short.reverseBytes(short)
429void IntrinsicLocationsBuilderMIPS::VisitShortReverseBytes(HInvoke* invoke) {
430 CreateIntToIntLocations(arena_, invoke);
431}
432
433void IntrinsicCodeGeneratorMIPS::VisitShortReverseBytes(HInvoke* invoke) {
Chris Larsen70014c82015-11-18 12:26:08 -0800434 GenReverse(invoke->GetLocations(),
435 Primitive::kPrimShort,
Chris Larsene16ce5a2015-11-18 12:30:20 -0800436 IsR2OrNewer(),
437 IsR6(),
Chris Larsenb74353a2015-11-20 09:07:09 -0800438 /* reverseBits */ false,
Chris Larsen70014c82015-11-18 12:26:08 -0800439 GetAssembler());
440}
441
Chris Larsene3845472015-11-18 12:27:15 -0800442static void GenNumberOfLeadingZeroes(LocationSummary* locations,
443 bool is64bit,
444 bool isR6,
445 MipsAssembler* assembler) {
446 Register out = locations->Out().AsRegister<Register>();
447 if (is64bit) {
448 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
449 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
450
451 if (isR6) {
452 __ ClzR6(AT, in_hi);
453 __ ClzR6(TMP, in_lo);
454 __ Seleqz(TMP, TMP, in_hi);
455 } else {
456 __ ClzR2(AT, in_hi);
457 __ ClzR2(TMP, in_lo);
458 __ Movn(TMP, ZERO, in_hi);
459 }
460 __ Addu(out, AT, TMP);
461 } else {
462 Register in = locations->InAt(0).AsRegister<Register>();
463
464 if (isR6) {
465 __ ClzR6(out, in);
466 } else {
467 __ ClzR2(out, in);
468 }
469 }
470}
471
472// int java.lang.Integer.numberOfLeadingZeros(int i)
473void IntrinsicLocationsBuilderMIPS::VisitIntegerNumberOfLeadingZeros(HInvoke* invoke) {
474 CreateIntToIntLocations(arena_, invoke);
475}
476
477void IntrinsicCodeGeneratorMIPS::VisitIntegerNumberOfLeadingZeros(HInvoke* invoke) {
Chris Larsenb74353a2015-11-20 09:07:09 -0800478 GenNumberOfLeadingZeroes(invoke->GetLocations(), /* is64bit */ false, IsR6(), GetAssembler());
Chris Larsene3845472015-11-18 12:27:15 -0800479}
480
481// int java.lang.Long.numberOfLeadingZeros(long i)
482void IntrinsicLocationsBuilderMIPS::VisitLongNumberOfLeadingZeros(HInvoke* invoke) {
483 CreateIntToIntLocations(arena_, invoke);
484}
485
486void IntrinsicCodeGeneratorMIPS::VisitLongNumberOfLeadingZeros(HInvoke* invoke) {
Chris Larsenb74353a2015-11-20 09:07:09 -0800487 GenNumberOfLeadingZeroes(invoke->GetLocations(), /* is64bit */ true, IsR6(), GetAssembler());
Chris Larsene3845472015-11-18 12:27:15 -0800488}
489
Chris Larsen86829602015-11-18 12:27:52 -0800490static void GenNumberOfTrailingZeroes(LocationSummary* locations,
491 bool is64bit,
492 bool isR6,
493 bool isR2OrNewer,
494 MipsAssembler* assembler) {
495 Register out = locations->Out().AsRegister<Register>();
496 Register in_lo;
497 Register in;
498
499 if (is64bit) {
Chris Larsen86829602015-11-18 12:27:52 -0800500 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
501
502 in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
503
504 // If in_lo is zero then count the number of trailing zeroes in in_hi;
505 // otherwise count the number of trailing zeroes in in_lo.
506 // AT = in_lo ? in_lo : in_hi;
507 if (isR6) {
508 __ Seleqz(out, in_hi, in_lo);
509 __ Selnez(TMP, in_lo, in_lo);
510 __ Or(out, out, TMP);
511 } else {
512 __ Movz(out, in_hi, in_lo);
513 __ Movn(out, in_lo, in_lo);
514 }
515
516 in = out;
517 } else {
518 in = locations->InAt(0).AsRegister<Register>();
519 // Give in_lo a dummy value to keep the compiler from complaining.
520 // Since we only get here in the 32-bit case, this value will never
521 // be used.
522 in_lo = in;
523 }
524
525 // We don't have an instruction to count the number of trailing zeroes.
526 // Start by flipping the bits end-for-end so we can count the number of
527 // leading zeroes instead.
528 if (isR2OrNewer) {
529 __ Rotr(out, in, 16);
530 __ Wsbh(out, out);
531 } else {
532 // MIPS32r1
533 // __ Rotr(out, in, 16);
534 __ Sll(TMP, in, 16);
535 __ Srl(out, in, 16);
536 __ Or(out, out, TMP);
537 // __ Wsbh(out, out);
538 __ LoadConst32(AT, 0x00FF00FF);
539 __ And(TMP, out, AT);
540 __ Sll(TMP, TMP, 8);
541 __ Srl(out, out, 8);
542 __ And(out, out, AT);
543 __ Or(out, out, TMP);
544 }
545
546 if (isR6) {
547 __ Bitswap(out, out);
548 __ ClzR6(out, out);
549 } else {
550 __ LoadConst32(AT, 0x0F0F0F0F);
551 __ And(TMP, out, AT);
552 __ Sll(TMP, TMP, 4);
553 __ Srl(out, out, 4);
554 __ And(out, out, AT);
555 __ Or(out, TMP, out);
556 __ LoadConst32(AT, 0x33333333);
557 __ And(TMP, out, AT);
558 __ Sll(TMP, TMP, 2);
559 __ Srl(out, out, 2);
560 __ And(out, out, AT);
561 __ Or(out, TMP, out);
562 __ LoadConst32(AT, 0x55555555);
563 __ And(TMP, out, AT);
564 __ Sll(TMP, TMP, 1);
565 __ Srl(out, out, 1);
566 __ And(out, out, AT);
567 __ Or(out, TMP, out);
568 __ ClzR2(out, out);
569 }
570
571 if (is64bit) {
572 // If in_lo is zero, then we counted the number of trailing zeroes in in_hi so we must add the
573 // number of trailing zeroes in in_lo (32) to get the correct final count
574 __ LoadConst32(TMP, 32);
575 if (isR6) {
576 __ Seleqz(TMP, TMP, in_lo);
577 } else {
578 __ Movn(TMP, ZERO, in_lo);
579 }
580 __ Addu(out, out, TMP);
581 }
582}
583
584// int java.lang.Integer.numberOfTrailingZeros(int i)
585void IntrinsicLocationsBuilderMIPS::VisitIntegerNumberOfTrailingZeros(HInvoke* invoke) {
586 CreateIntToIntLocations(arena_, invoke, Location::kOutputOverlap);
587}
588
589void IntrinsicCodeGeneratorMIPS::VisitIntegerNumberOfTrailingZeros(HInvoke* invoke) {
Chris Larsenb74353a2015-11-20 09:07:09 -0800590 GenNumberOfTrailingZeroes(invoke->GetLocations(),
591 /* is64bit */ false,
592 IsR6(),
593 IsR2OrNewer(),
594 GetAssembler());
Chris Larsen86829602015-11-18 12:27:52 -0800595}
596
597// int java.lang.Long.numberOfTrailingZeros(long i)
598void IntrinsicLocationsBuilderMIPS::VisitLongNumberOfTrailingZeros(HInvoke* invoke) {
599 CreateIntToIntLocations(arena_, invoke, Location::kOutputOverlap);
600}
601
602void IntrinsicCodeGeneratorMIPS::VisitLongNumberOfTrailingZeros(HInvoke* invoke) {
Chris Larsenb74353a2015-11-20 09:07:09 -0800603 GenNumberOfTrailingZeroes(invoke->GetLocations(),
604 /* is64bit */ true,
605 IsR6(),
606 IsR2OrNewer(),
607 GetAssembler());
Chris Larsene16ce5a2015-11-18 12:30:20 -0800608}
609
Chris Larsen70014c82015-11-18 12:26:08 -0800610// int java.lang.Integer.reverse(int)
611void IntrinsicLocationsBuilderMIPS::VisitIntegerReverse(HInvoke* invoke) {
612 CreateIntToIntLocations(arena_, invoke);
613}
614
615void IntrinsicCodeGeneratorMIPS::VisitIntegerReverse(HInvoke* invoke) {
616 GenReverse(invoke->GetLocations(),
617 Primitive::kPrimInt,
Chris Larsene16ce5a2015-11-18 12:30:20 -0800618 IsR2OrNewer(),
619 IsR6(),
Chris Larsenb74353a2015-11-20 09:07:09 -0800620 /* reverseBits */ true,
Chris Larsen70014c82015-11-18 12:26:08 -0800621 GetAssembler());
622}
623
624// long java.lang.Long.reverse(long)
625void IntrinsicLocationsBuilderMIPS::VisitLongReverse(HInvoke* invoke) {
626 CreateIntToIntLocations(arena_, invoke);
627}
628
629void IntrinsicCodeGeneratorMIPS::VisitLongReverse(HInvoke* invoke) {
630 GenReverse(invoke->GetLocations(),
631 Primitive::kPrimLong,
Chris Larsene16ce5a2015-11-18 12:30:20 -0800632 IsR2OrNewer(),
633 IsR6(),
Chris Larsenb74353a2015-11-20 09:07:09 -0800634 /* reverseBits */ true,
Chris Larsen70014c82015-11-18 12:26:08 -0800635 GetAssembler());
Chris Larsen3f8bf652015-10-28 10:08:56 -0700636}
637
Chris Larsenb74353a2015-11-20 09:07:09 -0800638static void CreateFPToFPLocations(ArenaAllocator* arena, HInvoke* invoke) {
639 LocationSummary* locations = new (arena) LocationSummary(invoke,
640 LocationSummary::kNoCall,
641 kIntrinsified);
642 locations->SetInAt(0, Location::RequiresFpuRegister());
643 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
644}
645
Chris Larsenedc16452016-02-12 17:59:00 -0800646static void GenBitCount(LocationSummary* locations,
647 Primitive::Type type,
648 bool isR6,
649 MipsAssembler* assembler) {
650 DCHECK(type == Primitive::kPrimInt || type == Primitive::kPrimLong);
651
652 Register out = locations->Out().AsRegister<Register>();
653
654 // https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
655 //
656 // A generalization of the best bit counting method to integers of
657 // bit-widths up to 128 (parameterized by type T) is this:
658 //
659 // v = v - ((v >> 1) & (T)~(T)0/3); // temp
660 // v = (v & (T)~(T)0/15*3) + ((v >> 2) & (T)~(T)0/15*3); // temp
661 // v = (v + (v >> 4)) & (T)~(T)0/255*15; // temp
662 // c = (T)(v * ((T)~(T)0/255)) >> (sizeof(T) - 1) * BITS_PER_BYTE; // count
663 //
664 // For comparison, for 32-bit quantities, this algorithm can be executed
665 // using 20 MIPS instructions (the calls to LoadConst32() generate two
666 // machine instructions each for the values being used in this algorithm).
667 // A(n unrolled) loop-based algorithm required 25 instructions.
668 //
669 // For 64-bit quantities, this algorithm gets executed twice, (once
670 // for in_lo, and again for in_hi), but saves a few instructions
671 // because the mask values only have to be loaded once. Using this
672 // algorithm the count for a 64-bit operand can be performed in 33
673 // instructions compared to a loop-based algorithm which required 47
674 // instructions.
675
676 if (type == Primitive::kPrimInt) {
677 Register in = locations->InAt(0).AsRegister<Register>();
678
679 __ Srl(TMP, in, 1);
680 __ LoadConst32(AT, 0x55555555);
681 __ And(TMP, TMP, AT);
682 __ Subu(TMP, in, TMP);
683 __ LoadConst32(AT, 0x33333333);
684 __ And(out, TMP, AT);
685 __ Srl(TMP, TMP, 2);
686 __ And(TMP, TMP, AT);
687 __ Addu(TMP, out, TMP);
688 __ Srl(out, TMP, 4);
689 __ Addu(out, out, TMP);
690 __ LoadConst32(AT, 0x0F0F0F0F);
691 __ And(out, out, AT);
692 __ LoadConst32(TMP, 0x01010101);
693 if (isR6) {
694 __ MulR6(out, out, TMP);
695 } else {
696 __ MulR2(out, out, TMP);
697 }
698 __ Srl(out, out, 24);
699 } else if (type == Primitive::kPrimLong) {
700 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
701 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
702 Register tmp_hi = locations->GetTemp(0).AsRegister<Register>();
703 Register out_hi = locations->GetTemp(1).AsRegister<Register>();
704 Register tmp_lo = TMP;
705 Register out_lo = out;
706
707 __ Srl(tmp_lo, in_lo, 1);
708 __ Srl(tmp_hi, in_hi, 1);
709
710 __ LoadConst32(AT, 0x55555555);
711
712 __ And(tmp_lo, tmp_lo, AT);
713 __ Subu(tmp_lo, in_lo, tmp_lo);
714
715 __ And(tmp_hi, tmp_hi, AT);
716 __ Subu(tmp_hi, in_hi, tmp_hi);
717
718 __ LoadConst32(AT, 0x33333333);
719
720 __ And(out_lo, tmp_lo, AT);
721 __ Srl(tmp_lo, tmp_lo, 2);
722 __ And(tmp_lo, tmp_lo, AT);
723 __ Addu(tmp_lo, out_lo, tmp_lo);
724 __ Srl(out_lo, tmp_lo, 4);
725 __ Addu(out_lo, out_lo, tmp_lo);
726
727 __ And(out_hi, tmp_hi, AT);
728 __ Srl(tmp_hi, tmp_hi, 2);
729 __ And(tmp_hi, tmp_hi, AT);
730 __ Addu(tmp_hi, out_hi, tmp_hi);
731 __ Srl(out_hi, tmp_hi, 4);
732 __ Addu(out_hi, out_hi, tmp_hi);
733
734 __ LoadConst32(AT, 0x0F0F0F0F);
735
736 __ And(out_lo, out_lo, AT);
737 __ And(out_hi, out_hi, AT);
738
739 __ LoadConst32(AT, 0x01010101);
740
741 if (isR6) {
742 __ MulR6(out_lo, out_lo, AT);
743
744 __ MulR6(out_hi, out_hi, AT);
745 } else {
746 __ MulR2(out_lo, out_lo, AT);
747
748 __ MulR2(out_hi, out_hi, AT);
749 }
750
751 __ Srl(out_lo, out_lo, 24);
752 __ Srl(out_hi, out_hi, 24);
753
754 __ Addu(out, out_hi, out_lo);
755 }
756}
757
758// int java.lang.Integer.bitCount(int)
759void IntrinsicLocationsBuilderMIPS::VisitIntegerBitCount(HInvoke* invoke) {
760 CreateIntToIntLocations(arena_, invoke);
761}
762
763void IntrinsicCodeGeneratorMIPS::VisitIntegerBitCount(HInvoke* invoke) {
764 GenBitCount(invoke->GetLocations(), Primitive::kPrimInt, IsR6(), GetAssembler());
765}
766
767// int java.lang.Long.bitCount(int)
768void IntrinsicLocationsBuilderMIPS::VisitLongBitCount(HInvoke* invoke) {
769 LocationSummary* locations = new (arena_) LocationSummary(invoke,
770 LocationSummary::kNoCall,
771 kIntrinsified);
772 locations->SetInAt(0, Location::RequiresRegister());
773 locations->SetOut(Location::RequiresRegister());
774 locations->AddTemp(Location::RequiresRegister());
775 locations->AddTemp(Location::RequiresRegister());
776}
777
778void IntrinsicCodeGeneratorMIPS::VisitLongBitCount(HInvoke* invoke) {
779 GenBitCount(invoke->GetLocations(), Primitive::kPrimLong, IsR6(), GetAssembler());
780}
781
Chris Larsenb74353a2015-11-20 09:07:09 -0800782static void MathAbsFP(LocationSummary* locations, bool is64bit, MipsAssembler* assembler) {
783 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
784 FRegister out = locations->Out().AsFpuRegister<FRegister>();
785
786 if (is64bit) {
787 __ AbsD(out, in);
788 } else {
789 __ AbsS(out, in);
790 }
791}
792
793// double java.lang.Math.abs(double)
794void IntrinsicLocationsBuilderMIPS::VisitMathAbsDouble(HInvoke* invoke) {
795 CreateFPToFPLocations(arena_, invoke);
796}
797
798void IntrinsicCodeGeneratorMIPS::VisitMathAbsDouble(HInvoke* invoke) {
799 MathAbsFP(invoke->GetLocations(), /* is64bit */ true, GetAssembler());
800}
801
802// float java.lang.Math.abs(float)
803void IntrinsicLocationsBuilderMIPS::VisitMathAbsFloat(HInvoke* invoke) {
804 CreateFPToFPLocations(arena_, invoke);
805}
806
807void IntrinsicCodeGeneratorMIPS::VisitMathAbsFloat(HInvoke* invoke) {
808 MathAbsFP(invoke->GetLocations(), /* is64bit */ false, GetAssembler());
809}
810
811static void GenAbsInteger(LocationSummary* locations, bool is64bit, MipsAssembler* assembler) {
812 if (is64bit) {
813 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>();
814 Register in_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
815 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
816 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
817
818 // The comments in this section show the analogous operations which would
819 // be performed if we had 64-bit registers "in", and "out".
820 // __ Dsra32(AT, in, 31);
821 __ Sra(AT, in_hi, 31);
822 // __ Xor(out, in, AT);
823 __ Xor(TMP, in_lo, AT);
824 __ Xor(out_hi, in_hi, AT);
825 // __ Dsubu(out, out, AT);
826 __ Subu(out_lo, TMP, AT);
827 __ Sltu(TMP, out_lo, TMP);
828 __ Addu(out_hi, out_hi, TMP);
829 } else {
830 Register in = locations->InAt(0).AsRegister<Register>();
831 Register out = locations->Out().AsRegister<Register>();
832
833 __ Sra(AT, in, 31);
834 __ Xor(out, in, AT);
835 __ Subu(out, out, AT);
836 }
837}
838
839// int java.lang.Math.abs(int)
840void IntrinsicLocationsBuilderMIPS::VisitMathAbsInt(HInvoke* invoke) {
841 CreateIntToIntLocations(arena_, invoke);
842}
843
844void IntrinsicCodeGeneratorMIPS::VisitMathAbsInt(HInvoke* invoke) {
845 GenAbsInteger(invoke->GetLocations(), /* is64bit */ false, GetAssembler());
846}
847
848// long java.lang.Math.abs(long)
849void IntrinsicLocationsBuilderMIPS::VisitMathAbsLong(HInvoke* invoke) {
850 CreateIntToIntLocations(arena_, invoke);
851}
852
853void IntrinsicCodeGeneratorMIPS::VisitMathAbsLong(HInvoke* invoke) {
854 GenAbsInteger(invoke->GetLocations(), /* is64bit */ true, GetAssembler());
855}
856
857static void GenMinMaxFP(LocationSummary* locations,
858 bool is_min,
859 Primitive::Type type,
860 bool is_R6,
861 MipsAssembler* assembler) {
862 FRegister out = locations->Out().AsFpuRegister<FRegister>();
863 FRegister a = locations->InAt(0).AsFpuRegister<FRegister>();
864 FRegister b = locations->InAt(1).AsFpuRegister<FRegister>();
865
866 if (is_R6) {
867 MipsLabel noNaNs;
868 MipsLabel done;
869 FRegister ftmp = ((out != a) && (out != b)) ? out : FTMP;
870
871 // When Java computes min/max it prefers a NaN to a number; the
872 // behavior of MIPSR6 is to prefer numbers to NaNs, i.e., if one of
873 // the inputs is a NaN and the other is a valid number, the MIPS
874 // instruction will return the number; Java wants the NaN value
875 // returned. This is why there is extra logic preceding the use of
876 // the MIPS min.fmt/max.fmt instructions. If either a, or b holds a
877 // NaN, return the NaN, otherwise return the min/max.
878 if (type == Primitive::kPrimDouble) {
879 __ CmpUnD(FTMP, a, b);
880 __ Bc1eqz(FTMP, &noNaNs);
881
882 // One of the inputs is a NaN
883 __ CmpEqD(ftmp, a, a);
884 // If a == a then b is the NaN, otherwise a is the NaN.
885 __ SelD(ftmp, a, b);
886
887 if (ftmp != out) {
888 __ MovD(out, ftmp);
889 }
890
891 __ B(&done);
892
893 __ Bind(&noNaNs);
894
895 if (is_min) {
896 __ MinD(out, a, b);
897 } else {
898 __ MaxD(out, a, b);
899 }
900 } else {
901 DCHECK_EQ(type, Primitive::kPrimFloat);
902 __ CmpUnS(FTMP, a, b);
903 __ Bc1eqz(FTMP, &noNaNs);
904
905 // One of the inputs is a NaN
906 __ CmpEqS(ftmp, a, a);
907 // If a == a then b is the NaN, otherwise a is the NaN.
908 __ SelS(ftmp, a, b);
909
910 if (ftmp != out) {
911 __ MovS(out, ftmp);
912 }
913
914 __ B(&done);
915
916 __ Bind(&noNaNs);
917
918 if (is_min) {
919 __ MinS(out, a, b);
920 } else {
921 __ MaxS(out, a, b);
922 }
923 }
924
925 __ Bind(&done);
926 } else {
927 MipsLabel ordered;
928 MipsLabel compare;
929 MipsLabel select;
930 MipsLabel done;
931
932 if (type == Primitive::kPrimDouble) {
933 __ CunD(a, b);
934 } else {
935 DCHECK_EQ(type, Primitive::kPrimFloat);
936 __ CunS(a, b);
937 }
938 __ Bc1f(&ordered);
939
940 // a or b (or both) is a NaN. Return one, which is a NaN.
941 if (type == Primitive::kPrimDouble) {
942 __ CeqD(b, b);
943 } else {
944 __ CeqS(b, b);
945 }
946 __ B(&select);
947
948 __ Bind(&ordered);
949
950 // Neither is a NaN.
951 // a == b? (-0.0 compares equal with +0.0)
952 // If equal, handle zeroes, else compare further.
953 if (type == Primitive::kPrimDouble) {
954 __ CeqD(a, b);
955 } else {
956 __ CeqS(a, b);
957 }
958 __ Bc1f(&compare);
959
960 // a == b either bit for bit or one is -0.0 and the other is +0.0.
961 if (type == Primitive::kPrimDouble) {
962 __ MoveFromFpuHigh(TMP, a);
963 __ MoveFromFpuHigh(AT, b);
964 } else {
965 __ Mfc1(TMP, a);
966 __ Mfc1(AT, b);
967 }
968
969 if (is_min) {
970 // -0.0 prevails over +0.0.
971 __ Or(TMP, TMP, AT);
972 } else {
973 // +0.0 prevails over -0.0.
974 __ And(TMP, TMP, AT);
975 }
976
977 if (type == Primitive::kPrimDouble) {
978 __ Mfc1(AT, a);
979 __ Mtc1(AT, out);
980 __ MoveToFpuHigh(TMP, out);
981 } else {
982 __ Mtc1(TMP, out);
983 }
984 __ B(&done);
985
986 __ Bind(&compare);
987
988 if (type == Primitive::kPrimDouble) {
989 if (is_min) {
990 // return (a <= b) ? a : b;
991 __ ColeD(a, b);
992 } else {
993 // return (a >= b) ? a : b;
994 __ ColeD(b, a); // b <= a
995 }
996 } else {
997 if (is_min) {
998 // return (a <= b) ? a : b;
999 __ ColeS(a, b);
1000 } else {
1001 // return (a >= b) ? a : b;
1002 __ ColeS(b, a); // b <= a
1003 }
1004 }
1005
1006 __ Bind(&select);
1007
1008 if (type == Primitive::kPrimDouble) {
1009 __ MovtD(out, a);
1010 __ MovfD(out, b);
1011 } else {
1012 __ MovtS(out, a);
1013 __ MovfS(out, b);
1014 }
1015
1016 __ Bind(&done);
1017 }
1018}
1019
1020static void CreateFPFPToFPLocations(ArenaAllocator* arena, HInvoke* invoke) {
1021 LocationSummary* locations = new (arena) LocationSummary(invoke,
1022 LocationSummary::kNoCall,
1023 kIntrinsified);
1024 locations->SetInAt(0, Location::RequiresFpuRegister());
1025 locations->SetInAt(1, Location::RequiresFpuRegister());
1026 locations->SetOut(Location::RequiresFpuRegister(), Location::kOutputOverlap);
1027}
1028
1029// double java.lang.Math.min(double, double)
1030void IntrinsicLocationsBuilderMIPS::VisitMathMinDoubleDouble(HInvoke* invoke) {
1031 CreateFPFPToFPLocations(arena_, invoke);
1032}
1033
1034void IntrinsicCodeGeneratorMIPS::VisitMathMinDoubleDouble(HInvoke* invoke) {
1035 GenMinMaxFP(invoke->GetLocations(),
1036 /* is_min */ true,
1037 Primitive::kPrimDouble,
1038 IsR6(),
1039 GetAssembler());
1040}
1041
1042// float java.lang.Math.min(float, float)
1043void IntrinsicLocationsBuilderMIPS::VisitMathMinFloatFloat(HInvoke* invoke) {
1044 CreateFPFPToFPLocations(arena_, invoke);
1045}
1046
1047void IntrinsicCodeGeneratorMIPS::VisitMathMinFloatFloat(HInvoke* invoke) {
1048 GenMinMaxFP(invoke->GetLocations(),
1049 /* is_min */ true,
1050 Primitive::kPrimFloat,
1051 IsR6(),
1052 GetAssembler());
1053}
1054
1055// double java.lang.Math.max(double, double)
1056void IntrinsicLocationsBuilderMIPS::VisitMathMaxDoubleDouble(HInvoke* invoke) {
1057 CreateFPFPToFPLocations(arena_, invoke);
1058}
1059
1060void IntrinsicCodeGeneratorMIPS::VisitMathMaxDoubleDouble(HInvoke* invoke) {
1061 GenMinMaxFP(invoke->GetLocations(),
1062 /* is_min */ false,
1063 Primitive::kPrimDouble,
1064 IsR6(),
1065 GetAssembler());
1066}
1067
1068// float java.lang.Math.max(float, float)
1069void IntrinsicLocationsBuilderMIPS::VisitMathMaxFloatFloat(HInvoke* invoke) {
1070 CreateFPFPToFPLocations(arena_, invoke);
1071}
1072
1073void IntrinsicCodeGeneratorMIPS::VisitMathMaxFloatFloat(HInvoke* invoke) {
1074 GenMinMaxFP(invoke->GetLocations(),
1075 /* is_min */ false,
1076 Primitive::kPrimFloat,
1077 IsR6(),
1078 GetAssembler());
1079}
1080
1081static void CreateIntIntToIntLocations(ArenaAllocator* arena, HInvoke* invoke) {
1082 LocationSummary* locations = new (arena) LocationSummary(invoke,
1083 LocationSummary::kNoCall,
1084 kIntrinsified);
1085 locations->SetInAt(0, Location::RequiresRegister());
1086 locations->SetInAt(1, Location::RequiresRegister());
1087 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1088}
1089
1090static void GenMinMax(LocationSummary* locations,
1091 bool is_min,
1092 Primitive::Type type,
1093 bool is_R6,
1094 MipsAssembler* assembler) {
1095 if (is_R6) {
1096 // Some architectures, such as ARM and MIPS (prior to r6), have a
1097 // conditional move instruction which only changes the target
1098 // (output) register if the condition is true (MIPS prior to r6 had
1099 // MOVF, MOVT, MOVN, and MOVZ). The SELEQZ and SELNEZ instructions
1100 // always change the target (output) register. If the condition is
1101 // true the output register gets the contents of the "rs" register;
1102 // otherwise, the output register is set to zero. One consequence
1103 // of this is that to implement something like "rd = c==0 ? rs : rt"
1104 // MIPS64r6 needs to use a pair of SELEQZ/SELNEZ instructions.
1105 // After executing this pair of instructions one of the output
1106 // registers from the pair will necessarily contain zero. Then the
1107 // code ORs the output registers from the SELEQZ/SELNEZ instructions
1108 // to get the final result.
1109 //
1110 // The initial test to see if the output register is same as the
1111 // first input register is needed to make sure that value in the
1112 // first input register isn't clobbered before we've finished
1113 // computing the output value. The logic in the corresponding else
1114 // clause performs the same task but makes sure the second input
1115 // register isn't clobbered in the event that it's the same register
1116 // as the output register; the else clause also handles the case
1117 // where the output register is distinct from both the first, and the
1118 // second input registers.
1119 if (type == Primitive::kPrimLong) {
1120 Register a_lo = locations->InAt(0).AsRegisterPairLow<Register>();
1121 Register a_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
1122 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>();
1123 Register b_hi = locations->InAt(1).AsRegisterPairHigh<Register>();
1124 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1125 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1126
1127 MipsLabel compare_done;
1128
1129 if (a_lo == b_lo) {
1130 if (out_lo != a_lo) {
1131 __ Move(out_lo, a_lo);
1132 __ Move(out_hi, a_hi);
1133 }
1134 } else {
1135 __ Slt(TMP, b_hi, a_hi);
1136 __ Bne(b_hi, a_hi, &compare_done);
1137
1138 __ Sltu(TMP, b_lo, a_lo);
1139
1140 __ Bind(&compare_done);
1141
1142 if (is_min) {
1143 __ Seleqz(AT, a_lo, TMP);
1144 __ Selnez(out_lo, b_lo, TMP); // Safe even if out_lo == a_lo/b_lo
1145 // because at this point we're
1146 // done using a_lo/b_lo.
1147 } else {
1148 __ Selnez(AT, a_lo, TMP);
1149 __ Seleqz(out_lo, b_lo, TMP); // ditto
1150 }
1151 __ Or(out_lo, out_lo, AT);
1152 if (is_min) {
1153 __ Seleqz(AT, a_hi, TMP);
1154 __ Selnez(out_hi, b_hi, TMP); // ditto but for out_hi & a_hi/b_hi
1155 } else {
1156 __ Selnez(AT, a_hi, TMP);
1157 __ Seleqz(out_hi, b_hi, TMP); // ditto but for out_hi & a_hi/b_hi
1158 }
1159 __ Or(out_hi, out_hi, AT);
1160 }
1161 } else {
1162 DCHECK_EQ(type, Primitive::kPrimInt);
1163 Register a = locations->InAt(0).AsRegister<Register>();
1164 Register b = locations->InAt(1).AsRegister<Register>();
1165 Register out = locations->Out().AsRegister<Register>();
1166
1167 if (a == b) {
1168 if (out != a) {
1169 __ Move(out, a);
1170 }
1171 } else {
1172 __ Slt(AT, b, a);
1173 if (is_min) {
1174 __ Seleqz(TMP, a, AT);
1175 __ Selnez(AT, b, AT);
1176 } else {
1177 __ Selnez(TMP, a, AT);
1178 __ Seleqz(AT, b, AT);
1179 }
1180 __ Or(out, TMP, AT);
1181 }
1182 }
1183 } else {
1184 if (type == Primitive::kPrimLong) {
1185 Register a_lo = locations->InAt(0).AsRegisterPairLow<Register>();
1186 Register a_hi = locations->InAt(0).AsRegisterPairHigh<Register>();
1187 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>();
1188 Register b_hi = locations->InAt(1).AsRegisterPairHigh<Register>();
1189 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1190 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1191
1192 MipsLabel compare_done;
1193
1194 if (a_lo == b_lo) {
1195 if (out_lo != a_lo) {
1196 __ Move(out_lo, a_lo);
1197 __ Move(out_hi, a_hi);
1198 }
1199 } else {
1200 __ Slt(TMP, a_hi, b_hi);
1201 __ Bne(a_hi, b_hi, &compare_done);
1202
1203 __ Sltu(TMP, a_lo, b_lo);
1204
1205 __ Bind(&compare_done);
1206
1207 if (is_min) {
1208 if (out_lo != a_lo) {
1209 __ Movn(out_hi, a_hi, TMP);
1210 __ Movn(out_lo, a_lo, TMP);
1211 }
1212 if (out_lo != b_lo) {
1213 __ Movz(out_hi, b_hi, TMP);
1214 __ Movz(out_lo, b_lo, TMP);
1215 }
1216 } else {
1217 if (out_lo != a_lo) {
1218 __ Movz(out_hi, a_hi, TMP);
1219 __ Movz(out_lo, a_lo, TMP);
1220 }
1221 if (out_lo != b_lo) {
1222 __ Movn(out_hi, b_hi, TMP);
1223 __ Movn(out_lo, b_lo, TMP);
1224 }
1225 }
1226 }
1227 } else {
1228 DCHECK_EQ(type, Primitive::kPrimInt);
1229 Register a = locations->InAt(0).AsRegister<Register>();
1230 Register b = locations->InAt(1).AsRegister<Register>();
1231 Register out = locations->Out().AsRegister<Register>();
1232
1233 if (a == b) {
1234 if (out != a) {
1235 __ Move(out, a);
1236 }
1237 } else {
1238 __ Slt(AT, a, b);
1239 if (is_min) {
1240 if (out != a) {
1241 __ Movn(out, a, AT);
1242 }
1243 if (out != b) {
1244 __ Movz(out, b, AT);
1245 }
1246 } else {
1247 if (out != a) {
1248 __ Movz(out, a, AT);
1249 }
1250 if (out != b) {
1251 __ Movn(out, b, AT);
1252 }
1253 }
1254 }
1255 }
1256 }
1257}
1258
1259// int java.lang.Math.min(int, int)
1260void IntrinsicLocationsBuilderMIPS::VisitMathMinIntInt(HInvoke* invoke) {
1261 CreateIntIntToIntLocations(arena_, invoke);
1262}
1263
1264void IntrinsicCodeGeneratorMIPS::VisitMathMinIntInt(HInvoke* invoke) {
1265 GenMinMax(invoke->GetLocations(),
1266 /* is_min */ true,
1267 Primitive::kPrimInt,
1268 IsR6(),
1269 GetAssembler());
1270}
1271
1272// long java.lang.Math.min(long, long)
1273void IntrinsicLocationsBuilderMIPS::VisitMathMinLongLong(HInvoke* invoke) {
1274 CreateIntIntToIntLocations(arena_, invoke);
1275}
1276
1277void IntrinsicCodeGeneratorMIPS::VisitMathMinLongLong(HInvoke* invoke) {
1278 GenMinMax(invoke->GetLocations(),
1279 /* is_min */ true,
1280 Primitive::kPrimLong,
1281 IsR6(),
1282 GetAssembler());
1283}
1284
1285// int java.lang.Math.max(int, int)
1286void IntrinsicLocationsBuilderMIPS::VisitMathMaxIntInt(HInvoke* invoke) {
1287 CreateIntIntToIntLocations(arena_, invoke);
1288}
1289
1290void IntrinsicCodeGeneratorMIPS::VisitMathMaxIntInt(HInvoke* invoke) {
1291 GenMinMax(invoke->GetLocations(),
1292 /* is_min */ false,
1293 Primitive::kPrimInt,
1294 IsR6(),
1295 GetAssembler());
1296}
1297
1298// long java.lang.Math.max(long, long)
1299void IntrinsicLocationsBuilderMIPS::VisitMathMaxLongLong(HInvoke* invoke) {
1300 CreateIntIntToIntLocations(arena_, invoke);
1301}
1302
1303void IntrinsicCodeGeneratorMIPS::VisitMathMaxLongLong(HInvoke* invoke) {
1304 GenMinMax(invoke->GetLocations(),
1305 /* is_min */ false,
1306 Primitive::kPrimLong,
1307 IsR6(),
1308 GetAssembler());
1309}
1310
1311// double java.lang.Math.sqrt(double)
1312void IntrinsicLocationsBuilderMIPS::VisitMathSqrt(HInvoke* invoke) {
1313 CreateFPToFPLocations(arena_, invoke);
1314}
1315
1316void IntrinsicCodeGeneratorMIPS::VisitMathSqrt(HInvoke* invoke) {
1317 LocationSummary* locations = invoke->GetLocations();
1318 MipsAssembler* assembler = GetAssembler();
1319 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
1320 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1321
1322 __ SqrtD(out, in);
1323}
1324
Chris Larsen3acee732015-11-18 13:31:08 -08001325// byte libcore.io.Memory.peekByte(long address)
1326void IntrinsicLocationsBuilderMIPS::VisitMemoryPeekByte(HInvoke* invoke) {
1327 CreateIntToIntLocations(arena_, invoke);
1328}
1329
1330void IntrinsicCodeGeneratorMIPS::VisitMemoryPeekByte(HInvoke* invoke) {
1331 MipsAssembler* assembler = GetAssembler();
1332 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1333 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1334
1335 __ Lb(out, adr, 0);
1336}
1337
1338// short libcore.io.Memory.peekShort(long address)
1339void IntrinsicLocationsBuilderMIPS::VisitMemoryPeekShortNative(HInvoke* invoke) {
1340 CreateIntToIntLocations(arena_, invoke);
1341}
1342
1343void IntrinsicCodeGeneratorMIPS::VisitMemoryPeekShortNative(HInvoke* invoke) {
1344 MipsAssembler* assembler = GetAssembler();
1345 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1346 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1347
1348 if (IsR6()) {
1349 __ Lh(out, adr, 0);
1350 } else if (IsR2OrNewer()) {
1351 // Unlike for words, there are no lhl/lhr instructions to load
1352 // unaligned halfwords so the code loads individual bytes, in case
1353 // the address isn't halfword-aligned, and assembles them into a
1354 // signed halfword.
1355 __ Lb(AT, adr, 1); // This byte must be sign-extended.
1356 __ Lb(out, adr, 0); // This byte can be either sign-extended, or
1357 // zero-extended because the following
1358 // instruction overwrites the sign bits.
1359 __ Ins(out, AT, 8, 24);
1360 } else {
1361 __ Lbu(AT, adr, 0); // This byte must be zero-extended. If it's not
1362 // the "or" instruction below will destroy the upper
1363 // 24 bits of the final result.
1364 __ Lb(out, adr, 1); // This byte must be sign-extended.
1365 __ Sll(out, out, 8);
1366 __ Or(out, out, AT);
1367 }
1368}
1369
1370// int libcore.io.Memory.peekInt(long address)
1371void IntrinsicLocationsBuilderMIPS::VisitMemoryPeekIntNative(HInvoke* invoke) {
1372 CreateIntToIntLocations(arena_, invoke, Location::kOutputOverlap);
1373}
1374
1375void IntrinsicCodeGeneratorMIPS::VisitMemoryPeekIntNative(HInvoke* invoke) {
1376 MipsAssembler* assembler = GetAssembler();
1377 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1378 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1379
1380 if (IsR6()) {
1381 __ Lw(out, adr, 0);
1382 } else {
1383 __ Lwr(out, adr, 0);
1384 __ Lwl(out, adr, 3);
1385 }
1386}
1387
1388// long libcore.io.Memory.peekLong(long address)
1389void IntrinsicLocationsBuilderMIPS::VisitMemoryPeekLongNative(HInvoke* invoke) {
1390 CreateIntToIntLocations(arena_, invoke, Location::kOutputOverlap);
1391}
1392
1393void IntrinsicCodeGeneratorMIPS::VisitMemoryPeekLongNative(HInvoke* invoke) {
1394 MipsAssembler* assembler = GetAssembler();
1395 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1396 Register out_lo = invoke->GetLocations()->Out().AsRegisterPairLow<Register>();
1397 Register out_hi = invoke->GetLocations()->Out().AsRegisterPairHigh<Register>();
1398
1399 if (IsR6()) {
1400 __ Lw(out_lo, adr, 0);
1401 __ Lw(out_hi, adr, 4);
1402 } else {
1403 __ Lwr(out_lo, adr, 0);
1404 __ Lwl(out_lo, adr, 3);
1405 __ Lwr(out_hi, adr, 4);
1406 __ Lwl(out_hi, adr, 7);
1407 }
1408}
1409
1410static void CreateIntIntToVoidLocations(ArenaAllocator* arena, HInvoke* invoke) {
1411 LocationSummary* locations = new (arena) LocationSummary(invoke,
1412 LocationSummary::kNoCall,
1413 kIntrinsified);
1414 locations->SetInAt(0, Location::RequiresRegister());
1415 locations->SetInAt(1, Location::RequiresRegister());
1416}
1417
1418// void libcore.io.Memory.pokeByte(long address, byte value)
1419void IntrinsicLocationsBuilderMIPS::VisitMemoryPokeByte(HInvoke* invoke) {
1420 CreateIntIntToVoidLocations(arena_, invoke);
1421}
1422
1423void IntrinsicCodeGeneratorMIPS::VisitMemoryPokeByte(HInvoke* invoke) {
1424 MipsAssembler* assembler = GetAssembler();
1425 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1426 Register val = invoke->GetLocations()->InAt(1).AsRegister<Register>();
1427
1428 __ Sb(val, adr, 0);
1429}
1430
1431// void libcore.io.Memory.pokeShort(long address, short value)
1432void IntrinsicLocationsBuilderMIPS::VisitMemoryPokeShortNative(HInvoke* invoke) {
1433 CreateIntIntToVoidLocations(arena_, invoke);
1434}
1435
1436void IntrinsicCodeGeneratorMIPS::VisitMemoryPokeShortNative(HInvoke* invoke) {
1437 MipsAssembler* assembler = GetAssembler();
1438 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1439 Register val = invoke->GetLocations()->InAt(1).AsRegister<Register>();
1440
1441 if (IsR6()) {
1442 __ Sh(val, adr, 0);
1443 } else {
1444 // Unlike for words, there are no shl/shr instructions to store
1445 // unaligned halfwords so the code stores individual bytes, in case
1446 // the address isn't halfword-aligned.
1447 __ Sb(val, adr, 0);
1448 __ Srl(AT, val, 8);
1449 __ Sb(AT, adr, 1);
1450 }
1451}
1452
1453// void libcore.io.Memory.pokeInt(long address, int value)
1454void IntrinsicLocationsBuilderMIPS::VisitMemoryPokeIntNative(HInvoke* invoke) {
1455 CreateIntIntToVoidLocations(arena_, invoke);
1456}
1457
1458void IntrinsicCodeGeneratorMIPS::VisitMemoryPokeIntNative(HInvoke* invoke) {
1459 MipsAssembler* assembler = GetAssembler();
1460 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1461 Register val = invoke->GetLocations()->InAt(1).AsRegister<Register>();
1462
1463 if (IsR6()) {
1464 __ Sw(val, adr, 0);
1465 } else {
1466 __ Swr(val, adr, 0);
1467 __ Swl(val, adr, 3);
1468 }
1469}
1470
1471// void libcore.io.Memory.pokeLong(long address, long value)
1472void IntrinsicLocationsBuilderMIPS::VisitMemoryPokeLongNative(HInvoke* invoke) {
1473 CreateIntIntToVoidLocations(arena_, invoke);
1474}
1475
1476void IntrinsicCodeGeneratorMIPS::VisitMemoryPokeLongNative(HInvoke* invoke) {
1477 MipsAssembler* assembler = GetAssembler();
1478 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>();
1479 Register val_lo = invoke->GetLocations()->InAt(1).AsRegisterPairLow<Register>();
1480 Register val_hi = invoke->GetLocations()->InAt(1).AsRegisterPairHigh<Register>();
1481
1482 if (IsR6()) {
1483 __ Sw(val_lo, adr, 0);
1484 __ Sw(val_hi, adr, 4);
1485 } else {
1486 __ Swr(val_lo, adr, 0);
1487 __ Swl(val_lo, adr, 3);
1488 __ Swr(val_hi, adr, 4);
1489 __ Swl(val_hi, adr, 7);
1490 }
1491}
1492
1493// char java.lang.String.charAt(int index)
1494void IntrinsicLocationsBuilderMIPS::VisitStringCharAt(HInvoke* invoke) {
1495 LocationSummary* locations = new (arena_) LocationSummary(invoke,
1496 LocationSummary::kCallOnSlowPath,
1497 kIntrinsified);
1498 locations->SetInAt(0, Location::RequiresRegister());
1499 locations->SetInAt(1, Location::RequiresRegister());
1500 locations->SetOut(Location::SameAsFirstInput());
1501}
1502
1503void IntrinsicCodeGeneratorMIPS::VisitStringCharAt(HInvoke* invoke) {
1504 LocationSummary* locations = invoke->GetLocations();
1505 MipsAssembler* assembler = GetAssembler();
1506
1507 // Location of reference to data array
1508 const int32_t value_offset = mirror::String::ValueOffset().Int32Value();
1509 // Location of count
1510 const int32_t count_offset = mirror::String::CountOffset().Int32Value();
1511
1512 Register obj = locations->InAt(0).AsRegister<Register>();
1513 Register idx = locations->InAt(1).AsRegister<Register>();
1514 Register out = locations->Out().AsRegister<Register>();
1515
1516 // TODO: Maybe we can support range check elimination. Overall,
1517 // though, I think it's not worth the cost.
1518 // TODO: For simplicity, the index parameter is requested in a
1519 // register, so different from Quick we will not optimize the
1520 // code for constants (which would save a register).
1521
1522 SlowPathCodeMIPS* slow_path = new (GetAllocator()) IntrinsicSlowPathMIPS(invoke);
1523 codegen_->AddSlowPath(slow_path);
1524
1525 // Load the string size
1526 __ Lw(TMP, obj, count_offset);
1527 codegen_->MaybeRecordImplicitNullCheck(invoke);
1528 // Revert to slow path if idx is too large, or negative
1529 __ Bgeu(idx, TMP, slow_path->GetEntryLabel());
1530
1531 // out = obj[2*idx].
1532 __ Sll(TMP, idx, 1); // idx * 2
1533 __ Addu(TMP, TMP, obj); // Address of char at location idx
1534 __ Lhu(out, TMP, value_offset); // Load char at location idx
1535
1536 __ Bind(slow_path->GetExitLabel());
1537}
1538
Chris Larsen16ba2b42015-11-02 10:58:31 -08001539// boolean java.lang.String.equals(Object anObject)
1540void IntrinsicLocationsBuilderMIPS::VisitStringEquals(HInvoke* invoke) {
1541 LocationSummary* locations = new (arena_) LocationSummary(invoke,
1542 LocationSummary::kNoCall,
1543 kIntrinsified);
1544 locations->SetInAt(0, Location::RequiresRegister());
1545 locations->SetInAt(1, Location::RequiresRegister());
1546 locations->SetOut(Location::RequiresRegister());
1547
1548 // Temporary registers to store lengths of strings and for calculations.
1549 locations->AddTemp(Location::RequiresRegister());
1550 locations->AddTemp(Location::RequiresRegister());
1551 locations->AddTemp(Location::RequiresRegister());
1552}
1553
1554void IntrinsicCodeGeneratorMIPS::VisitStringEquals(HInvoke* invoke) {
1555 MipsAssembler* assembler = GetAssembler();
1556 LocationSummary* locations = invoke->GetLocations();
1557
1558 Register str = locations->InAt(0).AsRegister<Register>();
1559 Register arg = locations->InAt(1).AsRegister<Register>();
1560 Register out = locations->Out().AsRegister<Register>();
1561
1562 Register temp1 = locations->GetTemp(0).AsRegister<Register>();
1563 Register temp2 = locations->GetTemp(1).AsRegister<Register>();
1564 Register temp3 = locations->GetTemp(2).AsRegister<Register>();
1565
1566 MipsLabel loop;
1567 MipsLabel end;
1568 MipsLabel return_true;
1569 MipsLabel return_false;
1570
1571 // Get offsets of count, value, and class fields within a string object.
1572 const uint32_t count_offset = mirror::String::CountOffset().Uint32Value();
1573 const uint32_t value_offset = mirror::String::ValueOffset().Uint32Value();
1574 const uint32_t class_offset = mirror::Object::ClassOffset().Uint32Value();
1575
1576 // Note that the null check must have been done earlier.
1577 DCHECK(!invoke->CanDoImplicitNullCheckOn(invoke->InputAt(0)));
1578
1579 // If the register containing the pointer to "this", and the register
1580 // containing the pointer to "anObject" are the same register then
1581 // "this", and "anObject" are the same object and we can
1582 // short-circuit the logic to a true result.
1583 if (str == arg) {
1584 __ LoadConst32(out, 1);
1585 return;
1586 }
1587
1588 // Check if input is null, return false if it is.
1589 __ Beqz(arg, &return_false);
1590
1591 // Reference equality check, return true if same reference.
1592 __ Beq(str, arg, &return_true);
1593
1594 // Instanceof check for the argument by comparing class fields.
1595 // All string objects must have the same type since String cannot be subclassed.
1596 // Receiver must be a string object, so its class field is equal to all strings' class fields.
1597 // If the argument is a string object, its class field must be equal to receiver's class field.
1598 __ Lw(temp1, str, class_offset);
1599 __ Lw(temp2, arg, class_offset);
1600 __ Bne(temp1, temp2, &return_false);
1601
1602 // Load lengths of this and argument strings.
1603 __ Lw(temp1, str, count_offset);
1604 __ Lw(temp2, arg, count_offset);
1605 // Check if lengths are equal, return false if they're not.
1606 __ Bne(temp1, temp2, &return_false);
1607 // Return true if both strings are empty.
1608 __ Beqz(temp1, &return_true);
1609
1610 // Don't overwrite input registers
1611 __ Move(TMP, str);
1612 __ Move(temp3, arg);
1613
1614 // Assertions that must hold in order to compare strings 2 characters at a time.
1615 DCHECK_ALIGNED(value_offset, 4);
1616 static_assert(IsAligned<4>(kObjectAlignment), "String of odd length is not zero padded");
1617
1618 // Loop to compare strings 2 characters at a time starting at the beginning of the string.
1619 // Ok to do this because strings are zero-padded.
1620 __ Bind(&loop);
1621 __ Lw(out, TMP, value_offset);
1622 __ Lw(temp2, temp3, value_offset);
1623 __ Bne(out, temp2, &return_false);
1624 __ Addiu(TMP, TMP, 4);
1625 __ Addiu(temp3, temp3, 4);
1626 __ Addiu(temp1, temp1, -2);
1627 __ Bgtz(temp1, &loop);
1628
1629 // Return true and exit the function.
1630 // If loop does not result in returning false, we return true.
1631 __ Bind(&return_true);
1632 __ LoadConst32(out, 1);
1633 __ B(&end);
1634
1635 // Return false and exit the function.
1636 __ Bind(&return_false);
1637 __ LoadConst32(out, 0);
1638 __ Bind(&end);
1639}
1640
Chris Larsen2714fe62016-02-11 14:23:53 -08001641static void GenIsInfinite(LocationSummary* locations,
1642 const Primitive::Type type,
1643 const bool isR6,
1644 MipsAssembler* assembler) {
1645 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
1646 Register out = locations->Out().AsRegister<Register>();
1647
1648 DCHECK(type == Primitive::kPrimFloat || type == Primitive::kPrimDouble);
1649
1650 if (isR6) {
1651 if (type == Primitive::kPrimDouble) {
1652 __ ClassD(FTMP, in);
1653 } else {
1654 __ ClassS(FTMP, in);
1655 }
1656 __ Mfc1(out, FTMP);
1657 __ Andi(out, out, kPositiveInfinity | kNegativeInfinity);
1658 __ Sltu(out, ZERO, out);
1659 } else {
1660 // If one, or more, of the exponent bits is zero, then the number can't be infinite.
1661 if (type == Primitive::kPrimDouble) {
1662 __ MoveFromFpuHigh(TMP, in);
1663 __ LoadConst32(AT, 0x7FF00000);
1664 } else {
1665 __ Mfc1(TMP, in);
1666 __ LoadConst32(AT, 0x7F800000);
1667 }
1668 __ Xor(TMP, TMP, AT);
1669
1670 __ Sll(TMP, TMP, 1);
1671
1672 if (type == Primitive::kPrimDouble) {
1673 __ Mfc1(AT, in);
1674 __ Or(TMP, TMP, AT);
1675 }
1676 // If any of the significand bits are one, then the number is not infinite.
1677 __ Sltiu(out, TMP, 1);
1678 }
1679}
1680
1681// boolean java.lang.Float.isInfinite(float)
1682void IntrinsicLocationsBuilderMIPS::VisitFloatIsInfinite(HInvoke* invoke) {
1683 CreateFPToIntLocations(arena_, invoke);
1684}
1685
1686void IntrinsicCodeGeneratorMIPS::VisitFloatIsInfinite(HInvoke* invoke) {
1687 GenIsInfinite(invoke->GetLocations(), Primitive::kPrimFloat, IsR6(), GetAssembler());
1688}
1689
1690// boolean java.lang.Double.isInfinite(double)
1691void IntrinsicLocationsBuilderMIPS::VisitDoubleIsInfinite(HInvoke* invoke) {
1692 CreateFPToIntLocations(arena_, invoke);
1693}
1694
1695void IntrinsicCodeGeneratorMIPS::VisitDoubleIsInfinite(HInvoke* invoke) {
1696 GenIsInfinite(invoke->GetLocations(), Primitive::kPrimDouble, IsR6(), GetAssembler());
1697}
1698
1699// Unimplemented intrinsics.
1700
Aart Bik2f9fcc92016-03-01 15:16:54 -08001701UNIMPLEMENTED_INTRINSIC(MIPS, MathCeil)
1702UNIMPLEMENTED_INTRINSIC(MIPS, MathFloor)
1703UNIMPLEMENTED_INTRINSIC(MIPS, MathRint)
1704UNIMPLEMENTED_INTRINSIC(MIPS, MathRoundDouble)
1705UNIMPLEMENTED_INTRINSIC(MIPS, MathRoundFloat)
1706UNIMPLEMENTED_INTRINSIC(MIPS, ThreadCurrentThread)
1707UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGet)
1708UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGetVolatile)
1709UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGetLong)
1710UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGetLongVolatile)
1711UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGetObject)
1712UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeGetObjectVolatile)
1713UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePut)
1714UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutOrdered)
1715UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutVolatile)
1716UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutObject)
1717UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutObjectOrdered)
1718UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutObjectVolatile)
1719UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutLong)
1720UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutLongOrdered)
1721UNIMPLEMENTED_INTRINSIC(MIPS, UnsafePutLongVolatile)
1722UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeCASInt)
1723UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeCASLong)
1724UNIMPLEMENTED_INTRINSIC(MIPS, UnsafeCASObject)
1725UNIMPLEMENTED_INTRINSIC(MIPS, StringCompareTo)
1726UNIMPLEMENTED_INTRINSIC(MIPS, StringIndexOf)
1727UNIMPLEMENTED_INTRINSIC(MIPS, StringIndexOfAfter)
1728UNIMPLEMENTED_INTRINSIC(MIPS, StringNewStringFromBytes)
1729UNIMPLEMENTED_INTRINSIC(MIPS, StringNewStringFromChars)
1730UNIMPLEMENTED_INTRINSIC(MIPS, StringNewStringFromString)
Chris Larsen701566a2015-10-27 15:29:13 -07001731
Aart Bik2f9fcc92016-03-01 15:16:54 -08001732UNIMPLEMENTED_INTRINSIC(MIPS, ReferenceGetReferent)
1733UNIMPLEMENTED_INTRINSIC(MIPS, StringGetCharsNoCheck)
1734UNIMPLEMENTED_INTRINSIC(MIPS, SystemArrayCopyChar)
1735UNIMPLEMENTED_INTRINSIC(MIPS, SystemArrayCopy)
Aart Bik3f67e692016-01-15 14:35:12 -08001736
Aart Bik2f9fcc92016-03-01 15:16:54 -08001737UNIMPLEMENTED_INTRINSIC(MIPS, MathCos)
1738UNIMPLEMENTED_INTRINSIC(MIPS, MathSin)
1739UNIMPLEMENTED_INTRINSIC(MIPS, MathAcos)
1740UNIMPLEMENTED_INTRINSIC(MIPS, MathAsin)
1741UNIMPLEMENTED_INTRINSIC(MIPS, MathAtan)
1742UNIMPLEMENTED_INTRINSIC(MIPS, MathAtan2)
1743UNIMPLEMENTED_INTRINSIC(MIPS, MathCbrt)
1744UNIMPLEMENTED_INTRINSIC(MIPS, MathCosh)
1745UNIMPLEMENTED_INTRINSIC(MIPS, MathExp)
1746UNIMPLEMENTED_INTRINSIC(MIPS, MathExpm1)
1747UNIMPLEMENTED_INTRINSIC(MIPS, MathHypot)
1748UNIMPLEMENTED_INTRINSIC(MIPS, MathLog)
1749UNIMPLEMENTED_INTRINSIC(MIPS, MathLog10)
1750UNIMPLEMENTED_INTRINSIC(MIPS, MathNextAfter)
1751UNIMPLEMENTED_INTRINSIC(MIPS, MathSinh)
1752UNIMPLEMENTED_INTRINSIC(MIPS, MathTan)
1753UNIMPLEMENTED_INTRINSIC(MIPS, MathTanh)
Chris Larsen701566a2015-10-27 15:29:13 -07001754
Aart Bik2f9fcc92016-03-01 15:16:54 -08001755UNIMPLEMENTED_INTRINSIC(MIPS, IntegerHighestOneBit)
1756UNIMPLEMENTED_INTRINSIC(MIPS, LongHighestOneBit)
1757UNIMPLEMENTED_INTRINSIC(MIPS, IntegerLowestOneBit)
1758UNIMPLEMENTED_INTRINSIC(MIPS, LongLowestOneBit)
Aart Bik59c94542016-01-25 14:20:58 -08001759
Aart Bik2f9fcc92016-03-01 15:16:54 -08001760UNREACHABLE_INTRINSICS(MIPS)
Chris Larsen701566a2015-10-27 15:29:13 -07001761
Chris Larsen2714fe62016-02-11 14:23:53 -08001762#undef UNIMPLEMENTED_INTRINSIC
1763
Chris Larsen701566a2015-10-27 15:29:13 -07001764#undef __
1765
1766} // namespace mips
1767} // namespace art