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Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001// Copyright 2011 Google Inc. All Rights Reserved.
2
Ian Rogers2c8f6532011-09-02 17:16:34 -07003#include "assembler_arm.h"
4
Brian Carlstrom578bbdc2011-07-21 14:07:47 -07005#include "logging.h"
6#include "offsets.h"
Carl Shapiroe2d373e2011-07-25 15:20:06 -07007#include "thread.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -07008#include "utils.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07009
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070010namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070011namespace arm {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070012
Carl Shapiroa2e18e12011-06-21 18:57:55 -070013// Instruction encoding bits.
14enum {
15 H = 1 << 5, // halfword (or byte)
16 L = 1 << 20, // load (or store)
17 S = 1 << 20, // set condition code (or leave unchanged)
18 W = 1 << 21, // writeback base register (or leave unchanged)
19 A = 1 << 21, // accumulate in multiply instruction (or not)
20 B = 1 << 22, // unsigned byte (or word)
21 N = 1 << 22, // long (or short)
22 U = 1 << 23, // positive (or negative) offset/index
23 P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing)
24 I = 1 << 25, // immediate shifter operand (or not)
25
26 B0 = 1,
27 B1 = 1 << 1,
28 B2 = 1 << 2,
29 B3 = 1 << 3,
30 B4 = 1 << 4,
31 B5 = 1 << 5,
32 B6 = 1 << 6,
33 B7 = 1 << 7,
34 B8 = 1 << 8,
35 B9 = 1 << 9,
36 B10 = 1 << 10,
37 B11 = 1 << 11,
38 B12 = 1 << 12,
39 B16 = 1 << 16,
40 B17 = 1 << 17,
41 B18 = 1 << 18,
42 B19 = 1 << 19,
43 B20 = 1 << 20,
44 B21 = 1 << 21,
45 B22 = 1 << 22,
46 B23 = 1 << 23,
47 B24 = 1 << 24,
48 B25 = 1 << 25,
49 B26 = 1 << 26,
50 B27 = 1 << 27,
51
52 // Instruction bit masks.
53 RdMask = 15 << 12, // in str instruction
54 CondMask = 15 << 28,
55 CoprocessorMask = 15 << 8,
56 OpCodeMask = 15 << 21, // in data-processing instructions
57 Imm24Mask = (1 << 24) - 1,
58 Off12Mask = (1 << 12) - 1,
59
60 // ldrex/strex register field encodings.
61 kLdExRnShift = 16,
62 kLdExRtShift = 12,
63 kStrExRnShift = 16,
64 kStrExRdShift = 12,
65 kStrExRtShift = 0,
66};
67
68
Elliott Hughes1f359b02011-07-17 14:27:17 -070069static const char* kRegisterNames[] = {
70 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
71 "fp", "ip", "sp", "lr", "pc"
72};
73std::ostream& operator<<(std::ostream& os, const Register& rhs) {
74 if (rhs >= R0 && rhs <= PC) {
75 os << kRegisterNames[rhs];
76 } else {
Ian Rogersb033c752011-07-20 12:22:35 -070077 os << "Register[" << static_cast<int>(rhs) << "]";
Elliott Hughes1f359b02011-07-17 14:27:17 -070078 }
79 return os;
80}
81
82
83std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
84 if (rhs >= S0 && rhs < kNumberOfSRegisters) {
Ian Rogersb033c752011-07-20 12:22:35 -070085 os << "s" << static_cast<int>(rhs);
Elliott Hughes1f359b02011-07-17 14:27:17 -070086 } else {
Ian Rogersb033c752011-07-20 12:22:35 -070087 os << "SRegister[" << static_cast<int>(rhs) << "]";
Elliott Hughes1f359b02011-07-17 14:27:17 -070088 }
89 return os;
90}
91
92
93std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
94 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
Ian Rogersb033c752011-07-20 12:22:35 -070095 os << "d" << static_cast<int>(rhs);
Elliott Hughes1f359b02011-07-17 14:27:17 -070096 } else {
Ian Rogersb033c752011-07-20 12:22:35 -070097 os << "DRegister[" << static_cast<int>(rhs) << "]";
Elliott Hughes1f359b02011-07-17 14:27:17 -070098 }
99 return os;
100}
101
102
103static const char* kConditionNames[] = {
Ian Rogersb033c752011-07-20 12:22:35 -0700104 "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT",
105 "LE", "AL",
Elliott Hughes1f359b02011-07-17 14:27:17 -0700106};
107std::ostream& operator<<(std::ostream& os, const Condition& rhs) {
108 if (rhs >= EQ && rhs <= AL) {
109 os << kConditionNames[rhs];
110 } else {
Ian Rogersb033c752011-07-20 12:22:35 -0700111 os << "Condition[" << static_cast<int>(rhs) << "]";
Elliott Hughes1f359b02011-07-17 14:27:17 -0700112 }
113 return os;
114}
115
Ian Rogers2c8f6532011-09-02 17:16:34 -0700116void ArmAssembler::Emit(int32_t value) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700117 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
118 buffer_.Emit<int32_t>(value);
119}
120
121
Ian Rogers2c8f6532011-09-02 17:16:34 -0700122void ArmAssembler::EmitType01(Condition cond,
123 int type,
124 Opcode opcode,
125 int set_cc,
126 Register rn,
127 Register rd,
128 ShifterOperand so) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700129 CHECK_NE(rd, kNoRegister);
130 CHECK_NE(cond, kNoCondition);
131 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
132 type << kTypeShift |
133 static_cast<int32_t>(opcode) << kOpcodeShift |
134 set_cc << kSShift |
135 static_cast<int32_t>(rn) << kRnShift |
136 static_cast<int32_t>(rd) << kRdShift |
137 so.encoding();
138 Emit(encoding);
139}
140
141
Ian Rogers2c8f6532011-09-02 17:16:34 -0700142void ArmAssembler::EmitType5(Condition cond, int offset, bool link) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700143 CHECK_NE(cond, kNoCondition);
144 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
145 5 << kTypeShift |
146 (link ? 1 : 0) << kLinkShift;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700147 Emit(ArmAssembler::EncodeBranchOffset(offset, encoding));
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700148}
149
150
Ian Rogers2c8f6532011-09-02 17:16:34 -0700151void ArmAssembler::EmitMemOp(Condition cond,
152 bool load,
153 bool byte,
154 Register rd,
155 Address ad) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700156 CHECK_NE(rd, kNoRegister);
157 CHECK_NE(cond, kNoCondition);
158 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
159 B26 |
160 (load ? L : 0) |
161 (byte ? B : 0) |
162 (static_cast<int32_t>(rd) << kRdShift) |
163 ad.encoding();
164 Emit(encoding);
165}
166
167
Ian Rogers2c8f6532011-09-02 17:16:34 -0700168void ArmAssembler::EmitMemOpAddressMode3(Condition cond,
169 int32_t mode,
170 Register rd,
171 Address ad) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700172 CHECK_NE(rd, kNoRegister);
173 CHECK_NE(cond, kNoCondition);
174 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
175 B22 |
176 mode |
177 (static_cast<int32_t>(rd) << kRdShift) |
178 ad.encoding3();
179 Emit(encoding);
180}
181
182
Ian Rogers2c8f6532011-09-02 17:16:34 -0700183void ArmAssembler::EmitMultiMemOp(Condition cond,
184 BlockAddressMode am,
185 bool load,
186 Register base,
187 RegList regs) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700188 CHECK_NE(base, kNoRegister);
189 CHECK_NE(cond, kNoCondition);
190 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
191 B27 |
192 am |
193 (load ? L : 0) |
194 (static_cast<int32_t>(base) << kRnShift) |
195 regs;
196 Emit(encoding);
197}
198
199
Ian Rogers2c8f6532011-09-02 17:16:34 -0700200void ArmAssembler::EmitShiftImmediate(Condition cond,
201 Shift opcode,
202 Register rd,
203 Register rm,
204 ShifterOperand so) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700205 CHECK_NE(cond, kNoCondition);
Elliott Hughes1f359b02011-07-17 14:27:17 -0700206 CHECK_EQ(so.type(), 1U);
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700207 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
208 static_cast<int32_t>(MOV) << kOpcodeShift |
209 static_cast<int32_t>(rd) << kRdShift |
210 so.encoding() << kShiftImmShift |
211 static_cast<int32_t>(opcode) << kShiftShift |
212 static_cast<int32_t>(rm);
213 Emit(encoding);
214}
215
216
Ian Rogers2c8f6532011-09-02 17:16:34 -0700217void ArmAssembler::EmitShiftRegister(Condition cond,
218 Shift opcode,
219 Register rd,
220 Register rm,
221 ShifterOperand so) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700222 CHECK_NE(cond, kNoCondition);
Elliott Hughes1f359b02011-07-17 14:27:17 -0700223 CHECK_EQ(so.type(), 0U);
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700224 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
225 static_cast<int32_t>(MOV) << kOpcodeShift |
226 static_cast<int32_t>(rd) << kRdShift |
227 so.encoding() << kShiftRegisterShift |
228 static_cast<int32_t>(opcode) << kShiftShift |
229 B4 |
230 static_cast<int32_t>(rm);
231 Emit(encoding);
232}
233
234
Ian Rogers2c8f6532011-09-02 17:16:34 -0700235void ArmAssembler::EmitBranch(Condition cond, Label* label, bool link) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700236 if (label->IsBound()) {
237 EmitType5(cond, label->Position() - buffer_.Size(), link);
238 } else {
239 int position = buffer_.Size();
240 // Use the offset field of the branch instruction for linking the sites.
241 EmitType5(cond, label->position_, link);
242 label->LinkTo(position);
243 }
244}
245
Ian Rogers2c8f6532011-09-02 17:16:34 -0700246void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so,
247 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700248 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
249}
250
251
Ian Rogers2c8f6532011-09-02 17:16:34 -0700252void ArmAssembler::eor(Register rd, Register rn, ShifterOperand so,
253 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700254 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void ArmAssembler::sub(Register rd, Register rn, ShifterOperand so,
259 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700260 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
261}
262
Ian Rogers2c8f6532011-09-02 17:16:34 -0700263void ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so,
264 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700265 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
266}
267
Ian Rogers2c8f6532011-09-02 17:16:34 -0700268void ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so,
269 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700270 EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void ArmAssembler::add(Register rd, Register rn, ShifterOperand so,
275 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700276 EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
277}
278
279
Ian Rogers2c8f6532011-09-02 17:16:34 -0700280void ArmAssembler::adds(Register rd, Register rn, ShifterOperand so,
281 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700282 EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
283}
284
285
Ian Rogers2c8f6532011-09-02 17:16:34 -0700286void ArmAssembler::subs(Register rd, Register rn, ShifterOperand so,
287 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700288 EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
289}
290
291
Ian Rogers2c8f6532011-09-02 17:16:34 -0700292void ArmAssembler::adc(Register rd, Register rn, ShifterOperand so,
293 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700294 EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
295}
296
297
Ian Rogers2c8f6532011-09-02 17:16:34 -0700298void ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so,
299 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700300 EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
301}
302
303
Ian Rogers2c8f6532011-09-02 17:16:34 -0700304void ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so,
305 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700306 EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
307}
308
309
Ian Rogers2c8f6532011-09-02 17:16:34 -0700310void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700311 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
312 EmitType01(cond, so.type(), TST, 1, rn, R0, so);
313}
314
315
Ian Rogers2c8f6532011-09-02 17:16:34 -0700316void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700317 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
318 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
319}
320
321
Ian Rogers2c8f6532011-09-02 17:16:34 -0700322void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700323 EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
324}
325
326
Ian Rogers2c8f6532011-09-02 17:16:34 -0700327void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700328 EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
329}
330
331
Ian Rogers2c8f6532011-09-02 17:16:34 -0700332void ArmAssembler::orr(Register rd, Register rn,
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700333 ShifterOperand so, Condition cond) {
334 EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
335}
336
337
Ian Rogers2c8f6532011-09-02 17:16:34 -0700338void ArmAssembler::orrs(Register rd, Register rn,
339 ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700340 EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
341}
342
343
Ian Rogers2c8f6532011-09-02 17:16:34 -0700344void ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700345 EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
346}
347
348
Ian Rogers2c8f6532011-09-02 17:16:34 -0700349void ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700350 EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
351}
352
353
Ian Rogers2c8f6532011-09-02 17:16:34 -0700354void ArmAssembler::bic(Register rd, Register rn, ShifterOperand so,
355 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700356 EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
357}
358
359
Ian Rogers2c8f6532011-09-02 17:16:34 -0700360void ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700361 EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
362}
363
364
Ian Rogers2c8f6532011-09-02 17:16:34 -0700365void ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700366 EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
367}
368
369
Ian Rogers2c8f6532011-09-02 17:16:34 -0700370void ArmAssembler::clz(Register rd, Register rm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700371 CHECK_NE(rd, kNoRegister);
372 CHECK_NE(rm, kNoRegister);
373 CHECK_NE(cond, kNoCondition);
374 CHECK_NE(rd, PC);
375 CHECK_NE(rm, PC);
376 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
377 B24 | B22 | B21 | (0xf << 16) |
378 (static_cast<int32_t>(rd) << kRdShift) |
379 (0xf << 8) | B4 | static_cast<int32_t>(rm);
380 Emit(encoding);
381}
382
383
Ian Rogers2c8f6532011-09-02 17:16:34 -0700384void ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700385 CHECK_NE(cond, kNoCondition);
386 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
387 B25 | B24 | ((imm16 >> 12) << 16) |
388 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
389 Emit(encoding);
390}
391
392
Ian Rogers2c8f6532011-09-02 17:16:34 -0700393void ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700394 CHECK_NE(cond, kNoCondition);
395 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
396 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
397 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
398 Emit(encoding);
399}
400
401
Ian Rogers2c8f6532011-09-02 17:16:34 -0700402void ArmAssembler::EmitMulOp(Condition cond, int32_t opcode,
403 Register rd, Register rn,
404 Register rm, Register rs) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700405 CHECK_NE(rd, kNoRegister);
406 CHECK_NE(rn, kNoRegister);
407 CHECK_NE(rm, kNoRegister);
408 CHECK_NE(rs, kNoRegister);
409 CHECK_NE(cond, kNoCondition);
410 int32_t encoding = opcode |
411 (static_cast<int32_t>(cond) << kConditionShift) |
412 (static_cast<int32_t>(rn) << kRnShift) |
413 (static_cast<int32_t>(rd) << kRdShift) |
414 (static_cast<int32_t>(rs) << kRsShift) |
415 B7 | B4 |
416 (static_cast<int32_t>(rm) << kRmShift);
417 Emit(encoding);
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700422 // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
423 EmitMulOp(cond, 0, R0, rd, rn, rm);
424}
425
426
Ian Rogers2c8f6532011-09-02 17:16:34 -0700427void ArmAssembler::mla(Register rd, Register rn, Register rm, Register ra,
428 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700429 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
430 EmitMulOp(cond, B21, ra, rd, rn, rm);
431}
432
433
Ian Rogers2c8f6532011-09-02 17:16:34 -0700434void ArmAssembler::mls(Register rd, Register rn, Register rm, Register ra,
435 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700436 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
437 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
438}
439
440
Ian Rogers2c8f6532011-09-02 17:16:34 -0700441void ArmAssembler::umull(Register rd_lo, Register rd_hi, Register rn,
442 Register rm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700443 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
444 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void ArmAssembler::ldr(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700449 EmitMemOp(cond, true, false, rd, ad);
450}
451
452
Ian Rogers2c8f6532011-09-02 17:16:34 -0700453void ArmAssembler::str(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700454 EmitMemOp(cond, false, false, rd, ad);
455}
456
457
Ian Rogers2c8f6532011-09-02 17:16:34 -0700458void ArmAssembler::ldrb(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700459 EmitMemOp(cond, true, true, rd, ad);
460}
461
462
Ian Rogers2c8f6532011-09-02 17:16:34 -0700463void ArmAssembler::strb(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700464 EmitMemOp(cond, false, true, rd, ad);
465}
466
467
Ian Rogers2c8f6532011-09-02 17:16:34 -0700468void ArmAssembler::ldrh(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700469 EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
470}
471
472
Ian Rogers2c8f6532011-09-02 17:16:34 -0700473void ArmAssembler::strh(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700474 EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
475}
476
477
Ian Rogers2c8f6532011-09-02 17:16:34 -0700478void ArmAssembler::ldrsb(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700479 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
480}
481
482
Ian Rogers2c8f6532011-09-02 17:16:34 -0700483void ArmAssembler::ldrsh(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700484 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
485}
486
487
Ian Rogers2c8f6532011-09-02 17:16:34 -0700488void ArmAssembler::ldrd(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700489 CHECK_EQ(rd % 2, 0);
490 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
491}
492
493
Ian Rogers2c8f6532011-09-02 17:16:34 -0700494void ArmAssembler::strd(Register rd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700495 CHECK_EQ(rd % 2, 0);
496 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
497}
498
499
Ian Rogers2c8f6532011-09-02 17:16:34 -0700500void ArmAssembler::ldm(BlockAddressMode am,
501 Register base,
502 RegList regs,
503 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700504 EmitMultiMemOp(cond, am, true, base, regs);
505}
506
507
Ian Rogers2c8f6532011-09-02 17:16:34 -0700508void ArmAssembler::stm(BlockAddressMode am,
509 Register base,
510 RegList regs,
511 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700512 EmitMultiMemOp(cond, am, false, base, regs);
513}
514
515
Ian Rogers2c8f6532011-09-02 17:16:34 -0700516void ArmAssembler::ldrex(Register rt, Register rn, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700517 CHECK_NE(rn, kNoRegister);
518 CHECK_NE(rt, kNoRegister);
519 CHECK_NE(cond, kNoCondition);
520 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
521 B24 |
522 B23 |
523 L |
524 (static_cast<int32_t>(rn) << kLdExRnShift) |
525 (static_cast<int32_t>(rt) << kLdExRtShift) |
526 B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
527 Emit(encoding);
528}
529
530
Ian Rogers2c8f6532011-09-02 17:16:34 -0700531void ArmAssembler::strex(Register rd,
532 Register rt,
533 Register rn,
534 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700535 CHECK_NE(rn, kNoRegister);
536 CHECK_NE(rd, kNoRegister);
537 CHECK_NE(rt, kNoRegister);
538 CHECK_NE(cond, kNoCondition);
539 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
540 B24 |
541 B23 |
542 (static_cast<int32_t>(rn) << kStrExRnShift) |
543 (static_cast<int32_t>(rd) << kStrExRdShift) |
544 B11 | B10 | B9 | B8 | B7 | B4 |
545 (static_cast<int32_t>(rt) << kStrExRtShift);
546 Emit(encoding);
547}
548
549
Ian Rogers2c8f6532011-09-02 17:16:34 -0700550void ArmAssembler::clrex() {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700551 int32_t encoding = (kSpecialCondition << kConditionShift) |
552 B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
553 Emit(encoding);
554}
555
556
Ian Rogers2c8f6532011-09-02 17:16:34 -0700557void ArmAssembler::nop(Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700558 CHECK_NE(cond, kNoCondition);
559 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
560 B25 | B24 | B21 | (0xf << 12);
561 Emit(encoding);
562}
563
564
Ian Rogers2c8f6532011-09-02 17:16:34 -0700565void ArmAssembler::vmovsr(SRegister sn, Register rt, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700566 CHECK_NE(sn, kNoSRegister);
567 CHECK_NE(rt, kNoRegister);
568 CHECK_NE(rt, SP);
569 CHECK_NE(rt, PC);
570 CHECK_NE(cond, kNoCondition);
571 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
572 B27 | B26 | B25 |
573 ((static_cast<int32_t>(sn) >> 1)*B16) |
574 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
575 ((static_cast<int32_t>(sn) & 1)*B7) | B4;
576 Emit(encoding);
577}
578
579
Ian Rogers2c8f6532011-09-02 17:16:34 -0700580void ArmAssembler::vmovrs(Register rt, SRegister sn, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700581 CHECK_NE(sn, kNoSRegister);
582 CHECK_NE(rt, kNoRegister);
583 CHECK_NE(rt, SP);
584 CHECK_NE(rt, PC);
585 CHECK_NE(cond, kNoCondition);
586 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
587 B27 | B26 | B25 | B20 |
588 ((static_cast<int32_t>(sn) >> 1)*B16) |
589 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
590 ((static_cast<int32_t>(sn) & 1)*B7) | B4;
591 Emit(encoding);
592}
593
594
Ian Rogers2c8f6532011-09-02 17:16:34 -0700595void ArmAssembler::vmovsrr(SRegister sm, Register rt, Register rt2,
596 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700597 CHECK_NE(sm, kNoSRegister);
598 CHECK_NE(sm, S31);
599 CHECK_NE(rt, kNoRegister);
600 CHECK_NE(rt, SP);
601 CHECK_NE(rt, PC);
602 CHECK_NE(rt2, kNoRegister);
603 CHECK_NE(rt2, SP);
604 CHECK_NE(rt2, PC);
605 CHECK_NE(cond, kNoCondition);
606 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
607 B27 | B26 | B22 |
608 (static_cast<int32_t>(rt2)*B16) |
609 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
610 ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
611 (static_cast<int32_t>(sm) >> 1);
612 Emit(encoding);
613}
614
615
Ian Rogers2c8f6532011-09-02 17:16:34 -0700616void ArmAssembler::vmovrrs(Register rt, Register rt2, SRegister sm,
617 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700618 CHECK_NE(sm, kNoSRegister);
619 CHECK_NE(sm, S31);
620 CHECK_NE(rt, kNoRegister);
621 CHECK_NE(rt, SP);
622 CHECK_NE(rt, PC);
623 CHECK_NE(rt2, kNoRegister);
624 CHECK_NE(rt2, SP);
625 CHECK_NE(rt2, PC);
626 CHECK_NE(rt, rt2);
627 CHECK_NE(cond, kNoCondition);
628 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
629 B27 | B26 | B22 | B20 |
630 (static_cast<int32_t>(rt2)*B16) |
631 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
632 ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
633 (static_cast<int32_t>(sm) >> 1);
634 Emit(encoding);
635}
636
637
Ian Rogers2c8f6532011-09-02 17:16:34 -0700638void ArmAssembler::vmovdrr(DRegister dm, Register rt, Register rt2,
639 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700640 CHECK_NE(dm, kNoDRegister);
641 CHECK_NE(rt, kNoRegister);
642 CHECK_NE(rt, SP);
643 CHECK_NE(rt, PC);
644 CHECK_NE(rt2, kNoRegister);
645 CHECK_NE(rt2, SP);
646 CHECK_NE(rt2, PC);
647 CHECK_NE(cond, kNoCondition);
648 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
649 B27 | B26 | B22 |
650 (static_cast<int32_t>(rt2)*B16) |
651 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
652 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
653 (static_cast<int32_t>(dm) & 0xf);
654 Emit(encoding);
655}
656
657
Ian Rogers2c8f6532011-09-02 17:16:34 -0700658void ArmAssembler::vmovrrd(Register rt, Register rt2, DRegister dm,
659 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700660 CHECK_NE(dm, kNoDRegister);
661 CHECK_NE(rt, kNoRegister);
662 CHECK_NE(rt, SP);
663 CHECK_NE(rt, PC);
664 CHECK_NE(rt2, kNoRegister);
665 CHECK_NE(rt2, SP);
666 CHECK_NE(rt2, PC);
667 CHECK_NE(rt, rt2);
668 CHECK_NE(cond, kNoCondition);
669 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
670 B27 | B26 | B22 | B20 |
671 (static_cast<int32_t>(rt2)*B16) |
672 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
673 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
674 (static_cast<int32_t>(dm) & 0xf);
675 Emit(encoding);
676}
677
678
Ian Rogers2c8f6532011-09-02 17:16:34 -0700679void ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700680 CHECK_NE(sd, kNoSRegister);
681 CHECK_NE(cond, kNoCondition);
682 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
683 B27 | B26 | B24 | B20 |
684 ((static_cast<int32_t>(sd) & 1)*B22) |
685 ((static_cast<int32_t>(sd) >> 1)*B12) |
686 B11 | B9 | ad.vencoding();
687 Emit(encoding);
688}
689
690
Ian Rogers2c8f6532011-09-02 17:16:34 -0700691void ArmAssembler::vstrs(SRegister sd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700692 CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC);
693 CHECK_NE(sd, kNoSRegister);
694 CHECK_NE(cond, kNoCondition);
695 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
696 B27 | B26 | B24 |
697 ((static_cast<int32_t>(sd) & 1)*B22) |
698 ((static_cast<int32_t>(sd) >> 1)*B12) |
699 B11 | B9 | ad.vencoding();
700 Emit(encoding);
701}
702
703
Ian Rogers2c8f6532011-09-02 17:16:34 -0700704void ArmAssembler::vldrd(DRegister dd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700705 CHECK_NE(dd, kNoDRegister);
706 CHECK_NE(cond, kNoCondition);
707 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
708 B27 | B26 | B24 | B20 |
709 ((static_cast<int32_t>(dd) >> 4)*B22) |
710 ((static_cast<int32_t>(dd) & 0xf)*B12) |
711 B11 | B9 | B8 | ad.vencoding();
712 Emit(encoding);
713}
714
715
Ian Rogers2c8f6532011-09-02 17:16:34 -0700716void ArmAssembler::vstrd(DRegister dd, Address ad, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700717 CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC);
718 CHECK_NE(dd, kNoDRegister);
719 CHECK_NE(cond, kNoCondition);
720 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
721 B27 | B26 | B24 |
722 ((static_cast<int32_t>(dd) >> 4)*B22) |
723 ((static_cast<int32_t>(dd) & 0xf)*B12) |
724 B11 | B9 | B8 | ad.vencoding();
725 Emit(encoding);
726}
727
728
Ian Rogers2c8f6532011-09-02 17:16:34 -0700729void ArmAssembler::EmitVFPsss(Condition cond, int32_t opcode,
730 SRegister sd, SRegister sn, SRegister sm) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700731 CHECK_NE(sd, kNoSRegister);
732 CHECK_NE(sn, kNoSRegister);
733 CHECK_NE(sm, kNoSRegister);
734 CHECK_NE(cond, kNoCondition);
735 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
736 B27 | B26 | B25 | B11 | B9 | opcode |
737 ((static_cast<int32_t>(sd) & 1)*B22) |
738 ((static_cast<int32_t>(sn) >> 1)*B16) |
739 ((static_cast<int32_t>(sd) >> 1)*B12) |
740 ((static_cast<int32_t>(sn) & 1)*B7) |
741 ((static_cast<int32_t>(sm) & 1)*B5) |
742 (static_cast<int32_t>(sm) >> 1);
743 Emit(encoding);
744}
745
746
Ian Rogers2c8f6532011-09-02 17:16:34 -0700747void ArmAssembler::EmitVFPddd(Condition cond, int32_t opcode,
748 DRegister dd, DRegister dn, DRegister dm) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700749 CHECK_NE(dd, kNoDRegister);
750 CHECK_NE(dn, kNoDRegister);
751 CHECK_NE(dm, kNoDRegister);
752 CHECK_NE(cond, kNoCondition);
753 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
754 B27 | B26 | B25 | B11 | B9 | B8 | opcode |
755 ((static_cast<int32_t>(dd) >> 4)*B22) |
756 ((static_cast<int32_t>(dn) & 0xf)*B16) |
757 ((static_cast<int32_t>(dd) & 0xf)*B12) |
758 ((static_cast<int32_t>(dn) >> 4)*B7) |
759 ((static_cast<int32_t>(dm) >> 4)*B5) |
760 (static_cast<int32_t>(dm) & 0xf);
761 Emit(encoding);
762}
763
764
Ian Rogers2c8f6532011-09-02 17:16:34 -0700765void ArmAssembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700766 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
767}
768
769
Ian Rogers2c8f6532011-09-02 17:16:34 -0700770void ArmAssembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700771 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
772}
773
774
Ian Rogers2c8f6532011-09-02 17:16:34 -0700775bool ArmAssembler::vmovs(SRegister sd, float s_imm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700776 uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
777 if (((imm32 & ((1 << 19) - 1)) == 0) &&
778 ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
779 (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) {
780 uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) |
781 ((imm32 >> 19) & ((1 << 6) -1));
782 EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf),
783 sd, S0, S0);
784 return true;
785 }
786 return false;
787}
788
789
Ian Rogers2c8f6532011-09-02 17:16:34 -0700790bool ArmAssembler::vmovd(DRegister dd, double d_imm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700791 uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
792 if (((imm64 & ((1LL << 48) - 1)) == 0) &&
793 ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
794 (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) {
795 uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) |
796 ((imm64 >> 48) & ((1 << 6) -1));
797 EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf),
798 dd, D0, D0);
799 return true;
800 }
801 return false;
802}
803
804
Ian Rogers2c8f6532011-09-02 17:16:34 -0700805void ArmAssembler::vadds(SRegister sd, SRegister sn, SRegister sm,
806 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700807 EmitVFPsss(cond, B21 | B20, sd, sn, sm);
808}
809
810
Ian Rogers2c8f6532011-09-02 17:16:34 -0700811void ArmAssembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
812 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700813 EmitVFPddd(cond, B21 | B20, dd, dn, dm);
814}
815
816
Ian Rogers2c8f6532011-09-02 17:16:34 -0700817void ArmAssembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
818 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700819 EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
820}
821
822
Ian Rogers2c8f6532011-09-02 17:16:34 -0700823void ArmAssembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
824 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700825 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
826}
827
828
Ian Rogers2c8f6532011-09-02 17:16:34 -0700829void ArmAssembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
830 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700831 EmitVFPsss(cond, B21, sd, sn, sm);
832}
833
834
Ian Rogers2c8f6532011-09-02 17:16:34 -0700835void ArmAssembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
836 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700837 EmitVFPddd(cond, B21, dd, dn, dm);
838}
839
840
Ian Rogers2c8f6532011-09-02 17:16:34 -0700841void ArmAssembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
842 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700843 EmitVFPsss(cond, 0, sd, sn, sm);
844}
845
846
Ian Rogers2c8f6532011-09-02 17:16:34 -0700847void ArmAssembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
848 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700849 EmitVFPddd(cond, 0, dd, dn, dm);
850}
851
852
Ian Rogers2c8f6532011-09-02 17:16:34 -0700853void ArmAssembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
854 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700855 EmitVFPsss(cond, B6, sd, sn, sm);
856}
857
858
Ian Rogers2c8f6532011-09-02 17:16:34 -0700859void ArmAssembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
860 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700861 EmitVFPddd(cond, B6, dd, dn, dm);
862}
863
864
Ian Rogers2c8f6532011-09-02 17:16:34 -0700865void ArmAssembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
866 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700867 EmitVFPsss(cond, B23, sd, sn, sm);
868}
869
870
Ian Rogers2c8f6532011-09-02 17:16:34 -0700871void ArmAssembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
872 Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700873 EmitVFPddd(cond, B23, dd, dn, dm);
874}
875
876
Ian Rogers2c8f6532011-09-02 17:16:34 -0700877void ArmAssembler::vabss(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700878 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
879}
880
881
Ian Rogers2c8f6532011-09-02 17:16:34 -0700882void ArmAssembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700883 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
884}
885
886
Ian Rogers2c8f6532011-09-02 17:16:34 -0700887void ArmAssembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700888 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
889}
890
891
Ian Rogers2c8f6532011-09-02 17:16:34 -0700892void ArmAssembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700893 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
894}
895
896
Ian Rogers2c8f6532011-09-02 17:16:34 -0700897void ArmAssembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700898 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
899}
900
Ian Rogers2c8f6532011-09-02 17:16:34 -0700901void ArmAssembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700902 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
903}
904
905
Ian Rogers2c8f6532011-09-02 17:16:34 -0700906void ArmAssembler::EmitVFPsd(Condition cond, int32_t opcode,
907 SRegister sd, DRegister dm) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700908 CHECK_NE(sd, kNoSRegister);
909 CHECK_NE(dm, kNoDRegister);
910 CHECK_NE(cond, kNoCondition);
911 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
912 B27 | B26 | B25 | B11 | B9 | opcode |
913 ((static_cast<int32_t>(sd) & 1)*B22) |
914 ((static_cast<int32_t>(sd) >> 1)*B12) |
915 ((static_cast<int32_t>(dm) >> 4)*B5) |
916 (static_cast<int32_t>(dm) & 0xf);
917 Emit(encoding);
918}
919
920
Ian Rogers2c8f6532011-09-02 17:16:34 -0700921void ArmAssembler::EmitVFPds(Condition cond, int32_t opcode,
922 DRegister dd, SRegister sm) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700923 CHECK_NE(dd, kNoDRegister);
924 CHECK_NE(sm, kNoSRegister);
925 CHECK_NE(cond, kNoCondition);
926 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
927 B27 | B26 | B25 | B11 | B9 | opcode |
928 ((static_cast<int32_t>(dd) >> 4)*B22) |
929 ((static_cast<int32_t>(dd) & 0xf)*B12) |
930 ((static_cast<int32_t>(sm) & 1)*B5) |
931 (static_cast<int32_t>(sm) >> 1);
932 Emit(encoding);
933}
934
935
Ian Rogers2c8f6532011-09-02 17:16:34 -0700936void ArmAssembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700937 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
938}
939
940
Ian Rogers2c8f6532011-09-02 17:16:34 -0700941void ArmAssembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700942 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
943}
944
945
Ian Rogers2c8f6532011-09-02 17:16:34 -0700946void ArmAssembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700947 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
948}
949
950
Ian Rogers2c8f6532011-09-02 17:16:34 -0700951void ArmAssembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700952 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
953}
954
955
Ian Rogers2c8f6532011-09-02 17:16:34 -0700956void ArmAssembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700957 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm);
958}
959
960
Ian Rogers2c8f6532011-09-02 17:16:34 -0700961void ArmAssembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700962 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm);
963}
964
965
Ian Rogers2c8f6532011-09-02 17:16:34 -0700966void ArmAssembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700967 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
968}
969
970
Ian Rogers2c8f6532011-09-02 17:16:34 -0700971void ArmAssembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700972 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
973}
974
975
Ian Rogers2c8f6532011-09-02 17:16:34 -0700976void ArmAssembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700977 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
978}
979
980
Ian Rogers2c8f6532011-09-02 17:16:34 -0700981void ArmAssembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700982 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
983}
984
985
Ian Rogers2c8f6532011-09-02 17:16:34 -0700986void ArmAssembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700987 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
988}
989
990
Ian Rogers2c8f6532011-09-02 17:16:34 -0700991void ArmAssembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700992 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
993}
994
995
Ian Rogers2c8f6532011-09-02 17:16:34 -0700996void ArmAssembler::vcmpsz(SRegister sd, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -0700997 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
998}
999
1000
Ian Rogers2c8f6532011-09-02 17:16:34 -07001001void ArmAssembler::vcmpdz(DRegister dd, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001002 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
1003}
1004
1005
Ian Rogers2c8f6532011-09-02 17:16:34 -07001006void ArmAssembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001007 CHECK_NE(cond, kNoCondition);
1008 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1009 B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
1010 (static_cast<int32_t>(PC)*B12) |
1011 B11 | B9 | B4;
1012 Emit(encoding);
1013}
1014
1015
Ian Rogers2c8f6532011-09-02 17:16:34 -07001016void ArmAssembler::svc(uint32_t imm24) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001017 CHECK(IsUint(24, imm24));
1018 int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
1019 Emit(encoding);
1020}
1021
1022
Ian Rogers2c8f6532011-09-02 17:16:34 -07001023void ArmAssembler::bkpt(uint16_t imm16) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001024 int32_t encoding = (AL << kConditionShift) | B24 | B21 |
1025 ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf);
1026 Emit(encoding);
1027}
1028
1029
Ian Rogers2c8f6532011-09-02 17:16:34 -07001030void ArmAssembler::b(Label* label, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001031 EmitBranch(cond, label, false);
1032}
1033
1034
Ian Rogers2c8f6532011-09-02 17:16:34 -07001035void ArmAssembler::bl(Label* label, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001036 EmitBranch(cond, label, true);
1037}
1038
1039
Ian Rogers2c8f6532011-09-02 17:16:34 -07001040void ArmAssembler::blx(Register rm, Condition cond) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001041 CHECK_NE(rm, kNoRegister);
1042 CHECK_NE(cond, kNoCondition);
1043 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1044 B24 | B21 | (0xfff << 8) | B5 | B4 |
1045 (static_cast<int32_t>(rm) << kRmShift);
1046 Emit(encoding);
1047}
1048
1049
Ian Rogers2c8f6532011-09-02 17:16:34 -07001050void ArmAssembler::MarkExceptionHandler(Label* label) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001051 EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0));
1052 Label l;
1053 b(&l);
1054 EmitBranch(AL, label, false);
1055 Bind(&l);
1056}
1057
1058
Ian Rogers2c8f6532011-09-02 17:16:34 -07001059void ArmAssembler::Bind(Label* label) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001060 CHECK(!label->IsBound());
1061 int bound_pc = buffer_.Size();
1062 while (label->IsLinked()) {
1063 int32_t position = label->Position();
1064 int32_t next = buffer_.Load<int32_t>(position);
Ian Rogers2c8f6532011-09-02 17:16:34 -07001065 int32_t encoded = ArmAssembler::EncodeBranchOffset(bound_pc - position, next);
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001066 buffer_.Store<int32_t>(position, encoded);
Ian Rogers2c8f6532011-09-02 17:16:34 -07001067 label->position_ = ArmAssembler::DecodeBranchOffset(next);
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001068 }
1069 label->BindTo(bound_pc);
1070}
1071
1072
Ian Rogers2c8f6532011-09-02 17:16:34 -07001073void ArmAssembler::EncodeUint32InTstInstructions(uint32_t data) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001074 // TODO: Consider using movw ip, <16 bits>.
1075 while (!IsUint(8, data)) {
1076 tst(R0, ShifterOperand(data & 0xFF), VS);
1077 data >>= 8;
1078 }
1079 tst(R0, ShifterOperand(data), MI);
1080}
1081
Ian Rogersb033c752011-07-20 12:22:35 -07001082
Ian Rogers2c8f6532011-09-02 17:16:34 -07001083int32_t ArmAssembler::EncodeBranchOffset(int offset, int32_t inst) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001084 // The offset is off by 8 due to the way the ARM CPUs read PC.
1085 offset -= 8;
1086 CHECK(IsAligned(offset, 4));
1087 CHECK(IsInt(CountOneBits(kBranchOffsetMask), offset));
1088
1089 // Properly preserve only the bits supported in the instruction.
1090 offset >>= 2;
1091 offset &= kBranchOffsetMask;
1092 return (inst & ~kBranchOffsetMask) | offset;
1093}
1094
1095
Ian Rogers2c8f6532011-09-02 17:16:34 -07001096int ArmAssembler::DecodeBranchOffset(int32_t inst) {
Carl Shapiroa2e18e12011-06-21 18:57:55 -07001097 // Sign-extend, left-shift by 2, then add 8.
1098 return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8);
1099}
1100
Ian Rogers2c8f6532011-09-02 17:16:34 -07001101void ArmAssembler::AddConstant(Register rd, int32_t value, Condition cond) {
Ian Rogersb033c752011-07-20 12:22:35 -07001102 AddConstant(rd, rd, value, cond);
1103}
1104
1105
Ian Rogers2c8f6532011-09-02 17:16:34 -07001106void ArmAssembler::AddConstant(Register rd, Register rn, int32_t value,
1107 Condition cond) {
Ian Rogersb033c752011-07-20 12:22:35 -07001108 if (value == 0) {
1109 if (rd != rn) {
1110 mov(rd, ShifterOperand(rn), cond);
1111 }
1112 return;
1113 }
1114 // We prefer to select the shorter code sequence rather than selecting add for
1115 // positive values and sub for negatives ones, which would slightly improve
1116 // the readability of generated code for some constants.
1117 ShifterOperand shifter_op;
1118 if (ShifterOperand::CanHold(value, &shifter_op)) {
1119 add(rd, rn, shifter_op, cond);
1120 } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
1121 sub(rd, rn, shifter_op, cond);
1122 } else {
1123 CHECK(rn != IP);
1124 if (ShifterOperand::CanHold(~value, &shifter_op)) {
1125 mvn(IP, shifter_op, cond);
1126 add(rd, rn, ShifterOperand(IP), cond);
1127 } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
1128 mvn(IP, shifter_op, cond);
1129 sub(rd, rn, ShifterOperand(IP), cond);
1130 } else {
1131 movw(IP, Low16Bits(value), cond);
1132 uint16_t value_high = High16Bits(value);
1133 if (value_high != 0) {
1134 movt(IP, value_high, cond);
1135 }
1136 add(rd, rn, ShifterOperand(IP), cond);
1137 }
1138 }
1139}
1140
1141
Ian Rogers2c8f6532011-09-02 17:16:34 -07001142void ArmAssembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
1143 Condition cond) {
Ian Rogersb033c752011-07-20 12:22:35 -07001144 ShifterOperand shifter_op;
1145 if (ShifterOperand::CanHold(value, &shifter_op)) {
1146 adds(rd, rn, shifter_op, cond);
1147 } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
1148 subs(rd, rn, shifter_op, cond);
1149 } else {
1150 CHECK(rn != IP);
1151 if (ShifterOperand::CanHold(~value, &shifter_op)) {
1152 mvn(IP, shifter_op, cond);
1153 adds(rd, rn, ShifterOperand(IP), cond);
1154 } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
1155 mvn(IP, shifter_op, cond);
1156 subs(rd, rn, ShifterOperand(IP), cond);
1157 } else {
1158 movw(IP, Low16Bits(value), cond);
1159 uint16_t value_high = High16Bits(value);
1160 if (value_high != 0) {
1161 movt(IP, value_high, cond);
1162 }
1163 adds(rd, rn, ShifterOperand(IP), cond);
1164 }
1165 }
1166}
1167
1168
Ian Rogers2c8f6532011-09-02 17:16:34 -07001169void ArmAssembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
Ian Rogersb033c752011-07-20 12:22:35 -07001170 ShifterOperand shifter_op;
1171 if (ShifterOperand::CanHold(value, &shifter_op)) {
1172 mov(rd, shifter_op, cond);
1173 } else if (ShifterOperand::CanHold(~value, &shifter_op)) {
1174 mvn(rd, shifter_op, cond);
1175 } else {
1176 movw(rd, Low16Bits(value), cond);
1177 uint16_t value_high = High16Bits(value);
1178 if (value_high != 0) {
1179 movt(rd, value_high, cond);
1180 }
1181 }
1182}
1183
1184
1185bool Address::CanHoldLoadOffset(LoadOperandType type, int offset) {
1186 switch (type) {
1187 case kLoadSignedByte:
1188 case kLoadSignedHalfword:
1189 case kLoadUnsignedHalfword:
1190 case kLoadWordPair:
1191 return IsAbsoluteUint(8, offset); // Addressing mode 3.
1192 case kLoadUnsignedByte:
1193 case kLoadWord:
1194 return IsAbsoluteUint(12, offset); // Addressing mode 2.
1195 case kLoadSWord:
1196 case kLoadDWord:
1197 return IsAbsoluteUint(10, offset); // VFP addressing mode.
1198 default:
1199 LOG(FATAL) << "UNREACHABLE";
1200 return false;
1201 }
1202}
1203
1204
1205bool Address::CanHoldStoreOffset(StoreOperandType type, int offset) {
1206 switch (type) {
1207 case kStoreHalfword:
1208 case kStoreWordPair:
1209 return IsAbsoluteUint(8, offset); // Addressing mode 3.
1210 case kStoreByte:
1211 case kStoreWord:
1212 return IsAbsoluteUint(12, offset); // Addressing mode 2.
1213 case kStoreSWord:
1214 case kStoreDWord:
1215 return IsAbsoluteUint(10, offset); // VFP addressing mode.
1216 default:
1217 LOG(FATAL) << "UNREACHABLE";
1218 return false;
1219 }
1220}
1221
1222
1223// Implementation note: this method must emit at most one instruction when
1224// Address::CanHoldLoadOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001225void ArmAssembler::LoadFromOffset(LoadOperandType type,
Ian Rogersb033c752011-07-20 12:22:35 -07001226 Register reg,
1227 Register base,
1228 int32_t offset,
1229 Condition cond) {
1230 if (!Address::CanHoldLoadOffset(type, offset)) {
1231 CHECK(base != IP);
1232 LoadImmediate(IP, offset, cond);
1233 add(IP, IP, ShifterOperand(base), cond);
1234 base = IP;
1235 offset = 0;
1236 }
1237 CHECK(Address::CanHoldLoadOffset(type, offset));
1238 switch (type) {
1239 case kLoadSignedByte:
1240 ldrsb(reg, Address(base, offset), cond);
1241 break;
1242 case kLoadUnsignedByte:
1243 ldrb(reg, Address(base, offset), cond);
1244 break;
1245 case kLoadSignedHalfword:
1246 ldrsh(reg, Address(base, offset), cond);
1247 break;
1248 case kLoadUnsignedHalfword:
1249 ldrh(reg, Address(base, offset), cond);
1250 break;
1251 case kLoadWord:
1252 ldr(reg, Address(base, offset), cond);
1253 break;
1254 case kLoadWordPair:
1255 ldrd(reg, Address(base, offset), cond);
1256 break;
1257 default:
1258 LOG(FATAL) << "UNREACHABLE";
1259 }
1260}
1261
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001262// Implementation note: this method must emit at most one instruction when
1263// Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001264void ArmAssembler::LoadSFromOffset(SRegister reg,
1265 Register base,
1266 int32_t offset,
1267 Condition cond) {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001268 if (!Address::CanHoldLoadOffset(kLoadSWord, offset)) {
1269 CHECK_NE(base, IP);
1270 LoadImmediate(IP, offset, cond);
1271 add(IP, IP, ShifterOperand(base), cond);
1272 base = IP;
1273 offset = 0;
1274 }
1275 CHECK(Address::CanHoldLoadOffset(kLoadSWord, offset));
1276 vldrs(reg, Address(base, offset), cond);
1277}
1278
1279// Implementation note: this method must emit at most one instruction when
1280// Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001281void ArmAssembler::LoadDFromOffset(DRegister reg,
1282 Register base,
1283 int32_t offset,
1284 Condition cond) {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001285 if (!Address::CanHoldLoadOffset(kLoadDWord, offset)) {
1286 CHECK_NE(base, IP);
1287 LoadImmediate(IP, offset, cond);
1288 add(IP, IP, ShifterOperand(base), cond);
1289 base = IP;
1290 offset = 0;
1291 }
1292 CHECK(Address::CanHoldLoadOffset(kLoadDWord, offset));
1293 vldrd(reg, Address(base, offset), cond);
1294}
Ian Rogersb033c752011-07-20 12:22:35 -07001295
1296// Implementation note: this method must emit at most one instruction when
1297// Address::CanHoldStoreOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001298void ArmAssembler::StoreToOffset(StoreOperandType type,
1299 Register reg,
1300 Register base,
1301 int32_t offset,
1302 Condition cond) {
Ian Rogersb033c752011-07-20 12:22:35 -07001303 if (!Address::CanHoldStoreOffset(type, offset)) {
1304 CHECK(reg != IP);
1305 CHECK(base != IP);
1306 LoadImmediate(IP, offset, cond);
1307 add(IP, IP, ShifterOperand(base), cond);
1308 base = IP;
1309 offset = 0;
1310 }
1311 CHECK(Address::CanHoldStoreOffset(type, offset));
1312 switch (type) {
1313 case kStoreByte:
1314 strb(reg, Address(base, offset), cond);
1315 break;
1316 case kStoreHalfword:
1317 strh(reg, Address(base, offset), cond);
1318 break;
1319 case kStoreWord:
1320 str(reg, Address(base, offset), cond);
1321 break;
1322 case kStoreWordPair:
1323 strd(reg, Address(base, offset), cond);
1324 break;
1325 default:
1326 LOG(FATAL) << "UNREACHABLE";
1327 }
1328}
1329
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001330// Implementation note: this method must emit at most one instruction when
1331// Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreToOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001332void ArmAssembler::StoreSToOffset(SRegister reg,
1333 Register base,
1334 int32_t offset,
1335 Condition cond) {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001336 if (!Address::CanHoldStoreOffset(kStoreSWord, offset)) {
1337 CHECK_NE(base, IP);
1338 LoadImmediate(IP, offset, cond);
1339 add(IP, IP, ShifterOperand(base), cond);
1340 base = IP;
1341 offset = 0;
1342 }
1343 CHECK(Address::CanHoldStoreOffset(kStoreSWord, offset));
1344 vstrs(reg, Address(base, offset), cond);
1345}
1346
1347// Implementation note: this method must emit at most one instruction when
1348// Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreSToOffset.
Ian Rogers2c8f6532011-09-02 17:16:34 -07001349void ArmAssembler::StoreDToOffset(DRegister reg,
1350 Register base,
1351 int32_t offset,
1352 Condition cond) {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001353 if (!Address::CanHoldStoreOffset(kStoreDWord, offset)) {
1354 CHECK_NE(base, IP);
1355 LoadImmediate(IP, offset, cond);
1356 add(IP, IP, ShifterOperand(base), cond);
1357 base = IP;
1358 offset = 0;
1359 }
1360 CHECK(Address::CanHoldStoreOffset(kStoreDWord, offset));
1361 vstrd(reg, Address(base, offset), cond);
1362}
1363
Ian Rogers2c8f6532011-09-02 17:16:34 -07001364void ArmAssembler::Push(Register rd, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001365 str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond);
1366}
1367
Ian Rogers2c8f6532011-09-02 17:16:34 -07001368void ArmAssembler::Pop(Register rd, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001369 ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond);
1370}
1371
Ian Rogers2c8f6532011-09-02 17:16:34 -07001372void ArmAssembler::PushList(RegList regs, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001373 stm(DB_W, SP, regs, cond);
1374}
1375
Ian Rogers2c8f6532011-09-02 17:16:34 -07001376void ArmAssembler::PopList(RegList regs, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001377 ldm(IA_W, SP, regs, cond);
1378}
1379
Ian Rogers2c8f6532011-09-02 17:16:34 -07001380void ArmAssembler::Mov(Register rd, Register rm, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001381 if (rd != rm) {
1382 mov(rd, ShifterOperand(rm), cond);
1383 }
1384}
1385
Ian Rogers2c8f6532011-09-02 17:16:34 -07001386void ArmAssembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
1387 Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001388 CHECK_NE(shift_imm, 0u); // Do not use Lsl if no shift is wanted.
1389 mov(rd, ShifterOperand(rm, LSL, shift_imm), cond);
1390}
1391
Ian Rogers2c8f6532011-09-02 17:16:34 -07001392void ArmAssembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
1393 Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001394 CHECK_NE(shift_imm, 0u); // Do not use Lsr if no shift is wanted.
1395 if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax.
1396 mov(rd, ShifterOperand(rm, LSR, shift_imm), cond);
1397}
1398
Ian Rogers2c8f6532011-09-02 17:16:34 -07001399void ArmAssembler::Asr(Register rd, Register rm, uint32_t shift_imm,
1400 Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001401 CHECK_NE(shift_imm, 0u); // Do not use Asr if no shift is wanted.
1402 if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax.
1403 mov(rd, ShifterOperand(rm, ASR, shift_imm), cond);
1404}
1405
Ian Rogers2c8f6532011-09-02 17:16:34 -07001406void ArmAssembler::Ror(Register rd, Register rm, uint32_t shift_imm,
1407 Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001408 CHECK_NE(shift_imm, 0u); // Use Rrx instruction.
1409 mov(rd, ShifterOperand(rm, ROR, shift_imm), cond);
1410}
1411
Ian Rogers2c8f6532011-09-02 17:16:34 -07001412void ArmAssembler::Rrx(Register rd, Register rm, Condition cond) {
Carl Shapiro9b9ba282011-08-14 15:30:39 -07001413 mov(rd, ShifterOperand(rm, ROR, 0), cond);
1414}
1415
Ian Rogers2c8f6532011-09-02 17:16:34 -07001416void ArmAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
1417 const std::vector<ManagedRegister>& spill_regs) {
Ian Rogers0d666d82011-08-14 16:03:46 -07001418 CHECK(IsAligned(frame_size, kStackAlignment));
Ian Rogers2c8f6532011-09-02 17:16:34 -07001419 CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister());
Ian Rogersb033c752011-07-20 12:22:35 -07001420 AddConstant(SP, -frame_size);
Ian Rogers0d666d82011-08-14 16:03:46 -07001421 RegList spill_list = 1 << R0 | 1 << LR;
Ian Rogers0cfe1fb2011-08-26 03:29:44 -07001422 for (size_t i = 0; i < spill_regs.size(); i++) {
Ian Rogers2c8f6532011-09-02 17:16:34 -07001423 Register reg = spill_regs.at(i).AsArm().AsCoreRegister();
Ian Rogers0d666d82011-08-14 16:03:46 -07001424 // check assumption LR is the last register that gets spilled
1425 CHECK_LT(reg, LR);
1426 spill_list |= 1 << reg;
1427 }
1428 // Store spill list from (low to high number register) starting at SP
1429 // incrementing after each store but not updating SP
1430 stm(IA, SP, spill_list, AL);
Ian Rogersb033c752011-07-20 12:22:35 -07001431}
1432
Ian Rogers2c8f6532011-09-02 17:16:34 -07001433void ArmAssembler::RemoveFrame(size_t frame_size,
1434 const std::vector<ManagedRegister>& spill_regs) {
Ian Rogers0d666d82011-08-14 16:03:46 -07001435 CHECK(IsAligned(frame_size, kStackAlignment));
1436 // Reload LR. TODO: reload any saved callee saves from spill_regs
1437 LoadFromOffset(kLoadWord, LR, SP, (spill_regs.size() + 1) * kPointerSize);
Ian Rogersb033c752011-07-20 12:22:35 -07001438 AddConstant(SP, frame_size);
1439 mov(PC, ShifterOperand(LR));
1440}
1441
Ian Rogers2c8f6532011-09-02 17:16:34 -07001442void ArmAssembler::FillFromSpillArea(const std::vector<ManagedRegister>& spill_regs,
1443 size_t displacement) {
Ian Rogers0d666d82011-08-14 16:03:46 -07001444 for(size_t i = 0; i < spill_regs.size(); i++) {
Ian Rogers2c8f6532011-09-02 17:16:34 -07001445 Register reg = spill_regs.at(i).AsArm().AsCoreRegister();
Ian Rogers0d666d82011-08-14 16:03:46 -07001446 LoadFromOffset(kLoadWord, reg, SP, displacement + ((i + 1) * kPointerSize));
1447 }
1448}
1449
Ian Rogers2c8f6532011-09-02 17:16:34 -07001450void ArmAssembler::IncreaseFrameSize(size_t adjust) {
Ian Rogers0d666d82011-08-14 16:03:46 -07001451 CHECK(IsAligned(adjust, kStackAlignment));
Ian Rogersb033c752011-07-20 12:22:35 -07001452 AddConstant(SP, -adjust);
1453}
1454
Ian Rogers2c8f6532011-09-02 17:16:34 -07001455void ArmAssembler::DecreaseFrameSize(size_t adjust) {
Ian Rogers0d666d82011-08-14 16:03:46 -07001456 CHECK(IsAligned(adjust, kStackAlignment));
Ian Rogersb033c752011-07-20 12:22:35 -07001457 AddConstant(SP, adjust);
1458}
1459
Ian Rogers2c8f6532011-09-02 17:16:34 -07001460void ArmAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
1461 ArmManagedRegister src = msrc.AsArm();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001462 if (src.IsNoRegister()) {
1463 CHECK_EQ(0u, size);
1464 } else if (src.IsCoreRegister()) {
Ian Rogersb033c752011-07-20 12:22:35 -07001465 CHECK_EQ(4u, size);
1466 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001467 } else if (src.IsRegisterPair()) {
1468 CHECK_EQ(8u, size);
1469 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
1470 StoreToOffset(kStoreWord, src.AsRegisterPairHigh(),
1471 SP, dest.Int32Value() + 4);
1472 } else if (src.IsSRegister()) {
1473 StoreSToOffset(src.AsSRegister(), SP, dest.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -07001474 } else {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001475 CHECK(src.IsDRegister());
1476 StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -07001477 }
1478}
1479
Ian Rogers2c8f6532011-09-02 17:16:34 -07001480void ArmAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
1481 ArmManagedRegister src = msrc.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001482 CHECK(src.IsCoreRegister());
1483 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
1484}
1485
Ian Rogers2c8f6532011-09-02 17:16:34 -07001486void ArmAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
1487 ArmManagedRegister src = msrc.AsArm();
Ian Rogersdf20fe02011-07-20 20:34:16 -07001488 CHECK(src.IsCoreRegister());
1489 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
1490}
1491
Ian Rogers2c8f6532011-09-02 17:16:34 -07001492void ArmAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc,
1493 FrameOffset in_off, ManagedRegister mscratch) {
1494 ArmManagedRegister src = msrc.AsArm();
1495 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogers7a99c112011-09-07 12:48:27 -07001496 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
1497 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
1498 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
1499}
1500
Ian Rogers2c8f6532011-09-02 17:16:34 -07001501void ArmAssembler::CopyRef(FrameOffset dest, FrameOffset src,
1502 ManagedRegister mscratch) {
1503 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001504 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
1505 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
1506}
1507
Ian Rogers2c8f6532011-09-02 17:16:34 -07001508void ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
1509 MemberOffset offs) {
1510 ArmManagedRegister dest = mdest.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001511 CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
1512 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
Ian Rogers2c8f6532011-09-02 17:16:34 -07001513 base.AsArm().AsCoreRegister(), offs.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -07001514}
1515
Ian Rogers2c8f6532011-09-02 17:16:34 -07001516void ArmAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) {
1517 ArmManagedRegister dest = mdest.AsArm();
1518 CHECK(dest.IsCoreRegister());
1519 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
1520 SP, src.Int32Value());
1521 }
1522
1523void ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
Ian Rogersa04d3972011-08-17 11:33:44 -07001524 Offset offs) {
Ian Rogers2c8f6532011-09-02 17:16:34 -07001525 ArmManagedRegister dest = mdest.AsArm();
Ian Rogersa04d3972011-08-17 11:33:44 -07001526 CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
1527 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
Ian Rogers2c8f6532011-09-02 17:16:34 -07001528 base.AsArm().AsCoreRegister(), offs.Int32Value());
Ian Rogersa04d3972011-08-17 11:33:44 -07001529}
1530
Ian Rogers2c8f6532011-09-02 17:16:34 -07001531void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
1532 ManagedRegister mscratch) {
1533 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001534 CHECK(scratch.IsCoreRegister());
1535 LoadImmediate(scratch.AsCoreRegister(), imm);
1536 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
1537}
1538
Ian Rogers2c8f6532011-09-02 17:16:34 -07001539void ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
1540 ManagedRegister mscratch) {
1541 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001542 CHECK(scratch.IsCoreRegister());
1543 LoadImmediate(scratch.AsCoreRegister(), imm);
1544 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value());
1545}
1546
Ian Rogers2c8f6532011-09-02 17:16:34 -07001547void ArmAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
1548 ArmManagedRegister dest = mdest.AsArm();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001549 if (dest.IsNoRegister()) {
1550 CHECK_EQ(0u, size);
1551 } else if (dest.IsCoreRegister()) {
Ian Rogersb033c752011-07-20 12:22:35 -07001552 CHECK_EQ(4u, size);
1553 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value());
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001554 } else if (dest.IsRegisterPair()) {
1555 CHECK_EQ(8u, size);
1556 LoadFromOffset(kLoadWord, dest.AsRegisterPairLow(), SP, src.Int32Value());
1557 LoadFromOffset(kLoadWord, dest.AsRegisterPairHigh(),
1558 SP, src.Int32Value() + 4);
1559 } else if (dest.IsSRegister()) {
1560 LoadSFromOffset(dest.AsSRegister(), SP, src.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -07001561 } else {
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001562 CHECK(dest.IsDRegister());
1563 LoadDFromOffset(dest.AsDRegister(), SP, src.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -07001564 }
1565}
1566
Ian Rogers2c8f6532011-09-02 17:16:34 -07001567void ArmAssembler::LoadRawPtrFromThread(ManagedRegister mdest,
1568 ThreadOffset offs) {
1569 ArmManagedRegister dest = mdest.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001570 CHECK(dest.IsCoreRegister());
1571 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
1572 TR, offs.Int32Value());
1573}
1574
Ian Rogers2c8f6532011-09-02 17:16:34 -07001575void ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
1576 ThreadOffset thr_offs,
1577 ManagedRegister mscratch) {
1578 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001579 CHECK(scratch.IsCoreRegister());
1580 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1581 TR, thr_offs.Int32Value());
1582 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1583 SP, fr_offs.Int32Value());
1584}
1585
Ian Rogers2c8f6532011-09-02 17:16:34 -07001586void ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs,
1587 FrameOffset fr_offs,
1588 ManagedRegister mscratch) {
1589 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001590 CHECK(scratch.IsCoreRegister());
1591 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1592 SP, fr_offs.Int32Value());
1593 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1594 TR, thr_offs.Int32Value());
1595}
1596
Ian Rogers2c8f6532011-09-02 17:16:34 -07001597void ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
1598 FrameOffset fr_offs,
1599 ManagedRegister mscratch) {
1600 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001601 CHECK(scratch.IsCoreRegister());
1602 AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value(), AL);
1603 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1604 TR, thr_offs.Int32Value());
1605}
1606
Ian Rogers2c8f6532011-09-02 17:16:34 -07001607void ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
Ian Rogers45a76cb2011-07-21 22:00:15 -07001608 StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
1609}
1610
Ian Rogers2c8f6532011-09-02 17:16:34 -07001611void ArmAssembler::Move(ManagedRegister mdest, ManagedRegister msrc) {
1612 ArmManagedRegister dest = mdest.AsArm();
1613 ArmManagedRegister src = msrc.AsArm();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001614 if (!dest.Equals(src)) {
1615 if (dest.IsCoreRegister()) {
1616 CHECK(src.IsCoreRegister());
1617 mov(dest.AsCoreRegister(), ShifterOperand(src.AsCoreRegister()));
Ian Rogers7a99c112011-09-07 12:48:27 -07001618 } else if (dest.IsDRegister()) {
1619 CHECK(src.IsDRegister());
1620 vmovd(dest.AsDRegister(), src.AsDRegister());
1621 } else if (dest.IsSRegister()) {
1622 CHECK(src.IsSRegister());
1623 vmovs(dest.AsSRegister(), src.AsSRegister());
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001624 } else {
Ian Rogers7a99c112011-09-07 12:48:27 -07001625 CHECK(dest.IsRegisterPair());
1626 CHECK(src.IsRegisterPair());
1627 // Ensure that the first move doesn't clobber the input of the second
1628 if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) {
1629 mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow()));
1630 mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh()));
1631 } else {
1632 mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh()));
1633 mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow()));
1634 }
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001635 }
Ian Rogersb033c752011-07-20 12:22:35 -07001636 }
1637}
1638
Ian Rogers2c8f6532011-09-02 17:16:34 -07001639void ArmAssembler::Copy(FrameOffset dest, FrameOffset src,
1640 ManagedRegister mscratch, size_t size) {
1641 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001642 CHECK(scratch.IsCoreRegister());
Shih-wei Liao5381cf92011-07-27 00:28:04 -07001643 CHECK(size == 4 || size == 8);
Ian Rogersb033c752011-07-20 12:22:35 -07001644 if (size == 4) {
1645 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1646 SP, src.Int32Value());
1647 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1648 SP, dest.Int32Value());
Shih-wei Liao5381cf92011-07-27 00:28:04 -07001649 } else if (size == 8) {
1650 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1651 SP, src.Int32Value());
1652 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1653 SP, dest.Int32Value());
1654 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1655 SP, src.Int32Value() + 4);
1656 StoreToOffset(kStoreWord, scratch.AsCoreRegister(),
1657 SP, dest.Int32Value() + 4);
Ian Rogersb033c752011-07-20 12:22:35 -07001658 }
1659}
1660
Ian Rogers2c8f6532011-09-02 17:16:34 -07001661void ArmAssembler::CreateSirtEntry(ManagedRegister mout_reg,
1662 FrameOffset sirt_offset,
1663 ManagedRegister min_reg, bool null_allowed) {
1664 ArmManagedRegister out_reg = mout_reg.AsArm();
1665 ArmManagedRegister in_reg = min_reg.AsArm();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001666 CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister());
Ian Rogersb033c752011-07-20 12:22:35 -07001667 CHECK(out_reg.IsCoreRegister());
1668 if (null_allowed) {
Ian Rogers408f79a2011-08-23 18:22:33 -07001669 // Null values get a SIRT entry value of 0. Otherwise, the SIRT entry is
1670 // the address in the SIRT holding the reference.
Ian Rogersb033c752011-07-20 12:22:35 -07001671 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001672 if (in_reg.IsNoRegister()) {
1673 LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(),
Ian Rogers408f79a2011-08-23 18:22:33 -07001674 SP, sirt_offset.Int32Value());
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001675 in_reg = out_reg;
1676 }
Ian Rogersb033c752011-07-20 12:22:35 -07001677 cmp(in_reg.AsCoreRegister(), ShifterOperand(0));
1678 if (!out_reg.Equals(in_reg)) {
1679 LoadImmediate(out_reg.AsCoreRegister(), 0, EQ);
1680 }
Ian Rogers408f79a2011-08-23 18:22:33 -07001681 AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE);
Ian Rogersb033c752011-07-20 12:22:35 -07001682 } else {
Ian Rogers408f79a2011-08-23 18:22:33 -07001683 AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL);
Ian Rogersb033c752011-07-20 12:22:35 -07001684 }
1685}
1686
Ian Rogers2c8f6532011-09-02 17:16:34 -07001687void ArmAssembler::CreateSirtEntry(FrameOffset out_off,
1688 FrameOffset sirt_offset,
1689 ManagedRegister mscratch,
1690 bool null_allowed) {
1691 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001692 CHECK(scratch.IsCoreRegister());
1693 if (null_allowed) {
1694 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP,
Ian Rogers408f79a2011-08-23 18:22:33 -07001695 sirt_offset.Int32Value());
1696 // Null values get a SIRT entry value of 0. Otherwise, the sirt entry is
1697 // the address in the SIRT holding the reference.
1698 // e.g. scratch = (scratch == 0) ? 0 : (SP+sirt_offset)
Ian Rogersb033c752011-07-20 12:22:35 -07001699 cmp(scratch.AsCoreRegister(), ShifterOperand(0));
Ian Rogers408f79a2011-08-23 18:22:33 -07001700 AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE);
Ian Rogersb033c752011-07-20 12:22:35 -07001701 } else {
Ian Rogers408f79a2011-08-23 18:22:33 -07001702 AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL);
Ian Rogersb033c752011-07-20 12:22:35 -07001703 }
1704 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value());
1705}
1706
Ian Rogers2c8f6532011-09-02 17:16:34 -07001707void ArmAssembler::LoadReferenceFromSirt(ManagedRegister mout_reg,
1708 ManagedRegister min_reg) {
1709 ArmManagedRegister out_reg = mout_reg.AsArm();
1710 ArmManagedRegister in_reg = min_reg.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001711 CHECK(out_reg.IsCoreRegister());
1712 CHECK(in_reg.IsCoreRegister());
1713 Label null_arg;
1714 if (!out_reg.Equals(in_reg)) {
1715 LoadImmediate(out_reg.AsCoreRegister(), 0, EQ);
1716 }
1717 cmp(in_reg.AsCoreRegister(), ShifterOperand(0));
Ian Rogersdf20fe02011-07-20 20:34:16 -07001718 LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(),
1719 in_reg.AsCoreRegister(), 0, NE);
Ian Rogersb033c752011-07-20 12:22:35 -07001720}
1721
Ian Rogers2c8f6532011-09-02 17:16:34 -07001722void ArmAssembler::VerifyObject(ManagedRegister src, bool could_be_null) {
Ian Rogersb033c752011-07-20 12:22:35 -07001723 // TODO: not validating references
1724}
1725
Ian Rogers2c8f6532011-09-02 17:16:34 -07001726void ArmAssembler::VerifyObject(FrameOffset src, bool could_be_null) {
Ian Rogersb033c752011-07-20 12:22:35 -07001727 // TODO: not validating references
1728}
1729
Ian Rogers2c8f6532011-09-02 17:16:34 -07001730void ArmAssembler::Call(ManagedRegister mbase, Offset offset,
1731 ManagedRegister mscratch) {
1732 ArmManagedRegister base = mbase.AsArm();
1733 ArmManagedRegister scratch = mscratch.AsArm();
Ian Rogersb033c752011-07-20 12:22:35 -07001734 CHECK(base.IsCoreRegister());
1735 CHECK(scratch.IsCoreRegister());
1736 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1737 base.AsCoreRegister(), offset.Int32Value());
1738 blx(scratch.AsCoreRegister());
1739 // TODO: place reference map on call
1740}
1741
Ian Rogers2c8f6532011-09-02 17:16:34 -07001742void ArmAssembler::Call(FrameOffset base, Offset offset,
1743 ManagedRegister mscratch) {
1744 ArmManagedRegister scratch = mscratch.AsArm();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001745 CHECK(scratch.IsCoreRegister());
1746 // Call *(*(SP + base) + offset)
1747 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1748 SP, base.Int32Value());
1749 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1750 scratch.AsCoreRegister(), offset.Int32Value());
1751 blx(scratch.AsCoreRegister());
1752 // TODO: place reference map on call
1753}
1754
Ian Rogers2c8f6532011-09-02 17:16:34 -07001755void ArmAssembler::GetCurrentThread(ManagedRegister tr) {
1756 mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR));
Shih-wei Liao668512a2011-09-01 14:18:34 -07001757}
1758
Ian Rogers2c8f6532011-09-02 17:16:34 -07001759void ArmAssembler::GetCurrentThread(FrameOffset offset,
1760 ManagedRegister scratch) {
Shih-wei Liao668512a2011-09-01 14:18:34 -07001761 StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL);
1762}
1763
Ian Rogers2c8f6532011-09-02 17:16:34 -07001764void ArmAssembler::SuspendPoll(ManagedRegister mscratch,
1765 ManagedRegister return_reg,
1766 FrameOffset return_save_location,
1767 size_t return_size) {
1768 ArmManagedRegister scratch = mscratch.AsArm();
1769 ArmSuspendCountSlowPath* slow =
1770 new ArmSuspendCountSlowPath(return_reg.AsArm(), return_save_location,
1771 return_size);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001772 buffer_.EnqueueSlowPath(slow);
1773 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1774 TR, Thread::SuspendCountOffset().Int32Value());
1775 cmp(scratch.AsCoreRegister(), ShifterOperand(0));
1776 b(slow->Entry(), NE);
1777 Bind(slow->Continuation());
1778}
1779
Ian Rogers2c8f6532011-09-02 17:16:34 -07001780void ArmSuspendCountSlowPath::Emit(Assembler* sasm) {
1781 ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm);
1782#define __ sp_asm->
1783 __ Bind(&entry_);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001784 // Save return value
Ian Rogers2c8f6532011-09-02 17:16:34 -07001785 __ Store(return_save_location_, return_register_, return_size_);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001786 // Pass top of stack as argument
Ian Rogers2c8f6532011-09-02 17:16:34 -07001787 __ mov(R0, ShifterOperand(SP));
1788 __ LoadFromOffset(kLoadWord, R12, TR,
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001789 Thread::SuspendCountEntryPointOffset().Int32Value());
1790 // Note: assume that link register will be spilled/filled on method entry/exit
Ian Rogers2c8f6532011-09-02 17:16:34 -07001791 __ blx(R12);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001792 // Reload return value
Ian Rogers2c8f6532011-09-02 17:16:34 -07001793 __ Load(return_register_, return_save_location_, return_size_);
1794 __ b(&continuation_);
1795#undef __
Ian Rogers45a76cb2011-07-21 22:00:15 -07001796}
1797
Ian Rogers2c8f6532011-09-02 17:16:34 -07001798void ArmAssembler::ExceptionPoll(ManagedRegister mscratch) {
1799 ArmManagedRegister scratch = mscratch.AsArm();
1800 ArmExceptionSlowPath* slow = new ArmExceptionSlowPath();
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001801 buffer_.EnqueueSlowPath(slow);
1802 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
1803 TR, Thread::ExceptionOffset().Int32Value());
1804 cmp(scratch.AsCoreRegister(), ShifterOperand(0));
1805 b(slow->Entry(), NE);
1806 Bind(slow->Continuation());
1807}
1808
Ian Rogers2c8f6532011-09-02 17:16:34 -07001809void ArmExceptionSlowPath::Emit(Assembler* sasm) {
1810 ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm);
1811#define __ sp_asm->
1812 __ Bind(&entry_);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001813 // Pass top of stack as argument
Ian Rogers2c8f6532011-09-02 17:16:34 -07001814 __ mov(R0, ShifterOperand(SP));
1815 __ LoadFromOffset(kLoadWord, R12, TR,
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001816 Thread::ExceptionEntryPointOffset().Int32Value());
1817 // Note: assume that link register will be spilled/filled on method entry/exit
Ian Rogers2c8f6532011-09-02 17:16:34 -07001818 __ blx(R12);
Carl Shapiroe2d373e2011-07-25 15:20:06 -07001819 // TODO: this call should never return as it should make a long jump to
1820 // the appropriate catch block
Ian Rogers2c8f6532011-09-02 17:16:34 -07001821 __ b(&continuation_);
1822#undef __
Ian Rogers45a76cb2011-07-21 22:00:15 -07001823}
1824
Ian Rogers2c8f6532011-09-02 17:16:34 -07001825} // namespace arm
Carl Shapiro6b6b5f02011-06-21 15:05:09 -07001826} // namespace art