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review.blissroms.org / platform_art / e4cec517faf1c74d6895e0e5b512a6e2f83a0e06 / . / runtime / interpreter / mterp / out / mterp_mips64.S
blob: 7cef823fff789de12a6c8a86739e294cba87d9b9 [file] [log] [blame]
Alexey Frunze00b53b72016-02-02 20:25:45 -0800[diff] [blame]1/*
2 * This file was generated automatically by gen-mterp.py for 'mips64'.
3 *
4 * --> DO NOT EDIT <--
5 */
6
7/* File: mips64/header.S */
8/*
9 * Copyright (C) 2016 The Android Open Source Project
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 */
23
24#include <machine/regdef.h>
25
26/* TODO: add the missing file and use its FP register definitions. */
27/* #include <machine/fpregdef.h> */
28/* FP register definitions */
29#define f0 $f0
30#define f1 $f1
31#define f2 $f2
32#define f3 $f3
33#define f12 $f12
34#define f13 $f13
35
36/*
37 * It looks like the GNU assembler currently does not support the blec and bgtc
38 * idioms, which should translate into bgec and bltc respectively with swapped
39 * left and right register operands.
40 * TODO: remove these macros when the assembler is fixed.
41 */
42.macro blec lreg, rreg, target
43 bgec \rreg, \lreg, \target
44.endm
45.macro bgtc lreg, rreg, target
46 bltc \rreg, \lreg, \target
47.endm
48
49/*
50Mterp and MIPS64 notes:
51
52The following registers have fixed assignments:
53
54 reg nick purpose
55 s0 rPC interpreted program counter, used for fetching instructions
56 s1 rFP interpreted frame pointer, used for accessing locals and args
57 s2 rSELF self (Thread) pointer
58 s3 rINST first 16-bit code unit of current instruction
59 s4 rIBASE interpreted instruction base pointer, used for computed goto
60 s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later).
61*/
62
63/* During bringup, we'll use the shadow frame model instead of rFP */
64/* single-purpose registers, given names for clarity */
65#define rPC s0
66#define rFP s1
67#define rSELF s2
68#define rINST s3
69#define rIBASE s4
70#define rREFS s5
71
72/*
73 * This is a #include, not a %include, because we want the C pre-processor
74 * to expand the macros into assembler assignment statements.
75 */
76#include "asm_support.h"
77
78/*
79 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So,
80 * to access other shadow frame fields, we need to use a backwards offset. Define those here.
81 */
82#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
83#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
84#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
85#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
86#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
87#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
88#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
89#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
90#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET)
91
92/*
93 *
94 * The reference interpreter performs explicit suspect checks, which is somewhat wasteful.
95 * Dalvik's interpreter folded suspend checks into the jump table mechanism, and eventually
96 * mterp should do so as well.
97 */
98#define MTERP_SUSPEND 0
99
100#define MTERP_LOGGING 0
101
102/*
103 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must
104 * be done *before* something throws.
105 *
106 * It's okay to do this more than once.
107 *
108 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
109 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction
110 * offset into the code_items_[] array. For effiency, we will "export" the
111 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
112 * to convert to a dex pc when needed.
113 */
114.macro EXPORT_PC
115 sd rPC, OFF_FP_DEX_PC_PTR(rFP)
116.endm
117
118/*
119 * Refresh handler table.
120 */
121.macro REFRESH_IBASE
122 ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
123.endm
124
125/*
126 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
127 */
128.macro FETCH_INST
129 lhu rINST, 0(rPC)
130.endm
131
132/* Advance rPC by some number of code units. */
133.macro ADVANCE count
134 daddu rPC, rPC, (\count) * 2
135.endm
136
137/*
138 * Fetch the next instruction from the specified offset. Advances rPC
139 * to point to the next instruction.
140 *
141 * This must come AFTER anything that can throw an exception, or the
142 * exception catch may miss. (This also implies that it must come after
143 * EXPORT_PC.)
144 */
145.macro FETCH_ADVANCE_INST count
146 ADVANCE \count
147 FETCH_INST
148.endm
149
150/*
151 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load
152 * rINST ahead of possible exception point. Be sure to manually advance rPC
153 * later.
154 */
155.macro PREFETCH_INST count
156 lhu rINST, ((\count) * 2)(rPC)
157.endm
158
159/*
160 * Put the instruction's opcode field into the specified register.
161 */
162.macro GET_INST_OPCODE reg
163 and \reg, rINST, 255
164.endm
165
166/*
167 * Begin executing the opcode in _reg.
168 */
169.macro GOTO_OPCODE reg
170 .set noat
171 sll AT, \reg, 7
172 daddu AT, rIBASE, AT
173 jic AT, 0
174 .set at
175.endm
176
177/*
178 * Get/set the 32-bit value from a Dalvik register.
179 * Note, GET_VREG does sign extension to 64 bits while
180 * GET_VREG_U does zero extension to 64 bits.
181 * One is useful for arithmetic while the other is
182 * useful for storing the result value as 64-bit.
183 */
184.macro GET_VREG reg, vreg
185 .set noat
186 dlsa AT, \vreg, rFP, 2
187 lw \reg, 0(AT)
188 .set at
189.endm
190.macro GET_VREG_U reg, vreg
191 .set noat
192 dlsa AT, \vreg, rFP, 2
193 lwu \reg, 0(AT)
194 .set at
195.endm
196.macro GET_VREG_FLOAT reg, vreg
197 .set noat
198 dlsa AT, \vreg, rFP, 2
199 lwc1 \reg, 0(AT)
200 .set at
201.endm
202.macro SET_VREG reg, vreg
203 .set noat
204 dlsa AT, \vreg, rFP, 2
205 sw \reg, 0(AT)
206 dlsa AT, \vreg, rREFS, 2
207 sw zero, 0(AT)
208 .set at
209.endm
210.macro SET_VREG_OBJECT reg, vreg
211 .set noat
212 dlsa AT, \vreg, rFP, 2
213 sw \reg, 0(AT)
214 dlsa AT, \vreg, rREFS, 2
215 sw \reg, 0(AT)
216 .set at
217.endm
218.macro SET_VREG_FLOAT reg, vreg
219 .set noat
220 dlsa AT, \vreg, rFP, 2
221 swc1 \reg, 0(AT)
222 dlsa AT, \vreg, rREFS, 2
223 sw zero, 0(AT)
224 .set at
225.endm
226
227/*
228 * Get/set the 64-bit value from a Dalvik register.
229 * Avoid unaligned memory accesses.
230 * Note, SET_VREG_WIDE clobbers the register containing the value being stored.
231 * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number.
232 */
233.macro GET_VREG_WIDE reg, vreg
234 .set noat
235 dlsa AT, \vreg, rFP, 2
236 lw \reg, 0(AT)
237 lw AT, 4(AT)
238 dinsu \reg, AT, 32, 32
239 .set at
240.endm
241.macro GET_VREG_DOUBLE reg, vreg
242 .set noat
243 dlsa AT, \vreg, rFP, 2
244 lwc1 \reg, 0(AT)
245 lw AT, 4(AT)
246 mthc1 AT, \reg
247 .set at
248.endm
249.macro SET_VREG_WIDE reg, vreg
250 .set noat
251 dlsa AT, \vreg, rFP, 2
252 sw \reg, 0(AT)
253 drotr32 \reg, \reg, 0
254 sw \reg, 4(AT)
255 dlsa AT, \vreg, rREFS, 2
256 sw zero, 0(AT)
257 sw zero, 4(AT)
258 .set at
259.endm
260.macro SET_VREG_DOUBLE reg, vreg
261 .set noat
262 dlsa AT, \vreg, rREFS, 2
263 sw zero, 0(AT)
264 sw zero, 4(AT)
265 dlsa AT, \vreg, rFP, 2
266 swc1 \reg, 0(AT)
267 mfhc1 \vreg, \reg
268 sw \vreg, 4(AT)
269 .set at
270.endm
271
272/*
273 * On-stack offsets for spilling/unspilling callee-saved registers
274 * and the frame size.
275 */
276#define STACK_OFFSET_RA 0
277#define STACK_OFFSET_GP 8
278#define STACK_OFFSET_S0 16
279#define STACK_OFFSET_S1 24
280#define STACK_OFFSET_S2 32
281#define STACK_OFFSET_S3 40
282#define STACK_OFFSET_S4 48
283#define STACK_OFFSET_S5 56
284#define STACK_SIZE 64
285
286/* Constants for float/double_to_int/long conversions */
287#define INT_MIN 0x80000000
288#define INT_MIN_AS_FLOAT 0xCF000000
289#define INT_MIN_AS_DOUBLE 0xC1E0000000000000
290#define LONG_MIN 0x8000000000000000
291#define LONG_MIN_AS_FLOAT 0xDF000000
292#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000
293
294/* File: mips64/entry.S */
295/*
296 * Copyright (C) 2016 The Android Open Source Project
297 *
298 * Licensed under the Apache License, Version 2.0 (the "License");
299 * you may not use this file except in compliance with the License.
300 * You may obtain a copy of the License at
301 *
302 * http://www.apache.org/licenses/LICENSE-2.0
303 *
304 * Unless required by applicable law or agreed to in writing, software
305 * distributed under the License is distributed on an "AS IS" BASIS,
306 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
307 * See the License for the specific language governing permissions and
308 * limitations under the License.
309 */
310
311/*
312 * Interpreter entry point.
313 */
314
315 .set reorder
316
317 .text
318 .global ExecuteMterpImpl
319 .type ExecuteMterpImpl, %function
320 .balign 16
321/*
322 * On entry:
323 * a0 Thread* self
324 * a1 code_item
325 * a2 ShadowFrame
326 * a3 JValue* result_register
327 *
328 */
329ExecuteMterpImpl:
330 .cfi_startproc
331 .cpsetup t9, t8, ExecuteMterpImpl
332
333 .cfi_def_cfa sp, 0
334 daddu sp, sp, -STACK_SIZE
335 .cfi_adjust_cfa_offset STACK_SIZE
336
337 sd t8, STACK_OFFSET_GP(sp)
338 .cfi_rel_offset 28, STACK_OFFSET_GP
339 sd ra, STACK_OFFSET_RA(sp)
340 .cfi_rel_offset 31, STACK_OFFSET_RA
341
342 sd s0, STACK_OFFSET_S0(sp)
343 .cfi_rel_offset 16, STACK_OFFSET_S0
344 sd s1, STACK_OFFSET_S1(sp)
345 .cfi_rel_offset 17, STACK_OFFSET_S1
346 sd s2, STACK_OFFSET_S2(sp)
347 .cfi_rel_offset 18, STACK_OFFSET_S2
348 sd s3, STACK_OFFSET_S3(sp)
349 .cfi_rel_offset 19, STACK_OFFSET_S3
350 sd s4, STACK_OFFSET_S4(sp)
351 .cfi_rel_offset 20, STACK_OFFSET_S4
352 sd s5, STACK_OFFSET_S5(sp)
353 .cfi_rel_offset 21, STACK_OFFSET_S5
354
355 /* Remember the return register */
356 sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2)
357
358 /* Remember the code_item */
359 sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2)
360
361 /* set up "named" registers */
362 move rSELF, a0
363 daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET
364 lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
365 dlsa rREFS, v0, rFP, 2
366 daddu rPC, a1, CODEITEM_INSNS_OFFSET
367 lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
368 dlsa rPC, v0, rPC, 1
369 EXPORT_PC
370
371 /* Starting ibase */
372 REFRESH_IBASE
373
374 /* start executing the instruction at rPC */
375 FETCH_INST
376 GET_INST_OPCODE v0
377 GOTO_OPCODE v0
378
379 /* NOTE: no fallthrough */
380
381
382 .global artMterpAsmInstructionStart
383 .type artMterpAsmInstructionStart, %function
384artMterpAsmInstructionStart = .L_op_nop
385 .text
386
387/* ------------------------------ */
388 .balign 128
389.L_op_nop: /* 0x00 */
390/* File: mips64/op_nop.S */
391 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
392 GET_INST_OPCODE v0 # extract opcode from rINST
393 GOTO_OPCODE v0 # jump to next instruction
394
395/* ------------------------------ */
396 .balign 128
397.L_op_move: /* 0x01 */
398/* File: mips64/op_move.S */
399 /* for move, move-object, long-to-int */
400 /* op vA, vB */
401 ext a2, rINST, 8, 4 # a2 <- A
402 ext a3, rINST, 12, 4 # a3 <- B
403 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
404 GET_VREG a0, a3 # a0 <- vB
405 GET_INST_OPCODE v0 # extract opcode from rINST
406 .if 0
407 SET_VREG_OBJECT a0, a2 # vA <- vB
408 .else
409 SET_VREG a0, a2 # vA <- vB
410 .endif
411 GOTO_OPCODE v0 # jump to next instruction
412
413/* ------------------------------ */
414 .balign 128
415.L_op_move_from16: /* 0x02 */
416/* File: mips64/op_move_from16.S */
417 /* for: move/from16, move-object/from16 */
418 /* op vAA, vBBBB */
419 lhu a3, 2(rPC) # a3 <- BBBB
420 srl a2, rINST, 8 # a2 <- AA
421 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
422 GET_VREG a0, a3 # a0 <- vBBBB
423 GET_INST_OPCODE v0 # extract opcode from rINST
424 .if 0
425 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB
426 .else
427 SET_VREG a0, a2 # vAA <- vBBBB
428 .endif
429 GOTO_OPCODE v0 # jump to next instruction
430
431/* ------------------------------ */
432 .balign 128
433.L_op_move_16: /* 0x03 */
434/* File: mips64/op_move_16.S */
435 /* for: move/16, move-object/16 */
436 /* op vAAAA, vBBBB */
437 lhu a3, 4(rPC) # a3 <- BBBB
438 lhu a2, 2(rPC) # a2 <- AAAA
439 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
440 GET_VREG a0, a3 # a0 <- vBBBB
441 GET_INST_OPCODE v0 # extract opcode from rINST
442 .if 0
443 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB
444 .else
445 SET_VREG a0, a2 # vAAAA <- vBBBB
446 .endif
447 GOTO_OPCODE v0 # jump to next instruction
448
449/* ------------------------------ */
450 .balign 128
451.L_op_move_wide: /* 0x04 */
452/* File: mips64/op_move_wide.S */
453 /* move-wide vA, vB */
454 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
455 ext a3, rINST, 12, 4 # a3 <- B
456 ext a2, rINST, 8, 4 # a2 <- A
457 GET_VREG_WIDE a0, a3 # a0 <- vB
458 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
459 GET_INST_OPCODE v0 # extract opcode from rINST
460 SET_VREG_WIDE a0, a2 # vA <- vB
461 GOTO_OPCODE v0 # jump to next instruction
462
463/* ------------------------------ */
464 .balign 128
465.L_op_move_wide_from16: /* 0x05 */
466/* File: mips64/op_move_wide_from16.S */
467 /* move-wide/from16 vAA, vBBBB */
468 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
469 lhu a3, 2(rPC) # a3 <- BBBB
470 srl a2, rINST, 8 # a2 <- AA
471 GET_VREG_WIDE a0, a3 # a0 <- vBBBB
472 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
473 GET_INST_OPCODE v0 # extract opcode from rINST
474 SET_VREG_WIDE a0, a2 # vAA <- vBBBB
475 GOTO_OPCODE v0 # jump to next instruction
476
477/* ------------------------------ */
478 .balign 128
479.L_op_move_wide_16: /* 0x06 */
480/* File: mips64/op_move_wide_16.S */
481 /* move-wide/16 vAAAA, vBBBB */
482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
483 lhu a3, 4(rPC) # a3 <- BBBB
484 lhu a2, 2(rPC) # a2 <- AAAA
485 GET_VREG_WIDE a0, a3 # a0 <- vBBBB
486 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
487 GET_INST_OPCODE v0 # extract opcode from rINST
488 SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB
489 GOTO_OPCODE v0 # jump to next instruction
490
491/* ------------------------------ */
492 .balign 128
493.L_op_move_object: /* 0x07 */
494/* File: mips64/op_move_object.S */
495/* File: mips64/op_move.S */
496 /* for move, move-object, long-to-int */
497 /* op vA, vB */
498 ext a2, rINST, 8, 4 # a2 <- A
499 ext a3, rINST, 12, 4 # a3 <- B
500 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
501 GET_VREG a0, a3 # a0 <- vB
502 GET_INST_OPCODE v0 # extract opcode from rINST
503 .if 1
504 SET_VREG_OBJECT a0, a2 # vA <- vB
505 .else
506 SET_VREG a0, a2 # vA <- vB
507 .endif
508 GOTO_OPCODE v0 # jump to next instruction
509
510
511/* ------------------------------ */
512 .balign 128
513.L_op_move_object_from16: /* 0x08 */
514/* File: mips64/op_move_object_from16.S */
515/* File: mips64/op_move_from16.S */
516 /* for: move/from16, move-object/from16 */
517 /* op vAA, vBBBB */
518 lhu a3, 2(rPC) # a3 <- BBBB
519 srl a2, rINST, 8 # a2 <- AA
520 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
521 GET_VREG a0, a3 # a0 <- vBBBB
522 GET_INST_OPCODE v0 # extract opcode from rINST
523 .if 1
524 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB
525 .else
526 SET_VREG a0, a2 # vAA <- vBBBB
527 .endif
528 GOTO_OPCODE v0 # jump to next instruction
529
530
531/* ------------------------------ */
532 .balign 128
533.L_op_move_object_16: /* 0x09 */
534/* File: mips64/op_move_object_16.S */
535/* File: mips64/op_move_16.S */
536 /* for: move/16, move-object/16 */
537 /* op vAAAA, vBBBB */
538 lhu a3, 4(rPC) # a3 <- BBBB
539 lhu a2, 2(rPC) # a2 <- AAAA
540 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
541 GET_VREG a0, a3 # a0 <- vBBBB
542 GET_INST_OPCODE v0 # extract opcode from rINST
543 .if 1
544 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB
545 .else
546 SET_VREG a0, a2 # vAAAA <- vBBBB
547 .endif
548 GOTO_OPCODE v0 # jump to next instruction
549
550
551/* ------------------------------ */
552 .balign 128
553.L_op_move_result: /* 0x0a */
554/* File: mips64/op_move_result.S */
555 /* for: move-result, move-result-object */
556 /* op vAA */
557 srl a2, rINST, 8 # a2 <- AA
558 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
559 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
560 lw a0, 0(a0) # a0 <- result.i
561 GET_INST_OPCODE v0 # extract opcode from rINST
562 .if 0
563 SET_VREG_OBJECT a0, a2 # vAA <- result
564 .else
565 SET_VREG a0, a2 # vAA <- result
566 .endif
567 GOTO_OPCODE v0 # jump to next instruction
568
569/* ------------------------------ */
570 .balign 128
571.L_op_move_result_wide: /* 0x0b */
572/* File: mips64/op_move_result_wide.S */
573 /* for: move-result-wide */
574 /* op vAA */
575 srl a2, rINST, 8 # a2 <- AA
576 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
577 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
578 ld a0, 0(a0) # a0 <- result.j
579 GET_INST_OPCODE v0 # extract opcode from rINST
580 SET_VREG_WIDE a0, a2 # vAA <- result
581 GOTO_OPCODE v0 # jump to next instruction
582
583/* ------------------------------ */
584 .balign 128
585.L_op_move_result_object: /* 0x0c */
586/* File: mips64/op_move_result_object.S */
587/* File: mips64/op_move_result.S */
588 /* for: move-result, move-result-object */
589 /* op vAA */
590 srl a2, rINST, 8 # a2 <- AA
591 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
592 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
593 lw a0, 0(a0) # a0 <- result.i
594 GET_INST_OPCODE v0 # extract opcode from rINST
595 .if 1
596 SET_VREG_OBJECT a0, a2 # vAA <- result
597 .else
598 SET_VREG a0, a2 # vAA <- result
599 .endif
600 GOTO_OPCODE v0 # jump to next instruction
601
602
603/* ------------------------------ */
604 .balign 128
605.L_op_move_exception: /* 0x0d */
606/* File: mips64/op_move_exception.S */
607 /* move-exception vAA */
608 srl a2, rINST, 8 # a2 <- AA
609 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj
610 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
611 SET_VREG_OBJECT a0, a2 # vAA <- exception obj
612 GET_INST_OPCODE v0 # extract opcode from rINST
613 sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception
614 GOTO_OPCODE v0 # jump to next instruction
615
616/* ------------------------------ */
617 .balign 128
618.L_op_return_void: /* 0x0e */
619/* File: mips64/op_return_void.S */
620 .extern MterpThreadFenceForConstructor
621 .extern MterpSuspendCheck
622 jal MterpThreadFenceForConstructor
623 lw ra, THREAD_FLAGS_OFFSET(rSELF)
624 move a0, rSELF
625 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
626 beqzc ra, 1f
627 jal MterpSuspendCheck # (self)
6281:
629 li a0, 0
630 b MterpReturn
631
632/* ------------------------------ */
633 .balign 128
634.L_op_return: /* 0x0f */
635/* File: mips64/op_return.S */
636 /*
637 * Return a 32-bit value.
638 *
639 * for: return, return-object
640 */
641 /* op vAA */
642 .extern MterpThreadFenceForConstructor
643 .extern MterpSuspendCheck
644 jal MterpThreadFenceForConstructor
645 lw ra, THREAD_FLAGS_OFFSET(rSELF)
646 move a0, rSELF
647 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
648 beqzc ra, 1f
649 jal MterpSuspendCheck # (self)
6501:
651 srl a2, rINST, 8 # a2 <- AA
652 GET_VREG_U a0, a2 # a0 <- vAA
653 b MterpReturn
654
655/* ------------------------------ */
656 .balign 128
657.L_op_return_wide: /* 0x10 */
658/* File: mips64/op_return_wide.S */
659 /*
660 * Return a 64-bit value.
661 */
662 /* return-wide vAA */
663 /* op vAA */
664 .extern MterpThreadFenceForConstructor
665 .extern MterpSuspendCheck
666 jal MterpThreadFenceForConstructor
667 lw ra, THREAD_FLAGS_OFFSET(rSELF)
668 move a0, rSELF
669 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
670 beqzc ra, 1f
671 jal MterpSuspendCheck # (self)
6721:
673 srl a2, rINST, 8 # a2 <- AA
674 GET_VREG_WIDE a0, a2 # a0 <- vAA
675 b MterpReturn
676
677/* ------------------------------ */
678 .balign 128
679.L_op_return_object: /* 0x11 */
680/* File: mips64/op_return_object.S */
681/* File: mips64/op_return.S */
682 /*
683 * Return a 32-bit value.
684 *
685 * for: return, return-object
686 */
687 /* op vAA */
688 .extern MterpThreadFenceForConstructor
689 .extern MterpSuspendCheck
690 jal MterpThreadFenceForConstructor
691 lw ra, THREAD_FLAGS_OFFSET(rSELF)
692 move a0, rSELF
693 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
694 beqzc ra, 1f
695 jal MterpSuspendCheck # (self)
6961:
697 srl a2, rINST, 8 # a2 <- AA
698 GET_VREG_U a0, a2 # a0 <- vAA
699 b MterpReturn
700
701
702/* ------------------------------ */
703 .balign 128
704.L_op_const_4: /* 0x12 */
705/* File: mips64/op_const_4.S */
706 /* const/4 vA, #+B */
707 ext a2, rINST, 8, 4 # a2 <- A
708 seh a0, rINST # sign extend B in rINST
709 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
710 sra a0, a0, 12 # shift B into its final position
711 GET_INST_OPCODE v0 # extract opcode from rINST
712 SET_VREG a0, a2 # vA <- +B
713 GOTO_OPCODE v0 # jump to next instruction
714
715/* ------------------------------ */
716 .balign 128
717.L_op_const_16: /* 0x13 */
718/* File: mips64/op_const_16.S */
719 /* const/16 vAA, #+BBBB */
720 srl a2, rINST, 8 # a2 <- AA
721 lh a0, 2(rPC) # a0 <- sign-extended BBBB
722 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
723 GET_INST_OPCODE v0 # extract opcode from rINST
724 SET_VREG a0, a2 # vAA <- +BBBB
725 GOTO_OPCODE v0 # jump to next instruction
726
727/* ------------------------------ */
728 .balign 128
729.L_op_const: /* 0x14 */
730/* File: mips64/op_const.S */
731 /* const vAA, #+BBBBbbbb */
732 srl a2, rINST, 8 # a2 <- AA
733 lh a0, 2(rPC) # a0 <- bbbb (low)
734 lh a1, 4(rPC) # a1 <- BBBB (high)
735 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
736 ins a0, a1, 16, 16 # a0 = BBBBbbbb
737 GET_INST_OPCODE v0 # extract opcode from rINST
738 SET_VREG a0, a2 # vAA <- +BBBBbbbb
739 GOTO_OPCODE v0 # jump to next instruction
740
741/* ------------------------------ */
742 .balign 128
743.L_op_const_high16: /* 0x15 */
744/* File: mips64/op_const_high16.S */
745 /* const/high16 vAA, #+BBBB0000 */
746 srl a2, rINST, 8 # a2 <- AA
747 lh a0, 2(rPC) # a0 <- BBBB
748 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
749 sll a0, a0, 16 # a0 <- BBBB0000
750 GET_INST_OPCODE v0 # extract opcode from rINST
751 SET_VREG a0, a2 # vAA <- +BBBB0000
752 GOTO_OPCODE v0 # jump to next instruction
753
754/* ------------------------------ */
755 .balign 128
756.L_op_const_wide_16: /* 0x16 */
757/* File: mips64/op_const_wide_16.S */
758 /* const-wide/16 vAA, #+BBBB */
759 srl a2, rINST, 8 # a2 <- AA
760 lh a0, 2(rPC) # a0 <- sign-extended BBBB
761 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
762 GET_INST_OPCODE v0 # extract opcode from rINST
763 SET_VREG_WIDE a0, a2 # vAA <- +BBBB
764 GOTO_OPCODE v0 # jump to next instruction
765
766/* ------------------------------ */
767 .balign 128
768.L_op_const_wide_32: /* 0x17 */
769/* File: mips64/op_const_wide_32.S */
770 /* const-wide/32 vAA, #+BBBBbbbb */
771 srl a2, rINST, 8 # a2 <- AA
772 lh a0, 2(rPC) # a0 <- bbbb (low)
773 lh a1, 4(rPC) # a1 <- BBBB (high)
774 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
775 ins a0, a1, 16, 16 # a0 = BBBBbbbb
776 GET_INST_OPCODE v0 # extract opcode from rINST
777 SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb
778 GOTO_OPCODE v0 # jump to next instruction
779
780/* ------------------------------ */
781 .balign 128
782.L_op_const_wide: /* 0x18 */
783/* File: mips64/op_const_wide.S */
784 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
785 srl a4, rINST, 8 # a4 <- AA
786 lh a0, 2(rPC) # a0 <- bbbb (low)
787 lh a1, 4(rPC) # a1 <- BBBB (low middle)
788 lh a2, 6(rPC) # a2 <- hhhh (high middle)
789 lh a3, 8(rPC) # a3 <- HHHH (high)
790 FETCH_ADVANCE_INST 5 # advance rPC, load rINST
791 ins a0, a1, 16, 16 # a0 = BBBBbbbb
792 ins a2, a3, 16, 16 # a2 = HHHHhhhh
793 dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb
794 GET_INST_OPCODE v0 # extract opcode from rINST
795 SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb
796 GOTO_OPCODE v0 # jump to next instruction
797
798/* ------------------------------ */
799 .balign 128
800.L_op_const_wide_high16: /* 0x19 */
801/* File: mips64/op_const_wide_high16.S */
802 /* const-wide/high16 vAA, #+BBBB000000000000 */
803 srl a2, rINST, 8 # a2 <- AA
804 lh a0, 2(rPC) # a0 <- BBBB
805 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
806 dsll32 a0, a0, 16 # a0 <- BBBB000000000000
807 GET_INST_OPCODE v0 # extract opcode from rINST
808 SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000
809 GOTO_OPCODE v0 # jump to next instruction
810
811/* ------------------------------ */
812 .balign 128
813.L_op_const_string: /* 0x1a */
814/* File: mips64/op_const_string.S */
815 /* const/string vAA, String//BBBB */
816 .extern MterpConstString
817 EXPORT_PC
818 lhu a0, 2(rPC) # a0 <- BBBB
819 srl a1, rINST, 8 # a1 <- AA
820 daddu a2, rFP, OFF_FP_SHADOWFRAME
821 move a3, rSELF
822 jal MterpConstString # (index, tgt_reg, shadow_frame, self)
823 PREFETCH_INST 2 # load rINST
824 bnez v0, MterpPossibleException # let reference interpreter deal with it.
825 ADVANCE 2 # advance rPC
826 GET_INST_OPCODE v0 # extract opcode from rINST
827 GOTO_OPCODE v0 # jump to next instruction
828
829/* ------------------------------ */
830 .balign 128
831.L_op_const_string_jumbo: /* 0x1b */
832/* File: mips64/op_const_string_jumbo.S */
833 /* const/string vAA, String//BBBBBBBB */
834 .extern MterpConstString
835 EXPORT_PC
836 lh a0, 2(rPC) # a0 <- bbbb (low)
837 lh a4, 4(rPC) # a4 <- BBBB (high)
838 srl a1, rINST, 8 # a1 <- AA
839 ins a0, a4, 16, 16 # a0 <- BBBBbbbb
840 daddu a2, rFP, OFF_FP_SHADOWFRAME
841 move a3, rSELF
842 jal MterpConstString # (index, tgt_reg, shadow_frame, self)
843 PREFETCH_INST 3 # load rINST
844 bnez v0, MterpPossibleException # let reference interpreter deal with it.
845 ADVANCE 3 # advance rPC
846 GET_INST_OPCODE v0 # extract opcode from rINST
847 GOTO_OPCODE v0 # jump to next instruction
848
849/* ------------------------------ */
850 .balign 128
851.L_op_const_class: /* 0x1c */
852/* File: mips64/op_const_class.S */
853 /* const/class vAA, Class//BBBB */
854 .extern MterpConstClass
855 EXPORT_PC
856 lhu a0, 2(rPC) # a0 <- BBBB
857 srl a1, rINST, 8 # a1 <- AA
858 daddu a2, rFP, OFF_FP_SHADOWFRAME
859 move a3, rSELF
860 jal MterpConstClass # (index, tgt_reg, shadow_frame, self)
861 PREFETCH_INST 2 # load rINST
862 bnez v0, MterpPossibleException # let reference interpreter deal with it.
863 ADVANCE 2 # advance rPC
864 GET_INST_OPCODE v0 # extract opcode from rINST
865 GOTO_OPCODE v0 # jump to next instruction
866
867/* ------------------------------ */
868 .balign 128
869.L_op_monitor_enter: /* 0x1d */
870/* File: mips64/op_monitor_enter.S */
871 /*
872 * Synchronize on an object.
873 */
874 /* monitor-enter vAA */
875 .extern artLockObjectFromCode
876 EXPORT_PC
877 srl a2, rINST, 8 # a2 <- AA
878 GET_VREG_U a0, a2 # a0 <- vAA (object)
879 move a1, rSELF # a1 <- self
880 jal artLockObjectFromCode
881 bnezc v0, MterpException
882 FETCH_ADVANCE_INST 1
883 GET_INST_OPCODE v0 # extract opcode from rINST
884 GOTO_OPCODE v0 # jump to next instruction
885
886/* ------------------------------ */
887 .balign 128
888.L_op_monitor_exit: /* 0x1e */
889/* File: mips64/op_monitor_exit.S */
890 /*
891 * Unlock an object.
892 *
893 * Exceptions that occur when unlocking a monitor need to appear as
894 * if they happened at the following instruction. See the Dalvik
895 * instruction spec.
896 */
897 /* monitor-exit vAA */
898 .extern artUnlockObjectFromCode
899 EXPORT_PC
900 srl a2, rINST, 8 # a2 <- AA
901 GET_VREG_U a0, a2 # a0 <- vAA (object)
902 move a1, rSELF # a1 <- self
903 jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj)
904 bnezc v0, MterpException
905 FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST
906 GET_INST_OPCODE v0 # extract opcode from rINST
907 GOTO_OPCODE v0 # jump to next instruction
908
909/* ------------------------------ */
910 .balign 128
911.L_op_check_cast: /* 0x1f */
912/* File: mips64/op_check_cast.S */
913 /*
914 * Check to see if a cast from one class to another is allowed.
915 */
916 /* check-cast vAA, class//BBBB */
917 .extern MterpCheckCast
918 EXPORT_PC
919 lhu a0, 2(rPC) # a0 <- BBBB
920 srl a1, rINST, 8 # a1 <- AA
921 dlsa a1, a1, rFP, 2 # a1 <- &object
922 ld a2, OFF_FP_METHOD(rFP) # a2 <- method
923 move a3, rSELF # a3 <- self
924 jal MterpCheckCast # (index, &obj, method, self)
925 PREFETCH_INST 2
926 bnez v0, MterpPossibleException
927 ADVANCE 2
928 GET_INST_OPCODE v0 # extract opcode from rINST
929 GOTO_OPCODE v0 # jump to next instruction
930
931/* ------------------------------ */
932 .balign 128
933.L_op_instance_of: /* 0x20 */
934/* File: mips64/op_instance_of.S */
935 /*
936 * Check to see if an object reference is an instance of a class.
937 *
938 * Most common situation is a non-null object, being compared against
939 * an already-resolved class.
940 */
941 /* instance-of vA, vB, class//CCCC */
942 .extern MterpInstanceOf
943 EXPORT_PC
944 lhu a0, 2(rPC) # a0 <- CCCC
945 srl a1, rINST, 12 # a1 <- B
946 dlsa a1, a1, rFP, 2 # a1 <- &object
947 ld a2, OFF_FP_METHOD(rFP) # a2 <- method
948 move a3, rSELF # a3 <- self
949 jal MterpInstanceOf # (index, &obj, method, self)
950 ld a1, THREAD_EXCEPTION_OFFSET(rSELF)
951 ext a2, rINST, 8, 4 # a2 <- A
952 PREFETCH_INST 2
953 bnez a1, MterpException
954 ADVANCE 2 # advance rPC
955 SET_VREG v0, a2 # vA <- v0
956 GET_INST_OPCODE v0 # extract opcode from rINST
957 GOTO_OPCODE v0 # jump to next instruction
958
959/* ------------------------------ */
960 .balign 128
961.L_op_array_length: /* 0x21 */
962/* File: mips64/op_array_length.S */
963 /*
964 * Return the length of an array.
965 */
966 srl a1, rINST, 12 # a1 <- B
967 GET_VREG_U a0, a1 # a0 <- vB (object ref)
968 ext a2, rINST, 8, 4 # a2 <- A
969 beqz a0, common_errNullObject # yup, fail
970 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
971 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length
972 GET_INST_OPCODE v0 # extract opcode from rINST
973 SET_VREG a3, a2 # vB <- length
974 GOTO_OPCODE v0 # jump to next instruction
975
976/* ------------------------------ */
977 .balign 128
978.L_op_new_instance: /* 0x22 */
979/* File: mips64/op_new_instance.S */
980 /*
981 * Create a new instance of a class.
982 */
983 /* new-instance vAA, class//BBBB */
984 .extern MterpNewInstance
985 EXPORT_PC
986 daddu a0, rFP, OFF_FP_SHADOWFRAME
987 move a1, rSELF
988 move a2, rINST
989 jal MterpNewInstance # (shadow_frame, self, inst_data)
990 beqzc v0, MterpPossibleException
991 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
992 GET_INST_OPCODE v0 # extract opcode from rINST
993 GOTO_OPCODE v0 # jump to next instruction
994
995/* ------------------------------ */
996 .balign 128
997.L_op_new_array: /* 0x23 */
998/* File: mips64/op_new_array.S */
999 /*
1000 * Allocate an array of objects, specified with the array class
1001 * and a count.
1002 *
1003 * The verifier guarantees that this is an array class, so we don't
1004 * check for it here.
1005 */
1006 /* new-array vA, vB, class//CCCC */
1007 .extern MterpNewArray
1008 EXPORT_PC
1009 daddu a0, rFP, OFF_FP_SHADOWFRAME
1010 move a1, rPC
1011 move a2, rINST
1012 move a3, rSELF
1013 jal MterpNewArray
1014 beqzc v0, MterpPossibleException
1015 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1016 GET_INST_OPCODE v0 # extract opcode from rINST
1017 GOTO_OPCODE v0 # jump to next instruction
1018
1019/* ------------------------------ */
1020 .balign 128
1021.L_op_filled_new_array: /* 0x24 */
1022/* File: mips64/op_filled_new_array.S */
1023 /*
1024 * Create a new array with elements filled from registers.
1025 *
1026 * for: filled-new-array, filled-new-array/range
1027 */
1028 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */
1029 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */
1030 .extern MterpFilledNewArray
1031 EXPORT_PC
1032 daddu a0, rFP, OFF_FP_SHADOWFRAME
1033 move a1, rPC
1034 move a2, rSELF
1035 jal MterpFilledNewArray
1036 beqzc v0, MterpPossibleException
1037 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
1038 GET_INST_OPCODE v0 # extract opcode from rINST
1039 GOTO_OPCODE v0 # jump to next instruction
1040
1041/* ------------------------------ */
1042 .balign 128
1043.L_op_filled_new_array_range: /* 0x25 */
1044/* File: mips64/op_filled_new_array_range.S */
1045/* File: mips64/op_filled_new_array.S */
1046 /*
1047 * Create a new array with elements filled from registers.
1048 *
1049 * for: filled-new-array, filled-new-array/range
1050 */
1051 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */
1052 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */
1053 .extern MterpFilledNewArrayRange
1054 EXPORT_PC
1055 daddu a0, rFP, OFF_FP_SHADOWFRAME
1056 move a1, rPC
1057 move a2, rSELF
1058 jal MterpFilledNewArrayRange
1059 beqzc v0, MterpPossibleException
1060 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
1061 GET_INST_OPCODE v0 # extract opcode from rINST
1062 GOTO_OPCODE v0 # jump to next instruction
1063
1064
1065/* ------------------------------ */
1066 .balign 128
1067.L_op_fill_array_data: /* 0x26 */
1068/* File: mips64/op_fill_array_data.S */
1069 /* fill-array-data vAA, +BBBBBBBB */
1070 .extern MterpFillArrayData
1071 EXPORT_PC
1072 lh a1, 2(rPC) # a1 <- bbbb (lo)
1073 lh a0, 4(rPC) # a0 <- BBBB (hi)
1074 srl a3, rINST, 8 # a3 <- AA
1075 ins a1, a0, 16, 16 # a1 <- BBBBbbbb
1076 GET_VREG_U a0, a3 # a0 <- vAA (array object)
1077 dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.)
1078 jal MterpFillArrayData # (obj, payload)
1079 beqzc v0, MterpPossibleException # exception?
1080 FETCH_ADVANCE_INST 3 # advance rPC, load rINST
1081 GET_INST_OPCODE v0 # extract opcode from rINST
1082 GOTO_OPCODE v0 # jump to next instruction
1083
1084/* ------------------------------ */
1085 .balign 128
1086.L_op_throw: /* 0x27 */
1087/* File: mips64/op_throw.S */
1088 /*
1089 * Throw an exception object in the current thread.
1090 */
1091 /* throw vAA */
1092 EXPORT_PC
1093 srl a2, rINST, 8 # a2 <- AA
1094 GET_VREG_U a0, a2 # a0 <- vAA (exception object)
1095 beqzc a0, common_errNullObject
1096 sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj
1097 b MterpException
1098
1099/* ------------------------------ */
1100 .balign 128
1101.L_op_goto: /* 0x28 */
1102/* File: mips64/op_goto.S */
1103 /*
1104 * Unconditional branch, 8-bit offset.
1105 *
1106 * The branch distance is a signed code-unit offset, which we need to
1107 * double to get a byte offset.
1108 */
1109 /* goto +AA */
1110 srl a0, rINST, 8
1111 seb a0, a0 # a0 <- sign-extended AA
1112 dlsa rPC, a0, rPC, 1 # rPC <- rPC + AA * 2
1113 FETCH_INST # load rINST
1114
1115#if MTERP_SUSPEND
1116 bgez a0, 1f # AA * 2 >= 0 => no suspend check
1117 REFRESH_IBASE
11181:
1119#else
1120 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1121 bltz a0, MterpCheckSuspendAndContinue
1122#endif
1123
1124 GET_INST_OPCODE v0 # extract opcode from rINST
1125 GOTO_OPCODE v0 # jump to next instruction
1126
1127/* ------------------------------ */
1128 .balign 128
1129.L_op_goto_16: /* 0x29 */
1130/* File: mips64/op_goto_16.S */
1131 /*
1132 * Unconditional branch, 16-bit offset.
1133 *
1134 * The branch distance is a signed code-unit offset, which we need to
1135 * double to get a byte offset.
1136 */
1137 /* goto/16 +AAAA */
1138 lh a0, 2(rPC) # a0 <- sign-extended AAAA
1139 dlsa rPC, a0, rPC, 1 # rPC <- rPC + AAAA * 2
1140 FETCH_INST # load rINST
1141
1142#if MTERP_SUSPEND
1143 bgez a0, 1f # AA * 2 >= 0 => no suspend check
1144 REFRESH_IBASE
11451:
1146#else
1147 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1148 bltz a0, MterpCheckSuspendAndContinue
1149#endif
1150
1151 GET_INST_OPCODE v0 # extract opcode from rINST
1152 GOTO_OPCODE v0 # jump to next instruction
1153
1154/* ------------------------------ */
1155 .balign 128
1156.L_op_goto_32: /* 0x2a */
1157/* File: mips64/op_goto_32.S */
1158 /*
1159 * Unconditional branch, 32-bit offset.
1160 *
1161 * The branch distance is a signed code-unit offset, which we need to
1162 * double to get a byte offset.
1163 *
1164 * Unlike most opcodes, this one is allowed to branch to itself, so
1165 * our "backward branch" test must be "<=0" instead of "<0".
1166 */
1167 /* goto/32 +AAAAAAAA */
1168 lh a0, 2(rPC) # a0 <- aaaa (low)
1169 lh a1, 4(rPC) # a1 <- AAAA (high)
1170 ins a0, a1, 16, 16 # a0 = sign-extended AAAAaaaa
1171 dlsa rPC, a0, rPC, 1 # rPC <- rPC + AAAAAAAA * 2
1172 FETCH_INST # load rINST
1173
1174#if MTERP_SUSPEND
1175 bgtz a0, 1f # AA * 2 > 0 => no suspend check
1176 REFRESH_IBASE
11771:
1178#else
1179 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1180 blez a0, MterpCheckSuspendAndContinue
1181#endif
1182
1183 GET_INST_OPCODE v0 # extract opcode from rINST
1184 GOTO_OPCODE v0 # jump to next instruction
1185
1186/* ------------------------------ */
1187 .balign 128
1188.L_op_packed_switch: /* 0x2b */
1189/* File: mips64/op_packed_switch.S */
1190 /*
1191 * Handle a packed-switch or sparse-switch instruction. In both cases
1192 * we decode it and hand it off to a helper function.
1193 *
1194 * We don't really expect backward branches in a switch statement, but
1195 * they're perfectly legal, so we check for them here.
1196 *
1197 * for: packed-switch, sparse-switch
1198 */
1199 /* op vAA, +BBBBBBBB */
1200 .extern MterpDoPackedSwitch
1201 lh a0, 2(rPC) # a0 <- bbbb (lo)
1202 lh a1, 4(rPC) # a1 <- BBBB (hi)
1203 srl a3, rINST, 8 # a3 <- AA
1204 ins a0, a1, 16, 16 # a0 <- BBBBbbbb
1205 GET_VREG a1, a3 # a1 <- vAA
1206 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2
1207 jal MterpDoPackedSwitch # v0 <- code-unit branch offset
1208 dlsa rPC, v0, rPC, 1 # rPC <- rPC + offset * 2
1209 FETCH_INST # load rINST
1210#if MTERP_SUSPEND
1211 bgtz v0, 1f # offset * 2 > 0 => no suspend check
1212 REFRESH_IBASE
12131:
1214#else
1215 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1216 blez v0, MterpCheckSuspendAndContinue
1217#endif
1218 GET_INST_OPCODE v0 # extract opcode from rINST
1219 GOTO_OPCODE v0 # jump to next instruction
1220
1221/* ------------------------------ */
1222 .balign 128
1223.L_op_sparse_switch: /* 0x2c */
1224/* File: mips64/op_sparse_switch.S */
1225/* File: mips64/op_packed_switch.S */
1226 /*
1227 * Handle a packed-switch or sparse-switch instruction. In both cases
1228 * we decode it and hand it off to a helper function.
1229 *
1230 * We don't really expect backward branches in a switch statement, but
1231 * they're perfectly legal, so we check for them here.
1232 *
1233 * for: packed-switch, sparse-switch
1234 */
1235 /* op vAA, +BBBBBBBB */
1236 .extern MterpDoSparseSwitch
1237 lh a0, 2(rPC) # a0 <- bbbb (lo)
1238 lh a1, 4(rPC) # a1 <- BBBB (hi)
1239 srl a3, rINST, 8 # a3 <- AA
1240 ins a0, a1, 16, 16 # a0 <- BBBBbbbb
1241 GET_VREG a1, a3 # a1 <- vAA
1242 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2
1243 jal MterpDoSparseSwitch # v0 <- code-unit branch offset
1244 dlsa rPC, v0, rPC, 1 # rPC <- rPC + offset * 2
1245 FETCH_INST # load rINST
1246#if MTERP_SUSPEND
1247 bgtz v0, 1f # offset * 2 > 0 => no suspend check
1248 REFRESH_IBASE
12491:
1250#else
1251 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1252 blez v0, MterpCheckSuspendAndContinue
1253#endif
1254 GET_INST_OPCODE v0 # extract opcode from rINST
1255 GOTO_OPCODE v0 # jump to next instruction
1256
1257
1258/* ------------------------------ */
1259 .balign 128
1260.L_op_cmpl_float: /* 0x2d */
1261/* File: mips64/op_cmpl_float.S */
1262/* File: mips64/fcmp.S */
1263 /*
1264 * Compare two floating-point values. Puts 0, 1, or -1 into the
1265 * destination register based on the results of the comparison.
1266 *
1267 * For: cmpl-float, cmpg-float
1268 */
1269 /* op vAA, vBB, vCC */
1270 srl a4, rINST, 8 # a4 <- AA
1271 lbu a2, 2(rPC) # a2 <- BB
1272 lbu a3, 3(rPC) # a3 <- CC
1273 GET_VREG_FLOAT f0, a2 # f0 <- vBB
1274 GET_VREG_FLOAT f1, a3 # f1 <- vCC
1275 cmp.eq.s f2, f0, f1
1276 li a0, 0
1277 bc1nez f2, 1f # done if vBB == vCC (ordered)
1278 .if 0
1279 cmp.lt.s f2, f0, f1
1280 li a0, -1
1281 bc1nez f2, 1f # done if vBB < vCC (ordered)
1282 li a0, 1 # vBB > vCC or unordered
1283 .else
1284 cmp.lt.s f2, f1, f0
1285 li a0, 1
1286 bc1nez f2, 1f # done if vBB > vCC (ordered)
1287 li a0, -1 # vBB < vCC or unordered
1288 .endif
12891:
1290 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1291 GET_INST_OPCODE v0 # extract opcode from rINST
1292 SET_VREG a0, a4 # vAA <- a0
1293 GOTO_OPCODE v0 # jump to next instruction
1294
1295
1296/* ------------------------------ */
1297 .balign 128
1298.L_op_cmpg_float: /* 0x2e */
1299/* File: mips64/op_cmpg_float.S */
1300/* File: mips64/fcmp.S */
1301 /*
1302 * Compare two floating-point values. Puts 0, 1, or -1 into the
1303 * destination register based on the results of the comparison.
1304 *
1305 * For: cmpl-float, cmpg-float
1306 */
1307 /* op vAA, vBB, vCC */
1308 srl a4, rINST, 8 # a4 <- AA
1309 lbu a2, 2(rPC) # a2 <- BB
1310 lbu a3, 3(rPC) # a3 <- CC
1311 GET_VREG_FLOAT f0, a2 # f0 <- vBB
1312 GET_VREG_FLOAT f1, a3 # f1 <- vCC
1313 cmp.eq.s f2, f0, f1
1314 li a0, 0
1315 bc1nez f2, 1f # done if vBB == vCC (ordered)
1316 .if 1
1317 cmp.lt.s f2, f0, f1
1318 li a0, -1
1319 bc1nez f2, 1f # done if vBB < vCC (ordered)
1320 li a0, 1 # vBB > vCC or unordered
1321 .else
1322 cmp.lt.s f2, f1, f0
1323 li a0, 1
1324 bc1nez f2, 1f # done if vBB > vCC (ordered)
1325 li a0, -1 # vBB < vCC or unordered
1326 .endif
13271:
1328 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1329 GET_INST_OPCODE v0 # extract opcode from rINST
1330 SET_VREG a0, a4 # vAA <- a0
1331 GOTO_OPCODE v0 # jump to next instruction
1332
1333
1334/* ------------------------------ */
1335 .balign 128
1336.L_op_cmpl_double: /* 0x2f */
1337/* File: mips64/op_cmpl_double.S */
1338/* File: mips64/fcmpWide.S */
1339 /*
1340 * Compare two floating-point values. Puts 0, 1, or -1 into the
1341 * destination register based on the results of the comparison.
1342 *
1343 * For: cmpl-double, cmpg-double
1344 */
1345 /* op vAA, vBB, vCC */
1346 srl a4, rINST, 8 # a4 <- AA
1347 lbu a2, 2(rPC) # a2 <- BB
1348 lbu a3, 3(rPC) # a3 <- CC
1349 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
1350 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
1351 cmp.eq.d f2, f0, f1
1352 li a0, 0
1353 bc1nez f2, 1f # done if vBB == vCC (ordered)
1354 .if 0
1355 cmp.lt.d f2, f0, f1
1356 li a0, -1
1357 bc1nez f2, 1f # done if vBB < vCC (ordered)
1358 li a0, 1 # vBB > vCC or unordered
1359 .else
1360 cmp.lt.d f2, f1, f0
1361 li a0, 1
1362 bc1nez f2, 1f # done if vBB > vCC (ordered)
1363 li a0, -1 # vBB < vCC or unordered
1364 .endif
13651:
1366 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1367 GET_INST_OPCODE v0 # extract opcode from rINST
1368 SET_VREG a0, a4 # vAA <- a0
1369 GOTO_OPCODE v0 # jump to next instruction
1370
1371
1372/* ------------------------------ */
1373 .balign 128
1374.L_op_cmpg_double: /* 0x30 */
1375/* File: mips64/op_cmpg_double.S */
1376/* File: mips64/fcmpWide.S */
1377 /*
1378 * Compare two floating-point values. Puts 0, 1, or -1 into the
1379 * destination register based on the results of the comparison.
1380 *
1381 * For: cmpl-double, cmpg-double
1382 */
1383 /* op vAA, vBB, vCC */
1384 srl a4, rINST, 8 # a4 <- AA
1385 lbu a2, 2(rPC) # a2 <- BB
1386 lbu a3, 3(rPC) # a3 <- CC
1387 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
1388 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
1389 cmp.eq.d f2, f0, f1
1390 li a0, 0
1391 bc1nez f2, 1f # done if vBB == vCC (ordered)
1392 .if 1
1393 cmp.lt.d f2, f0, f1
1394 li a0, -1
1395 bc1nez f2, 1f # done if vBB < vCC (ordered)
1396 li a0, 1 # vBB > vCC or unordered
1397 .else
1398 cmp.lt.d f2, f1, f0
1399 li a0, 1
1400 bc1nez f2, 1f # done if vBB > vCC (ordered)
1401 li a0, -1 # vBB < vCC or unordered
1402 .endif
14031:
1404 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1405 GET_INST_OPCODE v0 # extract opcode from rINST
1406 SET_VREG a0, a4 # vAA <- a0
1407 GOTO_OPCODE v0 # jump to next instruction
1408
1409
1410/* ------------------------------ */
1411 .balign 128
1412.L_op_cmp_long: /* 0x31 */
1413/* File: mips64/op_cmp_long.S */
1414 /* cmp-long vAA, vBB, vCC */
1415 lbu a2, 2(rPC) # a2 <- BB
1416 lbu a3, 3(rPC) # a3 <- CC
1417 srl a4, rINST, 8 # a4 <- AA
1418 GET_VREG_WIDE a0, a2 # a0 <- vBB
1419 GET_VREG_WIDE a1, a3 # a1 <- vCC
1420 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1421 slt a2, a0, a1
1422 slt a0, a1, a0
1423 subu a0, a0, a2
1424 GET_INST_OPCODE v0 # extract opcode from rINST
1425 SET_VREG a0, a4 # vAA <- result
1426 GOTO_OPCODE v0 # jump to next instruction
1427
1428/* ------------------------------ */
1429 .balign 128
1430.L_op_if_eq: /* 0x32 */
1431/* File: mips64/op_if_eq.S */
1432/* File: mips64/bincmp.S */
1433 /*
1434 * Generic two-operand compare-and-branch operation. Provide a "condition"
1435 * fragment that specifies the comparison to perform, e.g. for
1436 * "if-le" you would use "le".
1437 *
1438 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1439 */
1440 /* if-cmp vA, vB, +CCCC */
1441 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1442 ext a2, rINST, 8, 4 # a2 <- A
1443 ext a3, rINST, 12, 4 # a3 <- B
1444 GET_VREG a0, a2 # a0 <- vA
1445 GET_VREG a1, a3 # a1 <- vB
1446
1447 beqc a0, a1, 1f
1448 li a4, 2 # offset if branch not taken
14491:
1450
1451 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1452 FETCH_INST # load rINST
1453
1454#if MTERP_SUSPEND
1455 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1456 REFRESH_IBASE
14572:
1458#else
1459 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1460 bltz a4, MterpCheckSuspendAndContinue
1461#endif
1462
1463 GET_INST_OPCODE v0 # extract opcode from rINST
1464 GOTO_OPCODE v0 # jump to next instruction
1465
1466
1467/* ------------------------------ */
1468 .balign 128
1469.L_op_if_ne: /* 0x33 */
1470/* File: mips64/op_if_ne.S */
1471/* File: mips64/bincmp.S */
1472 /*
1473 * Generic two-operand compare-and-branch operation. Provide a "condition"
1474 * fragment that specifies the comparison to perform, e.g. for
1475 * "if-le" you would use "le".
1476 *
1477 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1478 */
1479 /* if-cmp vA, vB, +CCCC */
1480 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1481 ext a2, rINST, 8, 4 # a2 <- A
1482 ext a3, rINST, 12, 4 # a3 <- B
1483 GET_VREG a0, a2 # a0 <- vA
1484 GET_VREG a1, a3 # a1 <- vB
1485
1486 bnec a0, a1, 1f
1487 li a4, 2 # offset if branch not taken
14881:
1489
1490 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1491 FETCH_INST # load rINST
1492
1493#if MTERP_SUSPEND
1494 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1495 REFRESH_IBASE
14962:
1497#else
1498 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1499 bltz a4, MterpCheckSuspendAndContinue
1500#endif
1501
1502 GET_INST_OPCODE v0 # extract opcode from rINST
1503 GOTO_OPCODE v0 # jump to next instruction
1504
1505
1506/* ------------------------------ */
1507 .balign 128
1508.L_op_if_lt: /* 0x34 */
1509/* File: mips64/op_if_lt.S */
1510/* File: mips64/bincmp.S */
1511 /*
1512 * Generic two-operand compare-and-branch operation. Provide a "condition"
1513 * fragment that specifies the comparison to perform, e.g. for
1514 * "if-le" you would use "le".
1515 *
1516 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1517 */
1518 /* if-cmp vA, vB, +CCCC */
1519 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1520 ext a2, rINST, 8, 4 # a2 <- A
1521 ext a3, rINST, 12, 4 # a3 <- B
1522 GET_VREG a0, a2 # a0 <- vA
1523 GET_VREG a1, a3 # a1 <- vB
1524
1525 bltc a0, a1, 1f
1526 li a4, 2 # offset if branch not taken
15271:
1528
1529 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1530 FETCH_INST # load rINST
1531
1532#if MTERP_SUSPEND
1533 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1534 REFRESH_IBASE
15352:
1536#else
1537 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1538 bltz a4, MterpCheckSuspendAndContinue
1539#endif
1540
1541 GET_INST_OPCODE v0 # extract opcode from rINST
1542 GOTO_OPCODE v0 # jump to next instruction
1543
1544
1545/* ------------------------------ */
1546 .balign 128
1547.L_op_if_ge: /* 0x35 */
1548/* File: mips64/op_if_ge.S */
1549/* File: mips64/bincmp.S */
1550 /*
1551 * Generic two-operand compare-and-branch operation. Provide a "condition"
1552 * fragment that specifies the comparison to perform, e.g. for
1553 * "if-le" you would use "le".
1554 *
1555 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1556 */
1557 /* if-cmp vA, vB, +CCCC */
1558 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1559 ext a2, rINST, 8, 4 # a2 <- A
1560 ext a3, rINST, 12, 4 # a3 <- B
1561 GET_VREG a0, a2 # a0 <- vA
1562 GET_VREG a1, a3 # a1 <- vB
1563
1564 bgec a0, a1, 1f
1565 li a4, 2 # offset if branch not taken
15661:
1567
1568 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1569 FETCH_INST # load rINST
1570
1571#if MTERP_SUSPEND
1572 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1573 REFRESH_IBASE
15742:
1575#else
1576 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1577 bltz a4, MterpCheckSuspendAndContinue
1578#endif
1579
1580 GET_INST_OPCODE v0 # extract opcode from rINST
1581 GOTO_OPCODE v0 # jump to next instruction
1582
1583
1584/* ------------------------------ */
1585 .balign 128
1586.L_op_if_gt: /* 0x36 */
1587/* File: mips64/op_if_gt.S */
1588/* File: mips64/bincmp.S */
1589 /*
1590 * Generic two-operand compare-and-branch operation. Provide a "condition"
1591 * fragment that specifies the comparison to perform, e.g. for
1592 * "if-le" you would use "le".
1593 *
1594 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1595 */
1596 /* if-cmp vA, vB, +CCCC */
1597 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1598 ext a2, rINST, 8, 4 # a2 <- A
1599 ext a3, rINST, 12, 4 # a3 <- B
1600 GET_VREG a0, a2 # a0 <- vA
1601 GET_VREG a1, a3 # a1 <- vB
1602
1603 bgtc a0, a1, 1f
1604 li a4, 2 # offset if branch not taken
16051:
1606
1607 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1608 FETCH_INST # load rINST
1609
1610#if MTERP_SUSPEND
1611 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1612 REFRESH_IBASE
16132:
1614#else
1615 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1616 bltz a4, MterpCheckSuspendAndContinue
1617#endif
1618
1619 GET_INST_OPCODE v0 # extract opcode from rINST
1620 GOTO_OPCODE v0 # jump to next instruction
1621
1622
1623/* ------------------------------ */
1624 .balign 128
1625.L_op_if_le: /* 0x37 */
1626/* File: mips64/op_if_le.S */
1627/* File: mips64/bincmp.S */
1628 /*
1629 * Generic two-operand compare-and-branch operation. Provide a "condition"
1630 * fragment that specifies the comparison to perform, e.g. for
1631 * "if-le" you would use "le".
1632 *
1633 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1634 */
1635 /* if-cmp vA, vB, +CCCC */
1636 lh a4, 2(rPC) # a4 <- sign-extended CCCC
1637 ext a2, rINST, 8, 4 # a2 <- A
1638 ext a3, rINST, 12, 4 # a3 <- B
1639 GET_VREG a0, a2 # a0 <- vA
1640 GET_VREG a1, a3 # a1 <- vB
1641
1642 blec a0, a1, 1f
1643 li a4, 2 # offset if branch not taken
16441:
1645
1646 dlsa rPC, a4, rPC, 1 # rPC <- rPC + CCCC * 2
1647 FETCH_INST # load rINST
1648
1649#if MTERP_SUSPEND
1650 bgez a4, 2f # CCCC * 2 >= 0 => no suspend check
1651 REFRESH_IBASE
16522:
1653#else
1654 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1655 bltz a4, MterpCheckSuspendAndContinue
1656#endif
1657
1658 GET_INST_OPCODE v0 # extract opcode from rINST
1659 GOTO_OPCODE v0 # jump to next instruction
1660
1661
1662/* ------------------------------ */
1663 .balign 128
1664.L_op_if_eqz: /* 0x38 */
1665/* File: mips64/op_if_eqz.S */
1666/* File: mips64/zcmp.S */
1667 /*
1668 * Generic one-operand compare-and-branch operation. Provide a "condition"
1669 * fragment that specifies the comparison to perform, e.g. for
1670 * "if-lez" you would use "le".
1671 *
1672 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1673 */
1674 /* if-cmp vAA, +BBBB */
1675 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1676 srl a2, rINST, 8 # a2 <- AA
1677 GET_VREG a0, a2 # a0 <- vAA
1678
1679 beqzc a0, 1f
1680 li a4, 2 # offset if branch not taken
16811:
1682
1683 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1684 FETCH_INST # load rINST
1685
1686#if MTERP_SUSPEND
1687 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1688 REFRESH_IBASE
16892:
1690#else
1691 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1692 bltz a4, MterpCheckSuspendAndContinue
1693#endif
1694
1695 GET_INST_OPCODE v0 # extract opcode from rINST
1696 GOTO_OPCODE v0 # jump to next instruction
1697
1698
1699/* ------------------------------ */
1700 .balign 128
1701.L_op_if_nez: /* 0x39 */
1702/* File: mips64/op_if_nez.S */
1703/* File: mips64/zcmp.S */
1704 /*
1705 * Generic one-operand compare-and-branch operation. Provide a "condition"
1706 * fragment that specifies the comparison to perform, e.g. for
1707 * "if-lez" you would use "le".
1708 *
1709 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1710 */
1711 /* if-cmp vAA, +BBBB */
1712 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1713 srl a2, rINST, 8 # a2 <- AA
1714 GET_VREG a0, a2 # a0 <- vAA
1715
1716 bnezc a0, 1f
1717 li a4, 2 # offset if branch not taken
17181:
1719
1720 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1721 FETCH_INST # load rINST
1722
1723#if MTERP_SUSPEND
1724 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1725 REFRESH_IBASE
17262:
1727#else
1728 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1729 bltz a4, MterpCheckSuspendAndContinue
1730#endif
1731
1732 GET_INST_OPCODE v0 # extract opcode from rINST
1733 GOTO_OPCODE v0 # jump to next instruction
1734
1735
1736/* ------------------------------ */
1737 .balign 128
1738.L_op_if_ltz: /* 0x3a */
1739/* File: mips64/op_if_ltz.S */
1740/* File: mips64/zcmp.S */
1741 /*
1742 * Generic one-operand compare-and-branch operation. Provide a "condition"
1743 * fragment that specifies the comparison to perform, e.g. for
1744 * "if-lez" you would use "le".
1745 *
1746 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1747 */
1748 /* if-cmp vAA, +BBBB */
1749 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1750 srl a2, rINST, 8 # a2 <- AA
1751 GET_VREG a0, a2 # a0 <- vAA
1752
1753 bltzc a0, 1f
1754 li a4, 2 # offset if branch not taken
17551:
1756
1757 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1758 FETCH_INST # load rINST
1759
1760#if MTERP_SUSPEND
1761 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1762 REFRESH_IBASE
17632:
1764#else
1765 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1766 bltz a4, MterpCheckSuspendAndContinue
1767#endif
1768
1769 GET_INST_OPCODE v0 # extract opcode from rINST
1770 GOTO_OPCODE v0 # jump to next instruction
1771
1772
1773/* ------------------------------ */
1774 .balign 128
1775.L_op_if_gez: /* 0x3b */
1776/* File: mips64/op_if_gez.S */
1777/* File: mips64/zcmp.S */
1778 /*
1779 * Generic one-operand compare-and-branch operation. Provide a "condition"
1780 * fragment that specifies the comparison to perform, e.g. for
1781 * "if-lez" you would use "le".
1782 *
1783 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1784 */
1785 /* if-cmp vAA, +BBBB */
1786 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1787 srl a2, rINST, 8 # a2 <- AA
1788 GET_VREG a0, a2 # a0 <- vAA
1789
1790 bgezc a0, 1f
1791 li a4, 2 # offset if branch not taken
17921:
1793
1794 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1795 FETCH_INST # load rINST
1796
1797#if MTERP_SUSPEND
1798 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1799 REFRESH_IBASE
18002:
1801#else
1802 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1803 bltz a4, MterpCheckSuspendAndContinue
1804#endif
1805
1806 GET_INST_OPCODE v0 # extract opcode from rINST
1807 GOTO_OPCODE v0 # jump to next instruction
1808
1809
1810/* ------------------------------ */
1811 .balign 128
1812.L_op_if_gtz: /* 0x3c */
1813/* File: mips64/op_if_gtz.S */
1814/* File: mips64/zcmp.S */
1815 /*
1816 * Generic one-operand compare-and-branch operation. Provide a "condition"
1817 * fragment that specifies the comparison to perform, e.g. for
1818 * "if-lez" you would use "le".
1819 *
1820 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1821 */
1822 /* if-cmp vAA, +BBBB */
1823 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1824 srl a2, rINST, 8 # a2 <- AA
1825 GET_VREG a0, a2 # a0 <- vAA
1826
1827 bgtzc a0, 1f
1828 li a4, 2 # offset if branch not taken
18291:
1830
1831 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1832 FETCH_INST # load rINST
1833
1834#if MTERP_SUSPEND
1835 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1836 REFRESH_IBASE
18372:
1838#else
1839 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1840 bltz a4, MterpCheckSuspendAndContinue
1841#endif
1842
1843 GET_INST_OPCODE v0 # extract opcode from rINST
1844 GOTO_OPCODE v0 # jump to next instruction
1845
1846
1847/* ------------------------------ */
1848 .balign 128
1849.L_op_if_lez: /* 0x3d */
1850/* File: mips64/op_if_lez.S */
1851/* File: mips64/zcmp.S */
1852 /*
1853 * Generic one-operand compare-and-branch operation. Provide a "condition"
1854 * fragment that specifies the comparison to perform, e.g. for
1855 * "if-lez" you would use "le".
1856 *
1857 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1858 */
1859 /* if-cmp vAA, +BBBB */
1860 lh a4, 2(rPC) # a4 <- sign-extended BBBB
1861 srl a2, rINST, 8 # a2 <- AA
1862 GET_VREG a0, a2 # a0 <- vAA
1863
1864 blezc a0, 1f
1865 li a4, 2 # offset if branch not taken
18661:
1867
1868 dlsa rPC, a4, rPC, 1 # rPC <- rPC + BBBB * 2
1869 FETCH_INST # load rINST
1870
1871#if MTERP_SUSPEND
1872 bgez a4, 2f # BBBB * 2 >= 0 => no suspend check
1873 REFRESH_IBASE
18742:
1875#else
1876 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue
1877 bltz a4, MterpCheckSuspendAndContinue
1878#endif
1879
1880 GET_INST_OPCODE v0 # extract opcode from rINST
1881 GOTO_OPCODE v0 # jump to next instruction
1882
1883
1884/* ------------------------------ */
1885 .balign 128
1886.L_op_unused_3e: /* 0x3e */
1887/* File: mips64/op_unused_3e.S */
1888/* File: mips64/unused.S */
1889/*
1890 * Bail to reference interpreter to throw.
1891 */
1892 b MterpFallback
1893
1894
1895/* ------------------------------ */
1896 .balign 128
1897.L_op_unused_3f: /* 0x3f */
1898/* File: mips64/op_unused_3f.S */
1899/* File: mips64/unused.S */
1900/*
1901 * Bail to reference interpreter to throw.
1902 */
1903 b MterpFallback
1904
1905
1906/* ------------------------------ */
1907 .balign 128
1908.L_op_unused_40: /* 0x40 */
1909/* File: mips64/op_unused_40.S */
1910/* File: mips64/unused.S */
1911/*
1912 * Bail to reference interpreter to throw.
1913 */
1914 b MterpFallback
1915
1916
1917/* ------------------------------ */
1918 .balign 128
1919.L_op_unused_41: /* 0x41 */
1920/* File: mips64/op_unused_41.S */
1921/* File: mips64/unused.S */
1922/*
1923 * Bail to reference interpreter to throw.
1924 */
1925 b MterpFallback
1926
1927
1928/* ------------------------------ */
1929 .balign 128
1930.L_op_unused_42: /* 0x42 */
1931/* File: mips64/op_unused_42.S */
1932/* File: mips64/unused.S */
1933/*
1934 * Bail to reference interpreter to throw.
1935 */
1936 b MterpFallback
1937
1938
1939/* ------------------------------ */
1940 .balign 128
1941.L_op_unused_43: /* 0x43 */
1942/* File: mips64/op_unused_43.S */
1943/* File: mips64/unused.S */
1944/*
1945 * Bail to reference interpreter to throw.
1946 */
1947 b MterpFallback
1948
1949
1950/* ------------------------------ */
1951 .balign 128
1952.L_op_aget: /* 0x44 */
1953/* File: mips64/op_aget.S */
1954 /*
1955 * Array get, 32 bits or less. vAA <- vBB[vCC].
1956 *
1957 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
1958 *
1959 * NOTE: assumes data offset for arrays is the same for all non-wide types.
1960 * If this changes, specialize.
1961 */
1962 /* op vAA, vBB, vCC */
1963 lbu a2, 2(rPC) # a2 <- BB
1964 lbu a3, 3(rPC) # a3 <- CC
1965 srl a4, rINST, 8 # a4 <- AA
1966 GET_VREG_U a0, a2 # a0 <- vBB (array object)
1967 GET_VREG a1, a3 # a1 <- vCC (requested index)
1968 beqz a0, common_errNullObject # bail if null array object
1969 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
1970 .if 2
1971 # [d]lsa does not support shift count of 0.
1972 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width
1973 .else
1974 daddu a0, a1, a0 # a0 <- arrayObj + index*width
1975 .endif
1976 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
1977 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
1978 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
1979 GET_INST_OPCODE v0 # extract opcode from rINST
1980 SET_VREG a2, a4 # vAA <- a2
1981 GOTO_OPCODE v0 # jump to next instruction
1982
1983/* ------------------------------ */
1984 .balign 128
1985.L_op_aget_wide: /* 0x45 */
1986/* File: mips64/op_aget_wide.S */
1987 /*
1988 * Array get, 64 bits. vAA <- vBB[vCC].
1989 *
1990 */
1991 /* aget-wide vAA, vBB, vCC */
1992 lbu a2, 2(rPC) # a2 <- BB
1993 lbu a3, 3(rPC) # a3 <- CC
1994 srl a4, rINST, 8 # a4 <- AA
1995 GET_VREG_U a0, a2 # a0 <- vBB (array object)
1996 GET_VREG a1, a3 # a1 <- vCC (requested index)
1997 beqz a0, common_errNullObject # bail if null array object
1998 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
1999 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width
2000 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2001 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2002 lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0)
2003 lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0)
2004 dinsu a2, a3, 32, 32 # a2 <- vBB[vCC]
2005 GET_INST_OPCODE v0 # extract opcode from rINST
2006 SET_VREG_WIDE a2, a4 # vAA <- a2
2007 GOTO_OPCODE v0 # jump to next instruction
2008
2009/* ------------------------------ */
2010 .balign 128
2011.L_op_aget_object: /* 0x46 */
2012/* File: mips64/op_aget_object.S */
2013 /*
2014 * Array object get. vAA <- vBB[vCC].
2015 *
2016 * for: aget-object
2017 */
2018 /* op vAA, vBB, vCC */
2019 .extern artAGetObjectFromMterp
2020 lbu a2, 2(rPC) # a2 <- BB
2021 lbu a3, 3(rPC) # a3 <- CC
2022 EXPORT_PC
2023 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2024 GET_VREG a1, a3 # a1 <- vCC (requested index)
2025 jal artAGetObjectFromMterp # (array, index)
2026 ld a1, THREAD_EXCEPTION_OFFSET(rSELF)
2027 srl a4, rINST, 8 # a4 <- AA
2028 PREFETCH_INST 2
2029 bnez a1, MterpException
2030 SET_VREG_OBJECT v0, a4 # vAA <- v0
2031 ADVANCE 2
2032 GET_INST_OPCODE v0 # extract opcode from rINST
2033 GOTO_OPCODE v0 # jump to next instruction
2034
2035/* ------------------------------ */
2036 .balign 128
2037.L_op_aget_boolean: /* 0x47 */
2038/* File: mips64/op_aget_boolean.S */
2039/* File: mips64/op_aget.S */
2040 /*
2041 * Array get, 32 bits or less. vAA <- vBB[vCC].
2042 *
2043 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2044 *
2045 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2046 * If this changes, specialize.
2047 */
2048 /* op vAA, vBB, vCC */
2049 lbu a2, 2(rPC) # a2 <- BB
2050 lbu a3, 3(rPC) # a3 <- CC
2051 srl a4, rINST, 8 # a4 <- AA
2052 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2053 GET_VREG a1, a3 # a1 <- vCC (requested index)
2054 beqz a0, common_errNullObject # bail if null array object
2055 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2056 .if 0
2057 # [d]lsa does not support shift count of 0.
2058 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width
2059 .else
2060 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2061 .endif
2062 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2063 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2064 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2065 GET_INST_OPCODE v0 # extract opcode from rINST
2066 SET_VREG a2, a4 # vAA <- a2
2067 GOTO_OPCODE v0 # jump to next instruction
2068
2069
2070/* ------------------------------ */
2071 .balign 128
2072.L_op_aget_byte: /* 0x48 */
2073/* File: mips64/op_aget_byte.S */
2074/* File: mips64/op_aget.S */
2075 /*
2076 * Array get, 32 bits or less. vAA <- vBB[vCC].
2077 *
2078 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2079 *
2080 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2081 * If this changes, specialize.
2082 */
2083 /* op vAA, vBB, vCC */
2084 lbu a2, 2(rPC) # a2 <- BB
2085 lbu a3, 3(rPC) # a3 <- CC
2086 srl a4, rINST, 8 # a4 <- AA
2087 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2088 GET_VREG a1, a3 # a1 <- vCC (requested index)
2089 beqz a0, common_errNullObject # bail if null array object
2090 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2091 .if 0
2092 # [d]lsa does not support shift count of 0.
2093 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width
2094 .else
2095 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2096 .endif
2097 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2098 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2099 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2100 GET_INST_OPCODE v0 # extract opcode from rINST
2101 SET_VREG a2, a4 # vAA <- a2
2102 GOTO_OPCODE v0 # jump to next instruction
2103
2104
2105/* ------------------------------ */
2106 .balign 128
2107.L_op_aget_char: /* 0x49 */
2108/* File: mips64/op_aget_char.S */
2109/* File: mips64/op_aget.S */
2110 /*
2111 * Array get, 32 bits or less. vAA <- vBB[vCC].
2112 *
2113 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2114 *
2115 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2116 * If this changes, specialize.
2117 */
2118 /* op vAA, vBB, vCC */
2119 lbu a2, 2(rPC) # a2 <- BB
2120 lbu a3, 3(rPC) # a3 <- CC
2121 srl a4, rINST, 8 # a4 <- AA
2122 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2123 GET_VREG a1, a3 # a1 <- vCC (requested index)
2124 beqz a0, common_errNullObject # bail if null array object
2125 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2126 .if 1
2127 # [d]lsa does not support shift count of 0.
2128 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width
2129 .else
2130 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2131 .endif
2132 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2133 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2134 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2135 GET_INST_OPCODE v0 # extract opcode from rINST
2136 SET_VREG a2, a4 # vAA <- a2
2137 GOTO_OPCODE v0 # jump to next instruction
2138
2139
2140/* ------------------------------ */
2141 .balign 128
2142.L_op_aget_short: /* 0x4a */
2143/* File: mips64/op_aget_short.S */
2144/* File: mips64/op_aget.S */
2145 /*
2146 * Array get, 32 bits or less. vAA <- vBB[vCC].
2147 *
2148 * for: aget, aget-boolean, aget-byte, aget-char, aget-short
2149 *
2150 * NOTE: assumes data offset for arrays is the same for all non-wide types.
2151 * If this changes, specialize.
2152 */
2153 /* op vAA, vBB, vCC */
2154 lbu a2, 2(rPC) # a2 <- BB
2155 lbu a3, 3(rPC) # a3 <- CC
2156 srl a4, rINST, 8 # a4 <- AA
2157 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2158 GET_VREG a1, a3 # a1 <- vCC (requested index)
2159 beqz a0, common_errNullObject # bail if null array object
2160 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2161 .if 1
2162 # [d]lsa does not support shift count of 0.
2163 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width
2164 .else
2165 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2166 .endif
2167 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2168 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2169 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC]
2170 GET_INST_OPCODE v0 # extract opcode from rINST
2171 SET_VREG a2, a4 # vAA <- a2
2172 GOTO_OPCODE v0 # jump to next instruction
2173
2174
2175/* ------------------------------ */
2176 .balign 128
2177.L_op_aput: /* 0x4b */
2178/* File: mips64/op_aput.S */
2179 /*
2180 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2181 *
2182 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2183 *
2184 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2185 * If this changes, specialize.
2186 */
2187 /* op vAA, vBB, vCC */
2188 lbu a2, 2(rPC) # a2 <- BB
2189 lbu a3, 3(rPC) # a3 <- CC
2190 srl a4, rINST, 8 # a4 <- AA
2191 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2192 GET_VREG a1, a3 # a1 <- vCC (requested index)
2193 beqz a0, common_errNullObject # bail if null array object
2194 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2195 .if 2
2196 # [d]lsa does not support shift count of 0.
2197 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width
2198 .else
2199 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2200 .endif
2201 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2202 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2203 GET_VREG a2, a4 # a2 <- vAA
2204 GET_INST_OPCODE v0 # extract opcode from rINST
2205 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2206 GOTO_OPCODE v0 # jump to next instruction
2207
2208/* ------------------------------ */
2209 .balign 128
2210.L_op_aput_wide: /* 0x4c */
2211/* File: mips64/op_aput_wide.S */
2212 /*
2213 * Array put, 64 bits. vBB[vCC] <- vAA.
2214 *
2215 */
2216 /* aput-wide vAA, vBB, vCC */
2217 lbu a2, 2(rPC) # a2 <- BB
2218 lbu a3, 3(rPC) # a3 <- CC
2219 srl a4, rINST, 8 # a4 <- AA
2220 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2221 GET_VREG a1, a3 # a1 <- vCC (requested index)
2222 beqz a0, common_errNullObject # bail if null array object
2223 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2224 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width
2225 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2226 GET_VREG_WIDE a2, a4 # a2 <- vAA
2227 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2228 GET_INST_OPCODE v0 # extract opcode from rINST
2229 sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0)
2230 dsrl32 a2, a2, 0
2231 sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2
2232 GOTO_OPCODE v0 # jump to next instruction
2233
2234/* ------------------------------ */
2235 .balign 128
2236.L_op_aput_object: /* 0x4d */
2237/* File: mips64/op_aput_object.S */
2238 /*
2239 * Store an object into an array. vBB[vCC] <- vAA.
2240 */
2241 /* op vAA, vBB, vCC */
2242 .extern MterpAputObject
2243 EXPORT_PC
2244 daddu a0, rFP, OFF_FP_SHADOWFRAME
2245 move a1, rPC
2246 move a2, rINST
2247 jal MterpAputObject
2248 beqzc v0, MterpPossibleException
2249 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2250 GET_INST_OPCODE v0 # extract opcode from rINST
2251 GOTO_OPCODE v0 # jump to next instruction
2252
2253/* ------------------------------ */
2254 .balign 128
2255.L_op_aput_boolean: /* 0x4e */
2256/* File: mips64/op_aput_boolean.S */
2257/* File: mips64/op_aput.S */
2258 /*
2259 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2260 *
2261 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2262 *
2263 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2264 * If this changes, specialize.
2265 */
2266 /* op vAA, vBB, vCC */
2267 lbu a2, 2(rPC) # a2 <- BB
2268 lbu a3, 3(rPC) # a3 <- CC
2269 srl a4, rINST, 8 # a4 <- AA
2270 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2271 GET_VREG a1, a3 # a1 <- vCC (requested index)
2272 beqz a0, common_errNullObject # bail if null array object
2273 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2274 .if 0
2275 # [d]lsa does not support shift count of 0.
2276 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width
2277 .else
2278 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2279 .endif
2280 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2281 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2282 GET_VREG a2, a4 # a2 <- vAA
2283 GET_INST_OPCODE v0 # extract opcode from rINST
2284 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2285 GOTO_OPCODE v0 # jump to next instruction
2286
2287
2288/* ------------------------------ */
2289 .balign 128
2290.L_op_aput_byte: /* 0x4f */
2291/* File: mips64/op_aput_byte.S */
2292/* File: mips64/op_aput.S */
2293 /*
2294 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2295 *
2296 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2297 *
2298 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2299 * If this changes, specialize.
2300 */
2301 /* op vAA, vBB, vCC */
2302 lbu a2, 2(rPC) # a2 <- BB
2303 lbu a3, 3(rPC) # a3 <- CC
2304 srl a4, rINST, 8 # a4 <- AA
2305 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2306 GET_VREG a1, a3 # a1 <- vCC (requested index)
2307 beqz a0, common_errNullObject # bail if null array object
2308 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2309 .if 0
2310 # [d]lsa does not support shift count of 0.
2311 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width
2312 .else
2313 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2314 .endif
2315 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2316 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2317 GET_VREG a2, a4 # a2 <- vAA
2318 GET_INST_OPCODE v0 # extract opcode from rINST
2319 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2320 GOTO_OPCODE v0 # jump to next instruction
2321
2322
2323/* ------------------------------ */
2324 .balign 128
2325.L_op_aput_char: /* 0x50 */
2326/* File: mips64/op_aput_char.S */
2327/* File: mips64/op_aput.S */
2328 /*
2329 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2330 *
2331 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2332 *
2333 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2334 * If this changes, specialize.
2335 */
2336 /* op vAA, vBB, vCC */
2337 lbu a2, 2(rPC) # a2 <- BB
2338 lbu a3, 3(rPC) # a3 <- CC
2339 srl a4, rINST, 8 # a4 <- AA
2340 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2341 GET_VREG a1, a3 # a1 <- vCC (requested index)
2342 beqz a0, common_errNullObject # bail if null array object
2343 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2344 .if 1
2345 # [d]lsa does not support shift count of 0.
2346 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width
2347 .else
2348 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2349 .endif
2350 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2351 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2352 GET_VREG a2, a4 # a2 <- vAA
2353 GET_INST_OPCODE v0 # extract opcode from rINST
2354 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2355 GOTO_OPCODE v0 # jump to next instruction
2356
2357
2358/* ------------------------------ */
2359 .balign 128
2360.L_op_aput_short: /* 0x51 */
2361/* File: mips64/op_aput_short.S */
2362/* File: mips64/op_aput.S */
2363 /*
2364 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2365 *
2366 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2367 *
2368 * NOTE: this assumes data offset for arrays is the same for all non-wide types.
2369 * If this changes, specialize.
2370 */
2371 /* op vAA, vBB, vCC */
2372 lbu a2, 2(rPC) # a2 <- BB
2373 lbu a3, 3(rPC) # a3 <- CC
2374 srl a4, rINST, 8 # a4 <- AA
2375 GET_VREG_U a0, a2 # a0 <- vBB (array object)
2376 GET_VREG a1, a3 # a1 <- vCC (requested index)
2377 beqz a0, common_errNullObject # bail if null array object
2378 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length
2379 .if 1
2380 # [d]lsa does not support shift count of 0.
2381 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width
2382 .else
2383 daddu a0, a1, a0 # a0 <- arrayObj + index*width
2384 .endif
2385 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail
2386 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2387 GET_VREG a2, a4 # a2 <- vAA
2388 GET_INST_OPCODE v0 # extract opcode from rINST
2389 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2
2390 GOTO_OPCODE v0 # jump to next instruction
2391
2392
2393/* ------------------------------ */
2394 .balign 128
2395.L_op_iget: /* 0x52 */
2396/* File: mips64/op_iget.S */
2397 /*
2398 * General instance field get.
2399 *
2400 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2401 */
2402 .extern artGet32InstanceFromCode
2403 EXPORT_PC
2404 lhu a0, 2(rPC) # a0 <- field ref CCCC
2405 srl a1, rINST, 12 # a1 <- B
2406 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2407 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2408 move a3, rSELF # a3 <- self
2409 jal artGet32InstanceFromCode
2410 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2411 ext a2, rINST, 8, 4 # a2 <- A
2412 PREFETCH_INST 2
2413 bnez a3, MterpPossibleException # bail out
2414 .if 0
2415 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2416 .else
2417 SET_VREG v0, a2 # fp[A] <- v0
2418 .endif
2419 ADVANCE 2
2420 GET_INST_OPCODE v0 # extract opcode from rINST
2421 GOTO_OPCODE v0 # jump to next instruction
2422
2423/* ------------------------------ */
2424 .balign 128
2425.L_op_iget_wide: /* 0x53 */
2426/* File: mips64/op_iget_wide.S */
2427 /*
2428 * 64-bit instance field get.
2429 *
2430 * for: iget-wide
2431 */
2432 .extern artGet64InstanceFromCode
2433 EXPORT_PC
2434 lhu a0, 2(rPC) # a0 <- field ref CCCC
2435 srl a1, rINST, 12 # a1 <- B
2436 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2437 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2438 move a3, rSELF # a3 <- self
2439 jal artGet64InstanceFromCode
2440 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2441 ext a2, rINST, 8, 4 # a2 <- A
2442 PREFETCH_INST 2
2443 bnez a3, MterpPossibleException # bail out
2444 SET_VREG_WIDE v0, a2 # fp[A] <- v0
2445 ADVANCE 2
2446 GET_INST_OPCODE v0 # extract opcode from rINST
2447 GOTO_OPCODE v0 # jump to next instruction
2448
2449/* ------------------------------ */
2450 .balign 128
2451.L_op_iget_object: /* 0x54 */
2452/* File: mips64/op_iget_object.S */
2453/* File: mips64/op_iget.S */
2454 /*
2455 * General instance field get.
2456 *
2457 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2458 */
2459 .extern artGetObjInstanceFromCode
2460 EXPORT_PC
2461 lhu a0, 2(rPC) # a0 <- field ref CCCC
2462 srl a1, rINST, 12 # a1 <- B
2463 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2464 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2465 move a3, rSELF # a3 <- self
2466 jal artGetObjInstanceFromCode
2467 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2468 ext a2, rINST, 8, 4 # a2 <- A
2469 PREFETCH_INST 2
2470 bnez a3, MterpPossibleException # bail out
2471 .if 1
2472 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2473 .else
2474 SET_VREG v0, a2 # fp[A] <- v0
2475 .endif
2476 ADVANCE 2
2477 GET_INST_OPCODE v0 # extract opcode from rINST
2478 GOTO_OPCODE v0 # jump to next instruction
2479
2480
2481/* ------------------------------ */
2482 .balign 128
2483.L_op_iget_boolean: /* 0x55 */
2484/* File: mips64/op_iget_boolean.S */
2485/* File: mips64/op_iget.S */
2486 /*
2487 * General instance field get.
2488 *
2489 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2490 */
2491 .extern artGetBooleanInstanceFromCode
2492 EXPORT_PC
2493 lhu a0, 2(rPC) # a0 <- field ref CCCC
2494 srl a1, rINST, 12 # a1 <- B
2495 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2496 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2497 move a3, rSELF # a3 <- self
2498 jal artGetBooleanInstanceFromCode
2499 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2500 ext a2, rINST, 8, 4 # a2 <- A
2501 PREFETCH_INST 2
2502 bnez a3, MterpPossibleException # bail out
2503 .if 0
2504 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2505 .else
2506 SET_VREG v0, a2 # fp[A] <- v0
2507 .endif
2508 ADVANCE 2
2509 GET_INST_OPCODE v0 # extract opcode from rINST
2510 GOTO_OPCODE v0 # jump to next instruction
2511
2512
2513/* ------------------------------ */
2514 .balign 128
2515.L_op_iget_byte: /* 0x56 */
2516/* File: mips64/op_iget_byte.S */
2517/* File: mips64/op_iget.S */
2518 /*
2519 * General instance field get.
2520 *
2521 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2522 */
2523 .extern artGetByteInstanceFromCode
2524 EXPORT_PC
2525 lhu a0, 2(rPC) # a0 <- field ref CCCC
2526 srl a1, rINST, 12 # a1 <- B
2527 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2528 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2529 move a3, rSELF # a3 <- self
2530 jal artGetByteInstanceFromCode
2531 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2532 ext a2, rINST, 8, 4 # a2 <- A
2533 PREFETCH_INST 2
2534 bnez a3, MterpPossibleException # bail out
2535 .if 0
2536 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2537 .else
2538 SET_VREG v0, a2 # fp[A] <- v0
2539 .endif
2540 ADVANCE 2
2541 GET_INST_OPCODE v0 # extract opcode from rINST
2542 GOTO_OPCODE v0 # jump to next instruction
2543
2544
2545/* ------------------------------ */
2546 .balign 128
2547.L_op_iget_char: /* 0x57 */
2548/* File: mips64/op_iget_char.S */
2549/* File: mips64/op_iget.S */
2550 /*
2551 * General instance field get.
2552 *
2553 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2554 */
2555 .extern artGetCharInstanceFromCode
2556 EXPORT_PC
2557 lhu a0, 2(rPC) # a0 <- field ref CCCC
2558 srl a1, rINST, 12 # a1 <- B
2559 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2560 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2561 move a3, rSELF # a3 <- self
2562 jal artGetCharInstanceFromCode
2563 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2564 ext a2, rINST, 8, 4 # a2 <- A
2565 PREFETCH_INST 2
2566 bnez a3, MterpPossibleException # bail out
2567 .if 0
2568 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2569 .else
2570 SET_VREG v0, a2 # fp[A] <- v0
2571 .endif
2572 ADVANCE 2
2573 GET_INST_OPCODE v0 # extract opcode from rINST
2574 GOTO_OPCODE v0 # jump to next instruction
2575
2576
2577/* ------------------------------ */
2578 .balign 128
2579.L_op_iget_short: /* 0x58 */
2580/* File: mips64/op_iget_short.S */
2581/* File: mips64/op_iget.S */
2582 /*
2583 * General instance field get.
2584 *
2585 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2586 */
2587 .extern artGetShortInstanceFromCode
2588 EXPORT_PC
2589 lhu a0, 2(rPC) # a0 <- field ref CCCC
2590 srl a1, rINST, 12 # a1 <- B
2591 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2592 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer
2593 move a3, rSELF # a3 <- self
2594 jal artGetShortInstanceFromCode
2595 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2596 ext a2, rINST, 8, 4 # a2 <- A
2597 PREFETCH_INST 2
2598 bnez a3, MterpPossibleException # bail out
2599 .if 0
2600 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
2601 .else
2602 SET_VREG v0, a2 # fp[A] <- v0
2603 .endif
2604 ADVANCE 2
2605 GET_INST_OPCODE v0 # extract opcode from rINST
2606 GOTO_OPCODE v0 # jump to next instruction
2607
2608
2609/* ------------------------------ */
2610 .balign 128
2611.L_op_iput: /* 0x59 */
2612/* File: mips64/op_iput.S */
2613 /*
2614 * General 32-bit instance field put.
2615 *
2616 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2617 */
2618 /* op vA, vB, field//CCCC */
2619 .extern artSet32InstanceFromMterp
2620 EXPORT_PC
2621 lhu a0, 2(rPC) # a0 <- field ref CCCC
2622 srl a1, rINST, 12 # a1 <- B
2623 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2624 ext a2, rINST, 8, 4 # a2 <- A
2625 GET_VREG a2, a2 # a2 <- fp[A]
2626 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2627 PREFETCH_INST 2
2628 jal artSet32InstanceFromMterp
2629 bnez v0, MterpPossibleException # bail out
2630 ADVANCE 2
2631 GET_INST_OPCODE v0 # extract opcode from rINST
2632 GOTO_OPCODE v0 # jump to next instruction
2633
2634/* ------------------------------ */
2635 .balign 128
2636.L_op_iput_wide: /* 0x5a */
2637/* File: mips64/op_iput_wide.S */
2638 /* iput-wide vA, vB, field//CCCC */
2639 .extern artSet64InstanceFromMterp
2640 EXPORT_PC
2641 lhu a0, 2(rPC) # a0 <- field ref CCCC
2642 srl a1, rINST, 12 # a1 <- B
2643 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2644 ext a2, rINST, 8, 4 # a2 <- A
2645 dlsa a2, a2, rFP, 2 # a2 <- &fp[A]
2646 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2647 PREFETCH_INST 2
2648 jal artSet64InstanceFromMterp
2649 bnez v0, MterpPossibleException # bail out
2650 ADVANCE 2
2651 GET_INST_OPCODE v0 # extract opcode from rINST
2652 GOTO_OPCODE v0 # jump to next instruction
2653
2654/* ------------------------------ */
2655 .balign 128
2656.L_op_iput_object: /* 0x5b */
2657/* File: mips64/op_iput_object.S */
2658 .extern MterpIputObject
2659 EXPORT_PC
2660 daddu a0, rFP, OFF_FP_SHADOWFRAME
2661 move a1, rPC
2662 move a2, rINST
2663 move a3, rSELF
2664 jal MterpIputObject
2665 beqzc v0, MterpException
2666 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2667 GET_INST_OPCODE v0 # extract opcode from rINST
2668 GOTO_OPCODE v0 # jump to next instruction
2669
2670/* ------------------------------ */
2671 .balign 128
2672.L_op_iput_boolean: /* 0x5c */
2673/* File: mips64/op_iput_boolean.S */
2674/* File: mips64/op_iput.S */
2675 /*
2676 * General 32-bit instance field put.
2677 *
2678 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2679 */
2680 /* op vA, vB, field//CCCC */
2681 .extern artSet8InstanceFromMterp
2682 EXPORT_PC
2683 lhu a0, 2(rPC) # a0 <- field ref CCCC
2684 srl a1, rINST, 12 # a1 <- B
2685 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2686 ext a2, rINST, 8, 4 # a2 <- A
2687 GET_VREG a2, a2 # a2 <- fp[A]
2688 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2689 PREFETCH_INST 2
2690 jal artSet8InstanceFromMterp
2691 bnez v0, MterpPossibleException # bail out
2692 ADVANCE 2
2693 GET_INST_OPCODE v0 # extract opcode from rINST
2694 GOTO_OPCODE v0 # jump to next instruction
2695
2696
2697/* ------------------------------ */
2698 .balign 128
2699.L_op_iput_byte: /* 0x5d */
2700/* File: mips64/op_iput_byte.S */
2701/* File: mips64/op_iput.S */
2702 /*
2703 * General 32-bit instance field put.
2704 *
2705 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2706 */
2707 /* op vA, vB, field//CCCC */
2708 .extern artSet8InstanceFromMterp
2709 EXPORT_PC
2710 lhu a0, 2(rPC) # a0 <- field ref CCCC
2711 srl a1, rINST, 12 # a1 <- B
2712 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2713 ext a2, rINST, 8, 4 # a2 <- A
2714 GET_VREG a2, a2 # a2 <- fp[A]
2715 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2716 PREFETCH_INST 2
2717 jal artSet8InstanceFromMterp
2718 bnez v0, MterpPossibleException # bail out
2719 ADVANCE 2
2720 GET_INST_OPCODE v0 # extract opcode from rINST
2721 GOTO_OPCODE v0 # jump to next instruction
2722
2723
2724/* ------------------------------ */
2725 .balign 128
2726.L_op_iput_char: /* 0x5e */
2727/* File: mips64/op_iput_char.S */
2728/* File: mips64/op_iput.S */
2729 /*
2730 * General 32-bit instance field put.
2731 *
2732 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2733 */
2734 /* op vA, vB, field//CCCC */
2735 .extern artSet16InstanceFromMterp
2736 EXPORT_PC
2737 lhu a0, 2(rPC) # a0 <- field ref CCCC
2738 srl a1, rINST, 12 # a1 <- B
2739 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2740 ext a2, rINST, 8, 4 # a2 <- A
2741 GET_VREG a2, a2 # a2 <- fp[A]
2742 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2743 PREFETCH_INST 2
2744 jal artSet16InstanceFromMterp
2745 bnez v0, MterpPossibleException # bail out
2746 ADVANCE 2
2747 GET_INST_OPCODE v0 # extract opcode from rINST
2748 GOTO_OPCODE v0 # jump to next instruction
2749
2750
2751/* ------------------------------ */
2752 .balign 128
2753.L_op_iput_short: /* 0x5f */
2754/* File: mips64/op_iput_short.S */
2755/* File: mips64/op_iput.S */
2756 /*
2757 * General 32-bit instance field put.
2758 *
2759 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2760 */
2761 /* op vA, vB, field//CCCC */
2762 .extern artSet16InstanceFromMterp
2763 EXPORT_PC
2764 lhu a0, 2(rPC) # a0 <- field ref CCCC
2765 srl a1, rINST, 12 # a1 <- B
2766 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer
2767 ext a2, rINST, 8, 4 # a2 <- A
2768 GET_VREG a2, a2 # a2 <- fp[A]
2769 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer
2770 PREFETCH_INST 2
2771 jal artSet16InstanceFromMterp
2772 bnez v0, MterpPossibleException # bail out
2773 ADVANCE 2
2774 GET_INST_OPCODE v0 # extract opcode from rINST
2775 GOTO_OPCODE v0 # jump to next instruction
2776
2777
2778/* ------------------------------ */
2779 .balign 128
2780.L_op_sget: /* 0x60 */
2781/* File: mips64/op_sget.S */
2782 /*
2783 * General SGET handler wrapper.
2784 *
2785 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2786 */
2787 /* op vAA, field//BBBB */
2788 .extern artGet32StaticFromCode
2789 EXPORT_PC
2790 lhu a0, 2(rPC) # a0 <- field ref BBBB
2791 ld a1, OFF_FP_METHOD(rFP)
2792 move a2, rSELF
2793 jal artGet32StaticFromCode
2794 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2795 srl a2, rINST, 8 # a2 <- AA
2796
2797 PREFETCH_INST 2
2798 bnez a3, MterpException # bail out
2799 .if 0
2800 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2801 .else
2802 SET_VREG v0, a2 # fp[AA] <- v0
2803 .endif
2804 ADVANCE 2
2805 GET_INST_OPCODE v0 # extract opcode from rINST
2806 GOTO_OPCODE v0
2807
2808/* ------------------------------ */
2809 .balign 128
2810.L_op_sget_wide: /* 0x61 */
2811/* File: mips64/op_sget_wide.S */
2812 /*
2813 * SGET_WIDE handler wrapper.
2814 *
2815 */
2816 /* sget-wide vAA, field//BBBB */
2817 .extern artGet64StaticFromCode
2818 EXPORT_PC
2819 lhu a0, 2(rPC) # a0 <- field ref BBBB
2820 ld a1, OFF_FP_METHOD(rFP)
2821 move a2, rSELF
2822 jal artGet64StaticFromCode
2823 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2824 srl a4, rINST, 8 # a4 <- AA
2825 bnez a3, MterpException # bail out
2826 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
2827 SET_VREG_WIDE v0, a4
2828 GET_INST_OPCODE v0 # extract opcode from rINST
2829 GOTO_OPCODE v0 # jump to next instruction
2830
2831/* ------------------------------ */
2832 .balign 128
2833.L_op_sget_object: /* 0x62 */
2834/* File: mips64/op_sget_object.S */
2835/* File: mips64/op_sget.S */
2836 /*
2837 * General SGET handler wrapper.
2838 *
2839 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2840 */
2841 /* op vAA, field//BBBB */
2842 .extern artGetObjStaticFromCode
2843 EXPORT_PC
2844 lhu a0, 2(rPC) # a0 <- field ref BBBB
2845 ld a1, OFF_FP_METHOD(rFP)
2846 move a2, rSELF
2847 jal artGetObjStaticFromCode
2848 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2849 srl a2, rINST, 8 # a2 <- AA
2850
2851 PREFETCH_INST 2
2852 bnez a3, MterpException # bail out
2853 .if 1
2854 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2855 .else
2856 SET_VREG v0, a2 # fp[AA] <- v0
2857 .endif
2858 ADVANCE 2
2859 GET_INST_OPCODE v0 # extract opcode from rINST
2860 GOTO_OPCODE v0
2861
2862
2863/* ------------------------------ */
2864 .balign 128
2865.L_op_sget_boolean: /* 0x63 */
2866/* File: mips64/op_sget_boolean.S */
2867/* File: mips64/op_sget.S */
2868 /*
2869 * General SGET handler wrapper.
2870 *
2871 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2872 */
2873 /* op vAA, field//BBBB */
2874 .extern artGetBooleanStaticFromCode
2875 EXPORT_PC
2876 lhu a0, 2(rPC) # a0 <- field ref BBBB
2877 ld a1, OFF_FP_METHOD(rFP)
2878 move a2, rSELF
2879 jal artGetBooleanStaticFromCode
2880 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2881 srl a2, rINST, 8 # a2 <- AA
2882 and v0, v0, 0xff
2883 PREFETCH_INST 2
2884 bnez a3, MterpException # bail out
2885 .if 0
2886 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2887 .else
2888 SET_VREG v0, a2 # fp[AA] <- v0
2889 .endif
2890 ADVANCE 2
2891 GET_INST_OPCODE v0 # extract opcode from rINST
2892 GOTO_OPCODE v0
2893
2894
2895/* ------------------------------ */
2896 .balign 128
2897.L_op_sget_byte: /* 0x64 */
2898/* File: mips64/op_sget_byte.S */
2899/* File: mips64/op_sget.S */
2900 /*
2901 * General SGET handler wrapper.
2902 *
2903 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2904 */
2905 /* op vAA, field//BBBB */
2906 .extern artGetByteStaticFromCode
2907 EXPORT_PC
2908 lhu a0, 2(rPC) # a0 <- field ref BBBB
2909 ld a1, OFF_FP_METHOD(rFP)
2910 move a2, rSELF
2911 jal artGetByteStaticFromCode
2912 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2913 srl a2, rINST, 8 # a2 <- AA
2914 seb v0, v0
2915 PREFETCH_INST 2
2916 bnez a3, MterpException # bail out
2917 .if 0
2918 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2919 .else
2920 SET_VREG v0, a2 # fp[AA] <- v0
2921 .endif
2922 ADVANCE 2
2923 GET_INST_OPCODE v0 # extract opcode from rINST
2924 GOTO_OPCODE v0
2925
2926
2927/* ------------------------------ */
2928 .balign 128
2929.L_op_sget_char: /* 0x65 */
2930/* File: mips64/op_sget_char.S */
2931/* File: mips64/op_sget.S */
2932 /*
2933 * General SGET handler wrapper.
2934 *
2935 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2936 */
2937 /* op vAA, field//BBBB */
2938 .extern artGetCharStaticFromCode
2939 EXPORT_PC
2940 lhu a0, 2(rPC) # a0 <- field ref BBBB
2941 ld a1, OFF_FP_METHOD(rFP)
2942 move a2, rSELF
2943 jal artGetCharStaticFromCode
2944 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2945 srl a2, rINST, 8 # a2 <- AA
2946 and v0, v0, 0xffff
2947 PREFETCH_INST 2
2948 bnez a3, MterpException # bail out
2949 .if 0
2950 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2951 .else
2952 SET_VREG v0, a2 # fp[AA] <- v0
2953 .endif
2954 ADVANCE 2
2955 GET_INST_OPCODE v0 # extract opcode from rINST
2956 GOTO_OPCODE v0
2957
2958
2959/* ------------------------------ */
2960 .balign 128
2961.L_op_sget_short: /* 0x66 */
2962/* File: mips64/op_sget_short.S */
2963/* File: mips64/op_sget.S */
2964 /*
2965 * General SGET handler wrapper.
2966 *
2967 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2968 */
2969 /* op vAA, field//BBBB */
2970 .extern artGetShortStaticFromCode
2971 EXPORT_PC
2972 lhu a0, 2(rPC) # a0 <- field ref BBBB
2973 ld a1, OFF_FP_METHOD(rFP)
2974 move a2, rSELF
2975 jal artGetShortStaticFromCode
2976 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
2977 srl a2, rINST, 8 # a2 <- AA
2978 seh v0, v0
2979 PREFETCH_INST 2
2980 bnez a3, MterpException # bail out
2981 .if 0
2982 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0
2983 .else
2984 SET_VREG v0, a2 # fp[AA] <- v0
2985 .endif
2986 ADVANCE 2
2987 GET_INST_OPCODE v0 # extract opcode from rINST
2988 GOTO_OPCODE v0
2989
2990
2991/* ------------------------------ */
2992 .balign 128
2993.L_op_sput: /* 0x67 */
2994/* File: mips64/op_sput.S */
2995 /*
2996 * General SPUT handler wrapper.
2997 *
2998 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2999 */
3000 /* op vAA, field//BBBB */
3001 .extern artSet32StaticFromCode
3002 EXPORT_PC
3003 lhu a0, 2(rPC) # a0 <- field ref BBBB
3004 srl a3, rINST, 8 # a3 <- AA
3005 GET_VREG a1, a3 # a1 <- fp[AA]
3006 ld a2, OFF_FP_METHOD(rFP)
3007 move a3, rSELF
3008 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3009 jal artSet32StaticFromCode
3010 bnezc v0, MterpException # 0 on success
3011 ADVANCE 2 # Past exception point - now advance rPC
3012 GET_INST_OPCODE v0 # extract opcode from rINST
3013 GOTO_OPCODE v0 # jump to next instruction
3014
3015/* ------------------------------ */
3016 .balign 128
3017.L_op_sput_wide: /* 0x68 */
3018/* File: mips64/op_sput_wide.S */
3019 /*
3020 * SPUT_WIDE handler wrapper.
3021 *
3022 */
3023 /* sput-wide vAA, field//BBBB */
3024 .extern artSet64IndirectStaticFromMterp
3025 EXPORT_PC
3026 lhu a0, 2(rPC) # a0 <- field ref BBBB
3027 ld a1, OFF_FP_METHOD(rFP)
3028 srl a2, rINST, 8 # a2 <- AA
3029 dlsa a2, a2, rFP, 2
3030 move a3, rSELF
3031 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3032 jal artSet64IndirectStaticFromMterp
3033 bnezc v0, MterpException # 0 on success, -1 on failure
3034 ADVANCE 2 # Past exception point - now advance rPC
3035 GET_INST_OPCODE v0 # extract opcode from rINST
3036 GOTO_OPCODE v0 # jump to next instruction
3037
3038/* ------------------------------ */
3039 .balign 128
3040.L_op_sput_object: /* 0x69 */
3041/* File: mips64/op_sput_object.S */
3042 .extern MterpSputObject
3043 EXPORT_PC
3044 daddu a0, rFP, OFF_FP_SHADOWFRAME
3045 move a1, rPC
3046 move a2, rINST
3047 move a3, rSELF
3048 jal MterpSputObject
3049 beqzc v0, MterpException
3050 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
3051 GET_INST_OPCODE v0 # extract opcode from rINST
3052 GOTO_OPCODE v0 # jump to next instruction
3053
3054/* ------------------------------ */
3055 .balign 128
3056.L_op_sput_boolean: /* 0x6a */
3057/* File: mips64/op_sput_boolean.S */
3058/* File: mips64/op_sput.S */
3059 /*
3060 * General SPUT handler wrapper.
3061 *
3062 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3063 */
3064 /* op vAA, field//BBBB */
3065 .extern artSet8StaticFromCode
3066 EXPORT_PC
3067 lhu a0, 2(rPC) # a0 <- field ref BBBB
3068 srl a3, rINST, 8 # a3 <- AA
3069 GET_VREG a1, a3 # a1 <- fp[AA]
3070 ld a2, OFF_FP_METHOD(rFP)
3071 move a3, rSELF
3072 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3073 jal artSet8StaticFromCode
3074 bnezc v0, MterpException # 0 on success
3075 ADVANCE 2 # Past exception point - now advance rPC
3076 GET_INST_OPCODE v0 # extract opcode from rINST
3077 GOTO_OPCODE v0 # jump to next instruction
3078
3079
3080/* ------------------------------ */
3081 .balign 128
3082.L_op_sput_byte: /* 0x6b */
3083/* File: mips64/op_sput_byte.S */
3084/* File: mips64/op_sput.S */
3085 /*
3086 * General SPUT handler wrapper.
3087 *
3088 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3089 */
3090 /* op vAA, field//BBBB */
3091 .extern artSet8StaticFromCode
3092 EXPORT_PC
3093 lhu a0, 2(rPC) # a0 <- field ref BBBB
3094 srl a3, rINST, 8 # a3 <- AA
3095 GET_VREG a1, a3 # a1 <- fp[AA]
3096 ld a2, OFF_FP_METHOD(rFP)
3097 move a3, rSELF
3098 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3099 jal artSet8StaticFromCode
3100 bnezc v0, MterpException # 0 on success
3101 ADVANCE 2 # Past exception point - now advance rPC
3102 GET_INST_OPCODE v0 # extract opcode from rINST
3103 GOTO_OPCODE v0 # jump to next instruction
3104
3105
3106/* ------------------------------ */
3107 .balign 128
3108.L_op_sput_char: /* 0x6c */
3109/* File: mips64/op_sput_char.S */
3110/* File: mips64/op_sput.S */
3111 /*
3112 * General SPUT handler wrapper.
3113 *
3114 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3115 */
3116 /* op vAA, field//BBBB */
3117 .extern artSet16StaticFromCode
3118 EXPORT_PC
3119 lhu a0, 2(rPC) # a0 <- field ref BBBB
3120 srl a3, rINST, 8 # a3 <- AA
3121 GET_VREG a1, a3 # a1 <- fp[AA]
3122 ld a2, OFF_FP_METHOD(rFP)
3123 move a3, rSELF
3124 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3125 jal artSet16StaticFromCode
3126 bnezc v0, MterpException # 0 on success
3127 ADVANCE 2 # Past exception point - now advance rPC
3128 GET_INST_OPCODE v0 # extract opcode from rINST
3129 GOTO_OPCODE v0 # jump to next instruction
3130
3131
3132/* ------------------------------ */
3133 .balign 128
3134.L_op_sput_short: /* 0x6d */
3135/* File: mips64/op_sput_short.S */
3136/* File: mips64/op_sput.S */
3137 /*
3138 * General SPUT handler wrapper.
3139 *
3140 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3141 */
3142 /* op vAA, field//BBBB */
3143 .extern artSet16StaticFromCode
3144 EXPORT_PC
3145 lhu a0, 2(rPC) # a0 <- field ref BBBB
3146 srl a3, rINST, 8 # a3 <- AA
3147 GET_VREG a1, a3 # a1 <- fp[AA]
3148 ld a2, OFF_FP_METHOD(rFP)
3149 move a3, rSELF
3150 PREFETCH_INST 2 # Get next inst, but don't advance rPC
3151 jal artSet16StaticFromCode
3152 bnezc v0, MterpException # 0 on success
3153 ADVANCE 2 # Past exception point - now advance rPC
3154 GET_INST_OPCODE v0 # extract opcode from rINST
3155 GOTO_OPCODE v0 # jump to next instruction
3156
3157
3158/* ------------------------------ */
3159 .balign 128
3160.L_op_invoke_virtual: /* 0x6e */
3161/* File: mips64/op_invoke_virtual.S */
3162/* File: mips64/invoke.S */
3163 /*
3164 * Generic invoke handler wrapper.
3165 */
3166 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3167 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3168 .extern MterpInvokeVirtual
3169 EXPORT_PC
3170 move a0, rSELF
3171 daddu a1, rFP, OFF_FP_SHADOWFRAME
3172 move a2, rPC
3173 move a3, rINST
3174 jal MterpInvokeVirtual
3175 beqzc v0, MterpException
3176 FETCH_ADVANCE_INST 3
3177 GET_INST_OPCODE v0
3178 GOTO_OPCODE v0
3179
3180 /*
3181 * Handle a virtual method call.
3182 *
3183 * for: invoke-virtual, invoke-virtual/range
3184 */
3185 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3186 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3187
3188/* ------------------------------ */
3189 .balign 128
3190.L_op_invoke_super: /* 0x6f */
3191/* File: mips64/op_invoke_super.S */
3192/* File: mips64/invoke.S */
3193 /*
3194 * Generic invoke handler wrapper.
3195 */
3196 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3197 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3198 .extern MterpInvokeSuper
3199 EXPORT_PC
3200 move a0, rSELF
3201 daddu a1, rFP, OFF_FP_SHADOWFRAME
3202 move a2, rPC
3203 move a3, rINST
3204 jal MterpInvokeSuper
3205 beqzc v0, MterpException
3206 FETCH_ADVANCE_INST 3
3207 GET_INST_OPCODE v0
3208 GOTO_OPCODE v0
3209
3210 /*
3211 * Handle a "super" method call.
3212 *
3213 * for: invoke-super, invoke-super/range
3214 */
3215 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3216 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3217
3218/* ------------------------------ */
3219 .balign 128
3220.L_op_invoke_direct: /* 0x70 */
3221/* File: mips64/op_invoke_direct.S */
3222/* File: mips64/invoke.S */
3223 /*
3224 * Generic invoke handler wrapper.
3225 */
3226 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3227 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3228 .extern MterpInvokeDirect
3229 EXPORT_PC
3230 move a0, rSELF
3231 daddu a1, rFP, OFF_FP_SHADOWFRAME
3232 move a2, rPC
3233 move a3, rINST
3234 jal MterpInvokeDirect
3235 beqzc v0, MterpException
3236 FETCH_ADVANCE_INST 3
3237 GET_INST_OPCODE v0
3238 GOTO_OPCODE v0
3239
3240
3241/* ------------------------------ */
3242 .balign 128
3243.L_op_invoke_static: /* 0x71 */
3244/* File: mips64/op_invoke_static.S */
3245/* File: mips64/invoke.S */
3246 /*
3247 * Generic invoke handler wrapper.
3248 */
3249 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3250 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3251 .extern MterpInvokeStatic
3252 EXPORT_PC
3253 move a0, rSELF
3254 daddu a1, rFP, OFF_FP_SHADOWFRAME
3255 move a2, rPC
3256 move a3, rINST
3257 jal MterpInvokeStatic
3258 beqzc v0, MterpException
3259 FETCH_ADVANCE_INST 3
3260 GET_INST_OPCODE v0
3261 GOTO_OPCODE v0
3262
3263
3264/* ------------------------------ */
3265 .balign 128
3266.L_op_invoke_interface: /* 0x72 */
3267/* File: mips64/op_invoke_interface.S */
3268/* File: mips64/invoke.S */
3269 /*
3270 * Generic invoke handler wrapper.
3271 */
3272 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3273 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3274 .extern MterpInvokeInterface
3275 EXPORT_PC
3276 move a0, rSELF
3277 daddu a1, rFP, OFF_FP_SHADOWFRAME
3278 move a2, rPC
3279 move a3, rINST
3280 jal MterpInvokeInterface
3281 beqzc v0, MterpException
3282 FETCH_ADVANCE_INST 3
3283 GET_INST_OPCODE v0
3284 GOTO_OPCODE v0
3285
3286 /*
3287 * Handle an interface method call.
3288 *
3289 * for: invoke-interface, invoke-interface/range
3290 */
3291 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3292 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3293
3294/* ------------------------------ */
3295 .balign 128
3296.L_op_return_void_no_barrier: /* 0x73 */
3297/* File: mips64/op_return_void_no_barrier.S */
3298 .extern MterpSuspendCheck
3299 lw ra, THREAD_FLAGS_OFFSET(rSELF)
3300 move a0, rSELF
3301 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
3302 beqzc ra, 1f
3303 jal MterpSuspendCheck # (self)
33041:
3305 li a0, 0
3306 b MterpReturn
3307
3308/* ------------------------------ */
3309 .balign 128
3310.L_op_invoke_virtual_range: /* 0x74 */
3311/* File: mips64/op_invoke_virtual_range.S */
3312/* File: mips64/invoke.S */
3313 /*
3314 * Generic invoke handler wrapper.
3315 */
3316 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3317 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3318 .extern MterpInvokeVirtualRange
3319 EXPORT_PC
3320 move a0, rSELF
3321 daddu a1, rFP, OFF_FP_SHADOWFRAME
3322 move a2, rPC
3323 move a3, rINST
3324 jal MterpInvokeVirtualRange
3325 beqzc v0, MterpException
3326 FETCH_ADVANCE_INST 3
3327 GET_INST_OPCODE v0
3328 GOTO_OPCODE v0
3329
3330
3331/* ------------------------------ */
3332 .balign 128
3333.L_op_invoke_super_range: /* 0x75 */
3334/* File: mips64/op_invoke_super_range.S */
3335/* File: mips64/invoke.S */
3336 /*
3337 * Generic invoke handler wrapper.
3338 */
3339 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3340 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3341 .extern MterpInvokeSuperRange
3342 EXPORT_PC
3343 move a0, rSELF
3344 daddu a1, rFP, OFF_FP_SHADOWFRAME
3345 move a2, rPC
3346 move a3, rINST
3347 jal MterpInvokeSuperRange
3348 beqzc v0, MterpException
3349 FETCH_ADVANCE_INST 3
3350 GET_INST_OPCODE v0
3351 GOTO_OPCODE v0
3352
3353
3354/* ------------------------------ */
3355 .balign 128
3356.L_op_invoke_direct_range: /* 0x76 */
3357/* File: mips64/op_invoke_direct_range.S */
3358/* File: mips64/invoke.S */
3359 /*
3360 * Generic invoke handler wrapper.
3361 */
3362 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3363 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3364 .extern MterpInvokeDirectRange
3365 EXPORT_PC
3366 move a0, rSELF
3367 daddu a1, rFP, OFF_FP_SHADOWFRAME
3368 move a2, rPC
3369 move a3, rINST
3370 jal MterpInvokeDirectRange
3371 beqzc v0, MterpException
3372 FETCH_ADVANCE_INST 3
3373 GET_INST_OPCODE v0
3374 GOTO_OPCODE v0
3375
3376
3377/* ------------------------------ */
3378 .balign 128
3379.L_op_invoke_static_range: /* 0x77 */
3380/* File: mips64/op_invoke_static_range.S */
3381/* File: mips64/invoke.S */
3382 /*
3383 * Generic invoke handler wrapper.
3384 */
3385 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3386 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3387 .extern MterpInvokeStaticRange
3388 EXPORT_PC
3389 move a0, rSELF
3390 daddu a1, rFP, OFF_FP_SHADOWFRAME
3391 move a2, rPC
3392 move a3, rINST
3393 jal MterpInvokeStaticRange
3394 beqzc v0, MterpException
3395 FETCH_ADVANCE_INST 3
3396 GET_INST_OPCODE v0
3397 GOTO_OPCODE v0
3398
3399
3400/* ------------------------------ */
3401 .balign 128
3402.L_op_invoke_interface_range: /* 0x78 */
3403/* File: mips64/op_invoke_interface_range.S */
3404/* File: mips64/invoke.S */
3405 /*
3406 * Generic invoke handler wrapper.
3407 */
3408 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3409 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3410 .extern MterpInvokeInterfaceRange
3411 EXPORT_PC
3412 move a0, rSELF
3413 daddu a1, rFP, OFF_FP_SHADOWFRAME
3414 move a2, rPC
3415 move a3, rINST
3416 jal MterpInvokeInterfaceRange
3417 beqzc v0, MterpException
3418 FETCH_ADVANCE_INST 3
3419 GET_INST_OPCODE v0
3420 GOTO_OPCODE v0
3421
3422
3423/* ------------------------------ */
3424 .balign 128
3425.L_op_unused_79: /* 0x79 */
3426/* File: mips64/op_unused_79.S */
3427/* File: mips64/unused.S */
3428/*
3429 * Bail to reference interpreter to throw.
3430 */
3431 b MterpFallback
3432
3433
3434/* ------------------------------ */
3435 .balign 128
3436.L_op_unused_7a: /* 0x7a */
3437/* File: mips64/op_unused_7a.S */
3438/* File: mips64/unused.S */
3439/*
3440 * Bail to reference interpreter to throw.
3441 */
3442 b MterpFallback
3443
3444
3445/* ------------------------------ */
3446 .balign 128
3447.L_op_neg_int: /* 0x7b */
3448/* File: mips64/op_neg_int.S */
3449/* File: mips64/unop.S */
3450 /*
3451 * Generic 32-bit unary operation. Provide an "instr" line that
3452 * specifies an instruction that performs "a0 = op a0".
3453 *
3454 * for: int-to-byte, int-to-char, int-to-short,
3455 * not-int, neg-int
3456 */
3457 /* unop vA, vB */
3458 ext a3, rINST, 12, 4 # a3 <- B
3459 GET_VREG a0, a3 # a0 <- vB
3460 ext a2, rINST, 8, 4 # a2 <- A
3461 # optional op
3462 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3463 subu a0, zero, a0 # a0 <- op, a0-a3 changed
3464 GET_INST_OPCODE v0 # extract opcode from rINST
3465 SET_VREG a0, a2 # vA <- a0
3466 GOTO_OPCODE v0 # jump to next instruction
3467
3468
3469/* ------------------------------ */
3470 .balign 128
3471.L_op_not_int: /* 0x7c */
3472/* File: mips64/op_not_int.S */
3473/* File: mips64/unop.S */
3474 /*
3475 * Generic 32-bit unary operation. Provide an "instr" line that
3476 * specifies an instruction that performs "a0 = op a0".
3477 *
3478 * for: int-to-byte, int-to-char, int-to-short,
3479 * not-int, neg-int
3480 */
3481 /* unop vA, vB */
3482 ext a3, rINST, 12, 4 # a3 <- B
3483 GET_VREG a0, a3 # a0 <- vB
3484 ext a2, rINST, 8, 4 # a2 <- A
3485 # optional op
3486 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3487 nor a0, zero, a0 # a0 <- op, a0-a3 changed
3488 GET_INST_OPCODE v0 # extract opcode from rINST
3489 SET_VREG a0, a2 # vA <- a0
3490 GOTO_OPCODE v0 # jump to next instruction
3491
3492
3493/* ------------------------------ */
3494 .balign 128
3495.L_op_neg_long: /* 0x7d */
3496/* File: mips64/op_neg_long.S */
3497/* File: mips64/unopWide.S */
3498 /*
3499 * Generic 64-bit unary operation. Provide an "instr" line that
3500 * specifies an instruction that performs "a0 = op a0".
3501 *
3502 * For: not-long, neg-long
3503 */
3504 /* unop vA, vB */
3505 ext a3, rINST, 12, 4 # a3 <- B
3506 GET_VREG_WIDE a0, a3 # a0 <- vB
3507 ext a2, rINST, 8, 4 # a2 <- A
3508 # optional op
3509 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3510 dsubu a0, zero, a0 # a0 <- op, a0-a3 changed
3511 GET_INST_OPCODE v0 # extract opcode from rINST
3512 SET_VREG_WIDE a0, a2 # vA <- a0
3513 GOTO_OPCODE v0 # jump to next instruction
3514
3515
3516/* ------------------------------ */
3517 .balign 128
3518.L_op_not_long: /* 0x7e */
3519/* File: mips64/op_not_long.S */
3520/* File: mips64/unopWide.S */
3521 /*
3522 * Generic 64-bit unary operation. Provide an "instr" line that
3523 * specifies an instruction that performs "a0 = op a0".
3524 *
3525 * For: not-long, neg-long
3526 */
3527 /* unop vA, vB */
3528 ext a3, rINST, 12, 4 # a3 <- B
3529 GET_VREG_WIDE a0, a3 # a0 <- vB
3530 ext a2, rINST, 8, 4 # a2 <- A
3531 # optional op
3532 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3533 nor a0, zero, a0 # a0 <- op, a0-a3 changed
3534 GET_INST_OPCODE v0 # extract opcode from rINST
3535 SET_VREG_WIDE a0, a2 # vA <- a0
3536 GOTO_OPCODE v0 # jump to next instruction
3537
3538
3539/* ------------------------------ */
3540 .balign 128
3541.L_op_neg_float: /* 0x7f */
3542/* File: mips64/op_neg_float.S */
3543/* File: mips64/fcvtHeader.S */
3544 /*
3545 * Loads a specified register from vB. Used primarily for conversions
3546 * from or to a floating-point type.
3547 *
3548 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3549 * store the result in vA and jump to the next instruction.
3550 *
3551 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3552 * float-to-int, float-to-long, float-to-double, double-to-int,
3553 * double-to-long, double-to-float, neg-float, neg-double.
3554 */
3555 ext a1, rINST, 8, 4 # a1 <- A
3556 srl a2, rINST, 12 # a2 <- B
3557 GET_VREG_FLOAT f0, a2
3558 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3559
3560 neg.s f0, f0
3561/* File: mips64/fcvtFooter.S */
3562 /*
3563 * Stores a specified register containing the result of conversion
3564 * from or to a floating-point type and jumps to the next instruction.
3565 *
3566 * Expects a1 to contain the destination Dalvik register number.
3567 * a1 is set up by fcvtHeader.S.
3568 *
3569 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3570 * float-to-int, float-to-long, float-to-double, double-to-int,
3571 * double-to-long, double-to-float, neg-float, neg-double.
3572 *
3573 * Note that this file can't be included after a break in other files
3574 * and in those files its contents appear as a copy.
3575 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3576 */
3577 GET_INST_OPCODE v0 # extract opcode from rINST
3578 SET_VREG_FLOAT f0, a1
3579 GOTO_OPCODE v0 # jump to next instruction
3580
3581
3582/* ------------------------------ */
3583 .balign 128
3584.L_op_neg_double: /* 0x80 */
3585/* File: mips64/op_neg_double.S */
3586/* File: mips64/fcvtHeader.S */
3587 /*
3588 * Loads a specified register from vB. Used primarily for conversions
3589 * from or to a floating-point type.
3590 *
3591 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3592 * store the result in vA and jump to the next instruction.
3593 *
3594 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3595 * float-to-int, float-to-long, float-to-double, double-to-int,
3596 * double-to-long, double-to-float, neg-float, neg-double.
3597 */
3598 ext a1, rINST, 8, 4 # a1 <- A
3599 srl a2, rINST, 12 # a2 <- B
3600 GET_VREG_DOUBLE f0, a2
3601 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3602
3603 neg.d f0, f0
3604/* File: mips64/fcvtFooter.S */
3605 /*
3606 * Stores a specified register containing the result of conversion
3607 * from or to a floating-point type and jumps to the next instruction.
3608 *
3609 * Expects a1 to contain the destination Dalvik register number.
3610 * a1 is set up by fcvtHeader.S.
3611 *
3612 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3613 * float-to-int, float-to-long, float-to-double, double-to-int,
3614 * double-to-long, double-to-float, neg-float, neg-double.
3615 *
3616 * Note that this file can't be included after a break in other files
3617 * and in those files its contents appear as a copy.
3618 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3619 */
3620 GET_INST_OPCODE v0 # extract opcode from rINST
3621 SET_VREG_DOUBLE f0, a1
3622 GOTO_OPCODE v0 # jump to next instruction
3623
3624
3625/* ------------------------------ */
3626 .balign 128
3627.L_op_int_to_long: /* 0x81 */
3628/* File: mips64/op_int_to_long.S */
3629 /* int-to-long vA, vB */
3630 ext a3, rINST, 12, 4 # a3 <- B
3631 GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits)
3632 ext a2, rINST, 8, 4 # a2 <- A
3633 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3634 GET_INST_OPCODE v0 # extract opcode from rINST
3635 SET_VREG_WIDE a0, a2 # vA <- vB
3636 GOTO_OPCODE v0 # jump to next instruction
3637
3638/* ------------------------------ */
3639 .balign 128
3640.L_op_int_to_float: /* 0x82 */
3641/* File: mips64/op_int_to_float.S */
3642 /*
3643 * Conversion from or to floating-point happens in a floating-point register.
3644 * Therefore we load the input and store the output into or from a
3645 * floating-point register irrespective of the type.
3646 */
3647/* File: mips64/fcvtHeader.S */
3648 /*
3649 * Loads a specified register from vB. Used primarily for conversions
3650 * from or to a floating-point type.
3651 *
3652 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3653 * store the result in vA and jump to the next instruction.
3654 *
3655 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3656 * float-to-int, float-to-long, float-to-double, double-to-int,
3657 * double-to-long, double-to-float, neg-float, neg-double.
3658 */
3659 ext a1, rINST, 8, 4 # a1 <- A
3660 srl a2, rINST, 12 # a2 <- B
3661 GET_VREG_FLOAT f0, a2
3662 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3663
3664 cvt.s.w f0, f0
3665/* File: mips64/fcvtFooter.S */
3666 /*
3667 * Stores a specified register containing the result of conversion
3668 * from or to a floating-point type and jumps to the next instruction.
3669 *
3670 * Expects a1 to contain the destination Dalvik register number.
3671 * a1 is set up by fcvtHeader.S.
3672 *
3673 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3674 * float-to-int, float-to-long, float-to-double, double-to-int,
3675 * double-to-long, double-to-float, neg-float, neg-double.
3676 *
3677 * Note that this file can't be included after a break in other files
3678 * and in those files its contents appear as a copy.
3679 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3680 */
3681 GET_INST_OPCODE v0 # extract opcode from rINST
3682 SET_VREG_FLOAT f0, a1
3683 GOTO_OPCODE v0 # jump to next instruction
3684
3685
3686/* ------------------------------ */
3687 .balign 128
3688.L_op_int_to_double: /* 0x83 */
3689/* File: mips64/op_int_to_double.S */
3690 /*
3691 * Conversion from or to floating-point happens in a floating-point register.
3692 * Therefore we load the input and store the output into or from a
3693 * floating-point register irrespective of the type.
3694 */
3695/* File: mips64/fcvtHeader.S */
3696 /*
3697 * Loads a specified register from vB. Used primarily for conversions
3698 * from or to a floating-point type.
3699 *
3700 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3701 * store the result in vA and jump to the next instruction.
3702 *
3703 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3704 * float-to-int, float-to-long, float-to-double, double-to-int,
3705 * double-to-long, double-to-float, neg-float, neg-double.
3706 */
3707 ext a1, rINST, 8, 4 # a1 <- A
3708 srl a2, rINST, 12 # a2 <- B
3709 GET_VREG_FLOAT f0, a2
3710 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3711
3712 cvt.d.w f0, f0
3713/* File: mips64/fcvtFooter.S */
3714 /*
3715 * Stores a specified register containing the result of conversion
3716 * from or to a floating-point type and jumps to the next instruction.
3717 *
3718 * Expects a1 to contain the destination Dalvik register number.
3719 * a1 is set up by fcvtHeader.S.
3720 *
3721 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3722 * float-to-int, float-to-long, float-to-double, double-to-int,
3723 * double-to-long, double-to-float, neg-float, neg-double.
3724 *
3725 * Note that this file can't be included after a break in other files
3726 * and in those files its contents appear as a copy.
3727 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3728 */
3729 GET_INST_OPCODE v0 # extract opcode from rINST
3730 SET_VREG_DOUBLE f0, a1
3731 GOTO_OPCODE v0 # jump to next instruction
3732
3733
3734/* ------------------------------ */
3735 .balign 128
3736.L_op_long_to_int: /* 0x84 */
3737/* File: mips64/op_long_to_int.S */
3738/* we ignore the high word, making this equivalent to a 32-bit reg move */
3739/* File: mips64/op_move.S */
3740 /* for move, move-object, long-to-int */
3741 /* op vA, vB */
3742 ext a2, rINST, 8, 4 # a2 <- A
3743 ext a3, rINST, 12, 4 # a3 <- B
3744 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3745 GET_VREG a0, a3 # a0 <- vB
3746 GET_INST_OPCODE v0 # extract opcode from rINST
3747 .if 0
3748 SET_VREG_OBJECT a0, a2 # vA <- vB
3749 .else
3750 SET_VREG a0, a2 # vA <- vB
3751 .endif
3752 GOTO_OPCODE v0 # jump to next instruction
3753
3754
3755/* ------------------------------ */
3756 .balign 128
3757.L_op_long_to_float: /* 0x85 */
3758/* File: mips64/op_long_to_float.S */
3759 /*
3760 * Conversion from or to floating-point happens in a floating-point register.
3761 * Therefore we load the input and store the output into or from a
3762 * floating-point register irrespective of the type.
3763 */
3764/* File: mips64/fcvtHeader.S */
3765 /*
3766 * Loads a specified register from vB. Used primarily for conversions
3767 * from or to a floating-point type.
3768 *
3769 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3770 * store the result in vA and jump to the next instruction.
3771 *
3772 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3773 * float-to-int, float-to-long, float-to-double, double-to-int,
3774 * double-to-long, double-to-float, neg-float, neg-double.
3775 */
3776 ext a1, rINST, 8, 4 # a1 <- A
3777 srl a2, rINST, 12 # a2 <- B
3778 GET_VREG_DOUBLE f0, a2
3779 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3780
3781 cvt.s.l f0, f0
3782/* File: mips64/fcvtFooter.S */
3783 /*
3784 * Stores a specified register containing the result of conversion
3785 * from or to a floating-point type and jumps to the next instruction.
3786 *
3787 * Expects a1 to contain the destination Dalvik register number.
3788 * a1 is set up by fcvtHeader.S.
3789 *
3790 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3791 * float-to-int, float-to-long, float-to-double, double-to-int,
3792 * double-to-long, double-to-float, neg-float, neg-double.
3793 *
3794 * Note that this file can't be included after a break in other files
3795 * and in those files its contents appear as a copy.
3796 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3797 */
3798 GET_INST_OPCODE v0 # extract opcode from rINST
3799 SET_VREG_FLOAT f0, a1
3800 GOTO_OPCODE v0 # jump to next instruction
3801
3802
3803/* ------------------------------ */
3804 .balign 128
3805.L_op_long_to_double: /* 0x86 */
3806/* File: mips64/op_long_to_double.S */
3807 /*
3808 * Conversion from or to floating-point happens in a floating-point register.
3809 * Therefore we load the input and store the output into or from a
3810 * floating-point register irrespective of the type.
3811 */
3812/* File: mips64/fcvtHeader.S */
3813 /*
3814 * Loads a specified register from vB. Used primarily for conversions
3815 * from or to a floating-point type.
3816 *
3817 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3818 * store the result in vA and jump to the next instruction.
3819 *
3820 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3821 * float-to-int, float-to-long, float-to-double, double-to-int,
3822 * double-to-long, double-to-float, neg-float, neg-double.
3823 */
3824 ext a1, rINST, 8, 4 # a1 <- A
3825 srl a2, rINST, 12 # a2 <- B
3826 GET_VREG_DOUBLE f0, a2
3827 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3828
3829 cvt.d.l f0, f0
3830/* File: mips64/fcvtFooter.S */
3831 /*
3832 * Stores a specified register containing the result of conversion
3833 * from or to a floating-point type and jumps to the next instruction.
3834 *
3835 * Expects a1 to contain the destination Dalvik register number.
3836 * a1 is set up by fcvtHeader.S.
3837 *
3838 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3839 * float-to-int, float-to-long, float-to-double, double-to-int,
3840 * double-to-long, double-to-float, neg-float, neg-double.
3841 *
3842 * Note that this file can't be included after a break in other files
3843 * and in those files its contents appear as a copy.
3844 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3845 */
3846 GET_INST_OPCODE v0 # extract opcode from rINST
3847 SET_VREG_DOUBLE f0, a1
3848 GOTO_OPCODE v0 # jump to next instruction
3849
3850
3851/* ------------------------------ */
3852 .balign 128
3853.L_op_float_to_int: /* 0x87 */
3854/* File: mips64/op_float_to_int.S */
3855/* File: mips64/fcvtHeader.S */
3856 /*
3857 * Loads a specified register from vB. Used primarily for conversions
3858 * from or to a floating-point type.
3859 *
3860 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3861 * store the result in vA and jump to the next instruction.
3862 *
3863 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3864 * float-to-int, float-to-long, float-to-double, double-to-int,
3865 * double-to-long, double-to-float, neg-float, neg-double.
3866 */
3867 ext a1, rINST, 8, 4 # a1 <- A
3868 srl a2, rINST, 12 # a2 <- B
3869 GET_VREG_FLOAT f0, a2
3870 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3871
3872 /*
3873 * TODO: simplify this when the MIPS64R6 emulator
3874 * supports NAN2008=1.
3875 */
3876 li t0, INT_MIN_AS_FLOAT
3877 mtc1 t0, f1
3878 cmp.le.s f1, f1, f0
3879 bc1nez f1, .Lop_float_to_int_trunc
3880 cmp.eq.s f1, f0, f0
3881 li t0, INT_MIN
3882 mfc1 t1, f1
3883 and t0, t0, t1
3884 b .Lop_float_to_int_done
3885
3886/* ------------------------------ */
3887 .balign 128
3888.L_op_float_to_long: /* 0x88 */
3889/* File: mips64/op_float_to_long.S */
3890/* File: mips64/fcvtHeader.S */
3891 /*
3892 * Loads a specified register from vB. Used primarily for conversions
3893 * from or to a floating-point type.
3894 *
3895 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3896 * store the result in vA and jump to the next instruction.
3897 *
3898 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3899 * float-to-int, float-to-long, float-to-double, double-to-int,
3900 * double-to-long, double-to-float, neg-float, neg-double.
3901 */
3902 ext a1, rINST, 8, 4 # a1 <- A
3903 srl a2, rINST, 12 # a2 <- B
3904 GET_VREG_FLOAT f0, a2
3905 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3906
3907 /*
3908 * TODO: simplify this when the MIPS64R6 emulator
3909 * supports NAN2008=1.
3910 */
3911 li t0, LONG_MIN_AS_FLOAT
3912 mtc1 t0, f1
3913 cmp.le.s f1, f1, f0
3914 bc1nez f1, .Lop_float_to_long_trunc
3915 cmp.eq.s f1, f0, f0
3916 dli t0, LONG_MIN
3917 mfc1 t1, f1
3918 and t0, t0, t1
3919 b .Lop_float_to_long_done
3920
3921/* ------------------------------ */
3922 .balign 128
3923.L_op_float_to_double: /* 0x89 */
3924/* File: mips64/op_float_to_double.S */
3925 /*
3926 * Conversion from or to floating-point happens in a floating-point register.
3927 * Therefore we load the input and store the output into or from a
3928 * floating-point register irrespective of the type.
3929 */
3930/* File: mips64/fcvtHeader.S */
3931 /*
3932 * Loads a specified register from vB. Used primarily for conversions
3933 * from or to a floating-point type.
3934 *
3935 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3936 * store the result in vA and jump to the next instruction.
3937 *
3938 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3939 * float-to-int, float-to-long, float-to-double, double-to-int,
3940 * double-to-long, double-to-float, neg-float, neg-double.
3941 */
3942 ext a1, rINST, 8, 4 # a1 <- A
3943 srl a2, rINST, 12 # a2 <- B
3944 GET_VREG_FLOAT f0, a2
3945 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3946
3947 cvt.d.s f0, f0
3948/* File: mips64/fcvtFooter.S */
3949 /*
3950 * Stores a specified register containing the result of conversion
3951 * from or to a floating-point type and jumps to the next instruction.
3952 *
3953 * Expects a1 to contain the destination Dalvik register number.
3954 * a1 is set up by fcvtHeader.S.
3955 *
3956 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3957 * float-to-int, float-to-long, float-to-double, double-to-int,
3958 * double-to-long, double-to-float, neg-float, neg-double.
3959 *
3960 * Note that this file can't be included after a break in other files
3961 * and in those files its contents appear as a copy.
3962 * See: float-to-int, float-to-long, double-to-int, double-to-long.
3963 */
3964 GET_INST_OPCODE v0 # extract opcode from rINST
3965 SET_VREG_DOUBLE f0, a1
3966 GOTO_OPCODE v0 # jump to next instruction
3967
3968
3969/* ------------------------------ */
3970 .balign 128
3971.L_op_double_to_int: /* 0x8a */
3972/* File: mips64/op_double_to_int.S */
3973/* File: mips64/fcvtHeader.S */
3974 /*
3975 * Loads a specified register from vB. Used primarily for conversions
3976 * from or to a floating-point type.
3977 *
3978 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
3979 * store the result in vA and jump to the next instruction.
3980 *
3981 * For: int-to-float, int-to-double, long-to-float, long-to-double,
3982 * float-to-int, float-to-long, float-to-double, double-to-int,
3983 * double-to-long, double-to-float, neg-float, neg-double.
3984 */
3985 ext a1, rINST, 8, 4 # a1 <- A
3986 srl a2, rINST, 12 # a2 <- B
3987 GET_VREG_DOUBLE f0, a2
3988 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
3989
3990 /*
3991 * TODO: simplify this when the MIPS64R6 emulator
3992 * supports NAN2008=1.
3993 */
3994 dli t0, INT_MIN_AS_DOUBLE
3995 dmtc1 t0, f1
3996 cmp.le.d f1, f1, f0
3997 bc1nez f1, .Lop_double_to_int_trunc
3998 cmp.eq.d f1, f0, f0
3999 li t0, INT_MIN
4000 mfc1 t1, f1
4001 and t0, t0, t1
4002 b .Lop_double_to_int_done
4003
4004/* ------------------------------ */
4005 .balign 128
4006.L_op_double_to_long: /* 0x8b */
4007/* File: mips64/op_double_to_long.S */
4008/* File: mips64/fcvtHeader.S */
4009 /*
4010 * Loads a specified register from vB. Used primarily for conversions
4011 * from or to a floating-point type.
4012 *
4013 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
4014 * store the result in vA and jump to the next instruction.
4015 *
4016 * For: int-to-float, int-to-double, long-to-float, long-to-double,
4017 * float-to-int, float-to-long, float-to-double, double-to-int,
4018 * double-to-long, double-to-float, neg-float, neg-double.
4019 */
4020 ext a1, rINST, 8, 4 # a1 <- A
4021 srl a2, rINST, 12 # a2 <- B
4022 GET_VREG_DOUBLE f0, a2
4023 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
4024
4025 /*
4026 * TODO: simplify this when the MIPS64R6 emulator
4027 * supports NAN2008=1.
4028 */
4029 dli t0, LONG_MIN_AS_DOUBLE
4030 dmtc1 t0, f1
4031 cmp.le.d f1, f1, f0
4032 bc1nez f1, .Lop_double_to_long_trunc
4033 cmp.eq.d f1, f0, f0
4034 dli t0, LONG_MIN
4035 mfc1 t1, f1
4036 and t0, t0, t1
4037 b .Lop_double_to_long_done
4038
4039/* ------------------------------ */
4040 .balign 128
4041.L_op_double_to_float: /* 0x8c */
4042/* File: mips64/op_double_to_float.S */
4043 /*
4044 * Conversion from or to floating-point happens in a floating-point register.
4045 * Therefore we load the input and store the output into or from a
4046 * floating-point register irrespective of the type.
4047 */
4048/* File: mips64/fcvtHeader.S */
4049 /*
4050 * Loads a specified register from vB. Used primarily for conversions
4051 * from or to a floating-point type.
4052 *
4053 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to
4054 * store the result in vA and jump to the next instruction.
4055 *
4056 * For: int-to-float, int-to-double, long-to-float, long-to-double,
4057 * float-to-int, float-to-long, float-to-double, double-to-int,
4058 * double-to-long, double-to-float, neg-float, neg-double.
4059 */
4060 ext a1, rINST, 8, 4 # a1 <- A
4061 srl a2, rINST, 12 # a2 <- B
4062 GET_VREG_DOUBLE f0, a2
4063 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
4064
4065 cvt.s.d f0, f0
4066/* File: mips64/fcvtFooter.S */
4067 /*
4068 * Stores a specified register containing the result of conversion
4069 * from or to a floating-point type and jumps to the next instruction.
4070 *
4071 * Expects a1 to contain the destination Dalvik register number.
4072 * a1 is set up by fcvtHeader.S.
4073 *
4074 * For: int-to-float, int-to-double, long-to-float, long-to-double,
4075 * float-to-int, float-to-long, float-to-double, double-to-int,
4076 * double-to-long, double-to-float, neg-float, neg-double.
4077 *
4078 * Note that this file can't be included after a break in other files
4079 * and in those files its contents appear as a copy.
4080 * See: float-to-int, float-to-long, double-to-int, double-to-long.
4081 */
4082 GET_INST_OPCODE v0 # extract opcode from rINST
4083 SET_VREG_FLOAT f0, a1
4084 GOTO_OPCODE v0 # jump to next instruction
4085
4086
4087/* ------------------------------ */
4088 .balign 128
4089.L_op_int_to_byte: /* 0x8d */
4090/* File: mips64/op_int_to_byte.S */
4091/* File: mips64/unop.S */
4092 /*
4093 * Generic 32-bit unary operation. Provide an "instr" line that
4094 * specifies an instruction that performs "a0 = op a0".
4095 *
4096 * for: int-to-byte, int-to-char, int-to-short,
4097 * not-int, neg-int
4098 */
4099 /* unop vA, vB */
4100 ext a3, rINST, 12, 4 # a3 <- B
4101 GET_VREG a0, a3 # a0 <- vB
4102 ext a2, rINST, 8, 4 # a2 <- A
4103 # optional op
4104 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
4105 seb a0, a0 # a0 <- op, a0-a3 changed
4106 GET_INST_OPCODE v0 # extract opcode from rINST
4107 SET_VREG a0, a2 # vA <- a0
4108 GOTO_OPCODE v0 # jump to next instruction
4109
4110
4111/* ------------------------------ */
4112 .balign 128
4113.L_op_int_to_char: /* 0x8e */
4114/* File: mips64/op_int_to_char.S */
4115/* File: mips64/unop.S */
4116 /*
4117 * Generic 32-bit unary operation. Provide an "instr" line that
4118 * specifies an instruction that performs "a0 = op a0".
4119 *
4120 * for: int-to-byte, int-to-char, int-to-short,
4121 * not-int, neg-int
4122 */
4123 /* unop vA, vB */
4124 ext a3, rINST, 12, 4 # a3 <- B
4125 GET_VREG a0, a3 # a0 <- vB
4126 ext a2, rINST, 8, 4 # a2 <- A
4127 # optional op
4128 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
4129 and a0, a0, 0xffff # a0 <- op, a0-a3 changed
4130 GET_INST_OPCODE v0 # extract opcode from rINST
4131 SET_VREG a0, a2 # vA <- a0
4132 GOTO_OPCODE v0 # jump to next instruction
4133
4134
4135/* ------------------------------ */
4136 .balign 128
4137.L_op_int_to_short: /* 0x8f */
4138/* File: mips64/op_int_to_short.S */
4139/* File: mips64/unop.S */
4140 /*
4141 * Generic 32-bit unary operation. Provide an "instr" line that
4142 * specifies an instruction that performs "a0 = op a0".
4143 *
4144 * for: int-to-byte, int-to-char, int-to-short,
4145 * not-int, neg-int
4146 */
4147 /* unop vA, vB */
4148 ext a3, rINST, 12, 4 # a3 <- B
4149 GET_VREG a0, a3 # a0 <- vB
4150 ext a2, rINST, 8, 4 # a2 <- A
4151 # optional op
4152 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
4153 seh a0, a0 # a0 <- op, a0-a3 changed
4154 GET_INST_OPCODE v0 # extract opcode from rINST
4155 SET_VREG a0, a2 # vA <- a0
4156 GOTO_OPCODE v0 # jump to next instruction
4157
4158
4159/* ------------------------------ */
4160 .balign 128
4161.L_op_add_int: /* 0x90 */
4162/* File: mips64/op_add_int.S */
4163/* File: mips64/binop.S */
4164 /*
4165 * Generic 32-bit binary operation. Provide an "instr" line that
4166 * specifies an instruction that performs "result = a0 op a1".
4167 * This could be a MIPS instruction or a function call. (If the result
4168 * comes back in a register other than a0, you can override "result".)
4169 *
4170 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4171 * vCC (a1). Useful for integer division and modulus. Note that we
4172 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4173 * correctly.
4174 *
4175 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4176 * xor-int, shl-int, shr-int, ushr-int
4177 */
4178 /* binop vAA, vBB, vCC */
4179 srl a4, rINST, 8 # a4 <- AA
4180 lbu a2, 2(rPC) # a2 <- BB
4181 lbu a3, 3(rPC) # a3 <- CC
4182 GET_VREG a0, a2 # a0 <- vBB
4183 GET_VREG a1, a3 # a1 <- vCC
4184 .if 0
4185 beqz a1, common_errDivideByZero # is second operand zero?
4186 .endif
4187 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4188 # optional op
4189 addu a0, a0, a1 # a0 <- op, a0-a3 changed
4190 GET_INST_OPCODE v0 # extract opcode from rINST
4191 SET_VREG a0, a4 # vAA <- a0
4192 GOTO_OPCODE v0 # jump to next instruction
4193
4194
4195/* ------------------------------ */
4196 .balign 128
4197.L_op_sub_int: /* 0x91 */
4198/* File: mips64/op_sub_int.S */
4199/* File: mips64/binop.S */
4200 /*
4201 * Generic 32-bit binary operation. Provide an "instr" line that
4202 * specifies an instruction that performs "result = a0 op a1".
4203 * This could be a MIPS instruction or a function call. (If the result
4204 * comes back in a register other than a0, you can override "result".)
4205 *
4206 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4207 * vCC (a1). Useful for integer division and modulus. Note that we
4208 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4209 * correctly.
4210 *
4211 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4212 * xor-int, shl-int, shr-int, ushr-int
4213 */
4214 /* binop vAA, vBB, vCC */
4215 srl a4, rINST, 8 # a4 <- AA
4216 lbu a2, 2(rPC) # a2 <- BB
4217 lbu a3, 3(rPC) # a3 <- CC
4218 GET_VREG a0, a2 # a0 <- vBB
4219 GET_VREG a1, a3 # a1 <- vCC
4220 .if 0
4221 beqz a1, common_errDivideByZero # is second operand zero?
4222 .endif
4223 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4224 # optional op
4225 subu a0, a0, a1 # a0 <- op, a0-a3 changed
4226 GET_INST_OPCODE v0 # extract opcode from rINST
4227 SET_VREG a0, a4 # vAA <- a0
4228 GOTO_OPCODE v0 # jump to next instruction
4229
4230
4231/* ------------------------------ */
4232 .balign 128
4233.L_op_mul_int: /* 0x92 */
4234/* File: mips64/op_mul_int.S */
4235/* File: mips64/binop.S */
4236 /*
4237 * Generic 32-bit binary operation. Provide an "instr" line that
4238 * specifies an instruction that performs "result = a0 op a1".
4239 * This could be a MIPS instruction or a function call. (If the result
4240 * comes back in a register other than a0, you can override "result".)
4241 *
4242 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4243 * vCC (a1). Useful for integer division and modulus. Note that we
4244 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4245 * correctly.
4246 *
4247 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4248 * xor-int, shl-int, shr-int, ushr-int
4249 */
4250 /* binop vAA, vBB, vCC */
4251 srl a4, rINST, 8 # a4 <- AA
4252 lbu a2, 2(rPC) # a2 <- BB
4253 lbu a3, 3(rPC) # a3 <- CC
4254 GET_VREG a0, a2 # a0 <- vBB
4255 GET_VREG a1, a3 # a1 <- vCC
4256 .if 0
4257 beqz a1, common_errDivideByZero # is second operand zero?
4258 .endif
4259 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4260 # optional op
4261 mul a0, a0, a1 # a0 <- op, a0-a3 changed
4262 GET_INST_OPCODE v0 # extract opcode from rINST
4263 SET_VREG a0, a4 # vAA <- a0
4264 GOTO_OPCODE v0 # jump to next instruction
4265
4266
4267/* ------------------------------ */
4268 .balign 128
4269.L_op_div_int: /* 0x93 */
4270/* File: mips64/op_div_int.S */
4271/* File: mips64/binop.S */
4272 /*
4273 * Generic 32-bit binary operation. Provide an "instr" line that
4274 * specifies an instruction that performs "result = a0 op a1".
4275 * This could be a MIPS instruction or a function call. (If the result
4276 * comes back in a register other than a0, you can override "result".)
4277 *
4278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4279 * vCC (a1). Useful for integer division and modulus. Note that we
4280 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4281 * correctly.
4282 *
4283 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4284 * xor-int, shl-int, shr-int, ushr-int
4285 */
4286 /* binop vAA, vBB, vCC */
4287 srl a4, rINST, 8 # a4 <- AA
4288 lbu a2, 2(rPC) # a2 <- BB
4289 lbu a3, 3(rPC) # a3 <- CC
4290 GET_VREG a0, a2 # a0 <- vBB
4291 GET_VREG a1, a3 # a1 <- vCC
4292 .if 1
4293 beqz a1, common_errDivideByZero # is second operand zero?
4294 .endif
4295 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4296 # optional op
4297 div a0, a0, a1 # a0 <- op, a0-a3 changed
4298 GET_INST_OPCODE v0 # extract opcode from rINST
4299 SET_VREG a0, a4 # vAA <- a0
4300 GOTO_OPCODE v0 # jump to next instruction
4301
4302
4303/* ------------------------------ */
4304 .balign 128
4305.L_op_rem_int: /* 0x94 */
4306/* File: mips64/op_rem_int.S */
4307/* File: mips64/binop.S */
4308 /*
4309 * Generic 32-bit binary operation. Provide an "instr" line that
4310 * specifies an instruction that performs "result = a0 op a1".
4311 * This could be a MIPS instruction or a function call. (If the result
4312 * comes back in a register other than a0, you can override "result".)
4313 *
4314 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4315 * vCC (a1). Useful for integer division and modulus. Note that we
4316 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4317 * correctly.
4318 *
4319 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4320 * xor-int, shl-int, shr-int, ushr-int
4321 */
4322 /* binop vAA, vBB, vCC */
4323 srl a4, rINST, 8 # a4 <- AA
4324 lbu a2, 2(rPC) # a2 <- BB
4325 lbu a3, 3(rPC) # a3 <- CC
4326 GET_VREG a0, a2 # a0 <- vBB
4327 GET_VREG a1, a3 # a1 <- vCC
4328 .if 1
4329 beqz a1, common_errDivideByZero # is second operand zero?
4330 .endif
4331 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4332 # optional op
4333 mod a0, a0, a1 # a0 <- op, a0-a3 changed
4334 GET_INST_OPCODE v0 # extract opcode from rINST
4335 SET_VREG a0, a4 # vAA <- a0
4336 GOTO_OPCODE v0 # jump to next instruction
4337
4338
4339/* ------------------------------ */
4340 .balign 128
4341.L_op_and_int: /* 0x95 */
4342/* File: mips64/op_and_int.S */
4343/* File: mips64/binop.S */
4344 /*
4345 * Generic 32-bit binary operation. Provide an "instr" line that
4346 * specifies an instruction that performs "result = a0 op a1".
4347 * This could be a MIPS instruction or a function call. (If the result
4348 * comes back in a register other than a0, you can override "result".)
4349 *
4350 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4351 * vCC (a1). Useful for integer division and modulus. Note that we
4352 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4353 * correctly.
4354 *
4355 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4356 * xor-int, shl-int, shr-int, ushr-int
4357 */
4358 /* binop vAA, vBB, vCC */
4359 srl a4, rINST, 8 # a4 <- AA
4360 lbu a2, 2(rPC) # a2 <- BB
4361 lbu a3, 3(rPC) # a3 <- CC
4362 GET_VREG a0, a2 # a0 <- vBB
4363 GET_VREG a1, a3 # a1 <- vCC
4364 .if 0
4365 beqz a1, common_errDivideByZero # is second operand zero?
4366 .endif
4367 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4368 # optional op
4369 and a0, a0, a1 # a0 <- op, a0-a3 changed
4370 GET_INST_OPCODE v0 # extract opcode from rINST
4371 SET_VREG a0, a4 # vAA <- a0
4372 GOTO_OPCODE v0 # jump to next instruction
4373
4374
4375/* ------------------------------ */
4376 .balign 128
4377.L_op_or_int: /* 0x96 */
4378/* File: mips64/op_or_int.S */
4379/* File: mips64/binop.S */
4380 /*
4381 * Generic 32-bit binary operation. Provide an "instr" line that
4382 * specifies an instruction that performs "result = a0 op a1".
4383 * This could be a MIPS instruction or a function call. (If the result
4384 * comes back in a register other than a0, you can override "result".)
4385 *
4386 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4387 * vCC (a1). Useful for integer division and modulus. Note that we
4388 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4389 * correctly.
4390 *
4391 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4392 * xor-int, shl-int, shr-int, ushr-int
4393 */
4394 /* binop vAA, vBB, vCC */
4395 srl a4, rINST, 8 # a4 <- AA
4396 lbu a2, 2(rPC) # a2 <- BB
4397 lbu a3, 3(rPC) # a3 <- CC
4398 GET_VREG a0, a2 # a0 <- vBB
4399 GET_VREG a1, a3 # a1 <- vCC
4400 .if 0
4401 beqz a1, common_errDivideByZero # is second operand zero?
4402 .endif
4403 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4404 # optional op
4405 or a0, a0, a1 # a0 <- op, a0-a3 changed
4406 GET_INST_OPCODE v0 # extract opcode from rINST
4407 SET_VREG a0, a4 # vAA <- a0
4408 GOTO_OPCODE v0 # jump to next instruction
4409
4410
4411/* ------------------------------ */
4412 .balign 128
4413.L_op_xor_int: /* 0x97 */
4414/* File: mips64/op_xor_int.S */
4415/* File: mips64/binop.S */
4416 /*
4417 * Generic 32-bit binary operation. Provide an "instr" line that
4418 * specifies an instruction that performs "result = a0 op a1".
4419 * This could be a MIPS instruction or a function call. (If the result
4420 * comes back in a register other than a0, you can override "result".)
4421 *
4422 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4423 * vCC (a1). Useful for integer division and modulus. Note that we
4424 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4425 * correctly.
4426 *
4427 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4428 * xor-int, shl-int, shr-int, ushr-int
4429 */
4430 /* binop vAA, vBB, vCC */
4431 srl a4, rINST, 8 # a4 <- AA
4432 lbu a2, 2(rPC) # a2 <- BB
4433 lbu a3, 3(rPC) # a3 <- CC
4434 GET_VREG a0, a2 # a0 <- vBB
4435 GET_VREG a1, a3 # a1 <- vCC
4436 .if 0
4437 beqz a1, common_errDivideByZero # is second operand zero?
4438 .endif
4439 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4440 # optional op
4441 xor a0, a0, a1 # a0 <- op, a0-a3 changed
4442 GET_INST_OPCODE v0 # extract opcode from rINST
4443 SET_VREG a0, a4 # vAA <- a0
4444 GOTO_OPCODE v0 # jump to next instruction
4445
4446
4447/* ------------------------------ */
4448 .balign 128
4449.L_op_shl_int: /* 0x98 */
4450/* File: mips64/op_shl_int.S */
4451/* File: mips64/binop.S */
4452 /*
4453 * Generic 32-bit binary operation. Provide an "instr" line that
4454 * specifies an instruction that performs "result = a0 op a1".
4455 * This could be a MIPS instruction or a function call. (If the result
4456 * comes back in a register other than a0, you can override "result".)
4457 *
4458 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4459 * vCC (a1). Useful for integer division and modulus. Note that we
4460 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4461 * correctly.
4462 *
4463 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4464 * xor-int, shl-int, shr-int, ushr-int
4465 */
4466 /* binop vAA, vBB, vCC */
4467 srl a4, rINST, 8 # a4 <- AA
4468 lbu a2, 2(rPC) # a2 <- BB
4469 lbu a3, 3(rPC) # a3 <- CC
4470 GET_VREG a0, a2 # a0 <- vBB
4471 GET_VREG a1, a3 # a1 <- vCC
4472 .if 0
4473 beqz a1, common_errDivideByZero # is second operand zero?
4474 .endif
4475 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4476 # optional op
4477 sll a0, a0, a1 # a0 <- op, a0-a3 changed
4478 GET_INST_OPCODE v0 # extract opcode from rINST
4479 SET_VREG a0, a4 # vAA <- a0
4480 GOTO_OPCODE v0 # jump to next instruction
4481
4482
4483/* ------------------------------ */
4484 .balign 128
4485.L_op_shr_int: /* 0x99 */
4486/* File: mips64/op_shr_int.S */
4487/* File: mips64/binop.S */
4488 /*
4489 * Generic 32-bit binary operation. Provide an "instr" line that
4490 * specifies an instruction that performs "result = a0 op a1".
4491 * This could be a MIPS instruction or a function call. (If the result
4492 * comes back in a register other than a0, you can override "result".)
4493 *
4494 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4495 * vCC (a1). Useful for integer division and modulus. Note that we
4496 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4497 * correctly.
4498 *
4499 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4500 * xor-int, shl-int, shr-int, ushr-int
4501 */
4502 /* binop vAA, vBB, vCC */
4503 srl a4, rINST, 8 # a4 <- AA
4504 lbu a2, 2(rPC) # a2 <- BB
4505 lbu a3, 3(rPC) # a3 <- CC
4506 GET_VREG a0, a2 # a0 <- vBB
4507 GET_VREG a1, a3 # a1 <- vCC
4508 .if 0
4509 beqz a1, common_errDivideByZero # is second operand zero?
4510 .endif
4511 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4512 # optional op
4513 sra a0, a0, a1 # a0 <- op, a0-a3 changed
4514 GET_INST_OPCODE v0 # extract opcode from rINST
4515 SET_VREG a0, a4 # vAA <- a0
4516 GOTO_OPCODE v0 # jump to next instruction
4517
4518
4519/* ------------------------------ */
4520 .balign 128
4521.L_op_ushr_int: /* 0x9a */
4522/* File: mips64/op_ushr_int.S */
4523/* File: mips64/binop.S */
4524 /*
4525 * Generic 32-bit binary operation. Provide an "instr" line that
4526 * specifies an instruction that performs "result = a0 op a1".
4527 * This could be a MIPS instruction or a function call. (If the result
4528 * comes back in a register other than a0, you can override "result".)
4529 *
4530 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4531 * vCC (a1). Useful for integer division and modulus. Note that we
4532 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
4533 * correctly.
4534 *
4535 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4536 * xor-int, shl-int, shr-int, ushr-int
4537 */
4538 /* binop vAA, vBB, vCC */
4539 srl a4, rINST, 8 # a4 <- AA
4540 lbu a2, 2(rPC) # a2 <- BB
4541 lbu a3, 3(rPC) # a3 <- CC
4542 GET_VREG a0, a2 # a0 <- vBB
4543 GET_VREG a1, a3 # a1 <- vCC
4544 .if 0
4545 beqz a1, common_errDivideByZero # is second operand zero?
4546 .endif
4547 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4548 # optional op
4549 srl a0, a0, a1 # a0 <- op, a0-a3 changed
4550 GET_INST_OPCODE v0 # extract opcode from rINST
4551 SET_VREG a0, a4 # vAA <- a0
4552 GOTO_OPCODE v0 # jump to next instruction
4553
4554
4555/* ------------------------------ */
4556 .balign 128
4557.L_op_add_long: /* 0x9b */
4558/* File: mips64/op_add_long.S */
4559/* File: mips64/binopWide.S */
4560 /*
4561 * Generic 64-bit binary operation. Provide an "instr" line that
4562 * specifies an instruction that performs "result = a0 op a1".
4563 * This could be a MIPS instruction or a function call. (If the result
4564 * comes back in a register other than a0, you can override "result".)
4565 *
4566 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4567 * vCC (a1). Useful for integer division and modulus. Note that we
4568 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4569 * correctly.
4570 *
4571 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4572 * xor-long, shl-long, shr-long, ushr-long
4573 */
4574 /* binop vAA, vBB, vCC */
4575 srl a4, rINST, 8 # a4 <- AA
4576 lbu a2, 2(rPC) # a2 <- BB
4577 lbu a3, 3(rPC) # a3 <- CC
4578 GET_VREG_WIDE a0, a2 # a0 <- vBB
4579 GET_VREG_WIDE a1, a3 # a1 <- vCC
4580 .if 0
4581 beqz a1, common_errDivideByZero # is second operand zero?
4582 .endif
4583 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4584 # optional op
4585 daddu a0, a0, a1 # a0 <- op, a0-a3 changed
4586 GET_INST_OPCODE v0 # extract opcode from rINST
4587 SET_VREG_WIDE a0, a4 # vAA <- a0
4588 GOTO_OPCODE v0 # jump to next instruction
4589
4590
4591/* ------------------------------ */
4592 .balign 128
4593.L_op_sub_long: /* 0x9c */
4594/* File: mips64/op_sub_long.S */
4595/* File: mips64/binopWide.S */
4596 /*
4597 * Generic 64-bit binary operation. Provide an "instr" line that
4598 * specifies an instruction that performs "result = a0 op a1".
4599 * This could be a MIPS instruction or a function call. (If the result
4600 * comes back in a register other than a0, you can override "result".)
4601 *
4602 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4603 * vCC (a1). Useful for integer division and modulus. Note that we
4604 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4605 * correctly.
4606 *
4607 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4608 * xor-long, shl-long, shr-long, ushr-long
4609 */
4610 /* binop vAA, vBB, vCC */
4611 srl a4, rINST, 8 # a4 <- AA
4612 lbu a2, 2(rPC) # a2 <- BB
4613 lbu a3, 3(rPC) # a3 <- CC
4614 GET_VREG_WIDE a0, a2 # a0 <- vBB
4615 GET_VREG_WIDE a1, a3 # a1 <- vCC
4616 .if 0
4617 beqz a1, common_errDivideByZero # is second operand zero?
4618 .endif
4619 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4620 # optional op
4621 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed
4622 GET_INST_OPCODE v0 # extract opcode from rINST
4623 SET_VREG_WIDE a0, a4 # vAA <- a0
4624 GOTO_OPCODE v0 # jump to next instruction
4625
4626
4627/* ------------------------------ */
4628 .balign 128
4629.L_op_mul_long: /* 0x9d */
4630/* File: mips64/op_mul_long.S */
4631/* File: mips64/binopWide.S */
4632 /*
4633 * Generic 64-bit binary operation. Provide an "instr" line that
4634 * specifies an instruction that performs "result = a0 op a1".
4635 * This could be a MIPS instruction or a function call. (If the result
4636 * comes back in a register other than a0, you can override "result".)
4637 *
4638 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4639 * vCC (a1). Useful for integer division and modulus. Note that we
4640 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4641 * correctly.
4642 *
4643 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4644 * xor-long, shl-long, shr-long, ushr-long
4645 */
4646 /* binop vAA, vBB, vCC */
4647 srl a4, rINST, 8 # a4 <- AA
4648 lbu a2, 2(rPC) # a2 <- BB
4649 lbu a3, 3(rPC) # a3 <- CC
4650 GET_VREG_WIDE a0, a2 # a0 <- vBB
4651 GET_VREG_WIDE a1, a3 # a1 <- vCC
4652 .if 0
4653 beqz a1, common_errDivideByZero # is second operand zero?
4654 .endif
4655 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4656 # optional op
4657 dmul a0, a0, a1 # a0 <- op, a0-a3 changed
4658 GET_INST_OPCODE v0 # extract opcode from rINST
4659 SET_VREG_WIDE a0, a4 # vAA <- a0
4660 GOTO_OPCODE v0 # jump to next instruction
4661
4662
4663/* ------------------------------ */
4664 .balign 128
4665.L_op_div_long: /* 0x9e */
4666/* File: mips64/op_div_long.S */
4667/* File: mips64/binopWide.S */
4668 /*
4669 * Generic 64-bit binary operation. Provide an "instr" line that
4670 * specifies an instruction that performs "result = a0 op a1".
4671 * This could be a MIPS instruction or a function call. (If the result
4672 * comes back in a register other than a0, you can override "result".)
4673 *
4674 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4675 * vCC (a1). Useful for integer division and modulus. Note that we
4676 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4677 * correctly.
4678 *
4679 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4680 * xor-long, shl-long, shr-long, ushr-long
4681 */
4682 /* binop vAA, vBB, vCC */
4683 srl a4, rINST, 8 # a4 <- AA
4684 lbu a2, 2(rPC) # a2 <- BB
4685 lbu a3, 3(rPC) # a3 <- CC
4686 GET_VREG_WIDE a0, a2 # a0 <- vBB
4687 GET_VREG_WIDE a1, a3 # a1 <- vCC
4688 .if 1
4689 beqz a1, common_errDivideByZero # is second operand zero?
4690 .endif
4691 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4692 # optional op
4693 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed
4694 GET_INST_OPCODE v0 # extract opcode from rINST
4695 SET_VREG_WIDE a0, a4 # vAA <- a0
4696 GOTO_OPCODE v0 # jump to next instruction
4697
4698
4699/* ------------------------------ */
4700 .balign 128
4701.L_op_rem_long: /* 0x9f */
4702/* File: mips64/op_rem_long.S */
4703/* File: mips64/binopWide.S */
4704 /*
4705 * Generic 64-bit binary operation. Provide an "instr" line that
4706 * specifies an instruction that performs "result = a0 op a1".
4707 * This could be a MIPS instruction or a function call. (If the result
4708 * comes back in a register other than a0, you can override "result".)
4709 *
4710 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4711 * vCC (a1). Useful for integer division and modulus. Note that we
4712 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4713 * correctly.
4714 *
4715 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4716 * xor-long, shl-long, shr-long, ushr-long
4717 */
4718 /* binop vAA, vBB, vCC */
4719 srl a4, rINST, 8 # a4 <- AA
4720 lbu a2, 2(rPC) # a2 <- BB
4721 lbu a3, 3(rPC) # a3 <- CC
4722 GET_VREG_WIDE a0, a2 # a0 <- vBB
4723 GET_VREG_WIDE a1, a3 # a1 <- vCC
4724 .if 1
4725 beqz a1, common_errDivideByZero # is second operand zero?
4726 .endif
4727 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4728 # optional op
4729 dmod a0, a0, a1 # a0 <- op, a0-a3 changed
4730 GET_INST_OPCODE v0 # extract opcode from rINST
4731 SET_VREG_WIDE a0, a4 # vAA <- a0
4732 GOTO_OPCODE v0 # jump to next instruction
4733
4734
4735/* ------------------------------ */
4736 .balign 128
4737.L_op_and_long: /* 0xa0 */
4738/* File: mips64/op_and_long.S */
4739/* File: mips64/binopWide.S */
4740 /*
4741 * Generic 64-bit binary operation. Provide an "instr" line that
4742 * specifies an instruction that performs "result = a0 op a1".
4743 * This could be a MIPS instruction or a function call. (If the result
4744 * comes back in a register other than a0, you can override "result".)
4745 *
4746 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4747 * vCC (a1). Useful for integer division and modulus. Note that we
4748 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4749 * correctly.
4750 *
4751 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4752 * xor-long, shl-long, shr-long, ushr-long
4753 */
4754 /* binop vAA, vBB, vCC */
4755 srl a4, rINST, 8 # a4 <- AA
4756 lbu a2, 2(rPC) # a2 <- BB
4757 lbu a3, 3(rPC) # a3 <- CC
4758 GET_VREG_WIDE a0, a2 # a0 <- vBB
4759 GET_VREG_WIDE a1, a3 # a1 <- vCC
4760 .if 0
4761 beqz a1, common_errDivideByZero # is second operand zero?
4762 .endif
4763 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4764 # optional op
4765 and a0, a0, a1 # a0 <- op, a0-a3 changed
4766 GET_INST_OPCODE v0 # extract opcode from rINST
4767 SET_VREG_WIDE a0, a4 # vAA <- a0
4768 GOTO_OPCODE v0 # jump to next instruction
4769
4770
4771/* ------------------------------ */
4772 .balign 128
4773.L_op_or_long: /* 0xa1 */
4774/* File: mips64/op_or_long.S */
4775/* File: mips64/binopWide.S */
4776 /*
4777 * Generic 64-bit binary operation. Provide an "instr" line that
4778 * specifies an instruction that performs "result = a0 op a1".
4779 * This could be a MIPS instruction or a function call. (If the result
4780 * comes back in a register other than a0, you can override "result".)
4781 *
4782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4783 * vCC (a1). Useful for integer division and modulus. Note that we
4784 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4785 * correctly.
4786 *
4787 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4788 * xor-long, shl-long, shr-long, ushr-long
4789 */
4790 /* binop vAA, vBB, vCC */
4791 srl a4, rINST, 8 # a4 <- AA
4792 lbu a2, 2(rPC) # a2 <- BB
4793 lbu a3, 3(rPC) # a3 <- CC
4794 GET_VREG_WIDE a0, a2 # a0 <- vBB
4795 GET_VREG_WIDE a1, a3 # a1 <- vCC
4796 .if 0
4797 beqz a1, common_errDivideByZero # is second operand zero?
4798 .endif
4799 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4800 # optional op
4801 or a0, a0, a1 # a0 <- op, a0-a3 changed
4802 GET_INST_OPCODE v0 # extract opcode from rINST
4803 SET_VREG_WIDE a0, a4 # vAA <- a0
4804 GOTO_OPCODE v0 # jump to next instruction
4805
4806
4807/* ------------------------------ */
4808 .balign 128
4809.L_op_xor_long: /* 0xa2 */
4810/* File: mips64/op_xor_long.S */
4811/* File: mips64/binopWide.S */
4812 /*
4813 * Generic 64-bit binary operation. Provide an "instr" line that
4814 * specifies an instruction that performs "result = a0 op a1".
4815 * This could be a MIPS instruction or a function call. (If the result
4816 * comes back in a register other than a0, you can override "result".)
4817 *
4818 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4819 * vCC (a1). Useful for integer division and modulus. Note that we
4820 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4821 * correctly.
4822 *
4823 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4824 * xor-long, shl-long, shr-long, ushr-long
4825 */
4826 /* binop vAA, vBB, vCC */
4827 srl a4, rINST, 8 # a4 <- AA
4828 lbu a2, 2(rPC) # a2 <- BB
4829 lbu a3, 3(rPC) # a3 <- CC
4830 GET_VREG_WIDE a0, a2 # a0 <- vBB
4831 GET_VREG_WIDE a1, a3 # a1 <- vCC
4832 .if 0
4833 beqz a1, common_errDivideByZero # is second operand zero?
4834 .endif
4835 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4836 # optional op
4837 xor a0, a0, a1 # a0 <- op, a0-a3 changed
4838 GET_INST_OPCODE v0 # extract opcode from rINST
4839 SET_VREG_WIDE a0, a4 # vAA <- a0
4840 GOTO_OPCODE v0 # jump to next instruction
4841
4842
4843/* ------------------------------ */
4844 .balign 128
4845.L_op_shl_long: /* 0xa3 */
4846/* File: mips64/op_shl_long.S */
4847/* File: mips64/binopWide.S */
4848 /*
4849 * Generic 64-bit binary operation. Provide an "instr" line that
4850 * specifies an instruction that performs "result = a0 op a1".
4851 * This could be a MIPS instruction or a function call. (If the result
4852 * comes back in a register other than a0, you can override "result".)
4853 *
4854 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4855 * vCC (a1). Useful for integer division and modulus. Note that we
4856 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4857 * correctly.
4858 *
4859 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4860 * xor-long, shl-long, shr-long, ushr-long
4861 */
4862 /* binop vAA, vBB, vCC */
4863 srl a4, rINST, 8 # a4 <- AA
4864 lbu a2, 2(rPC) # a2 <- BB
4865 lbu a3, 3(rPC) # a3 <- CC
4866 GET_VREG_WIDE a0, a2 # a0 <- vBB
4867 GET_VREG_WIDE a1, a3 # a1 <- vCC
4868 .if 0
4869 beqz a1, common_errDivideByZero # is second operand zero?
4870 .endif
4871 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4872 # optional op
4873 dsll a0, a0, a1 # a0 <- op, a0-a3 changed
4874 GET_INST_OPCODE v0 # extract opcode from rINST
4875 SET_VREG_WIDE a0, a4 # vAA <- a0
4876 GOTO_OPCODE v0 # jump to next instruction
4877
4878
4879/* ------------------------------ */
4880 .balign 128
4881.L_op_shr_long: /* 0xa4 */
4882/* File: mips64/op_shr_long.S */
4883/* File: mips64/binopWide.S */
4884 /*
4885 * Generic 64-bit binary operation. Provide an "instr" line that
4886 * specifies an instruction that performs "result = a0 op a1".
4887 * This could be a MIPS instruction or a function call. (If the result
4888 * comes back in a register other than a0, you can override "result".)
4889 *
4890 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4891 * vCC (a1). Useful for integer division and modulus. Note that we
4892 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4893 * correctly.
4894 *
4895 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4896 * xor-long, shl-long, shr-long, ushr-long
4897 */
4898 /* binop vAA, vBB, vCC */
4899 srl a4, rINST, 8 # a4 <- AA
4900 lbu a2, 2(rPC) # a2 <- BB
4901 lbu a3, 3(rPC) # a3 <- CC
4902 GET_VREG_WIDE a0, a2 # a0 <- vBB
4903 GET_VREG_WIDE a1, a3 # a1 <- vCC
4904 .if 0
4905 beqz a1, common_errDivideByZero # is second operand zero?
4906 .endif
4907 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4908 # optional op
4909 dsra a0, a0, a1 # a0 <- op, a0-a3 changed
4910 GET_INST_OPCODE v0 # extract opcode from rINST
4911 SET_VREG_WIDE a0, a4 # vAA <- a0
4912 GOTO_OPCODE v0 # jump to next instruction
4913
4914
4915/* ------------------------------ */
4916 .balign 128
4917.L_op_ushr_long: /* 0xa5 */
4918/* File: mips64/op_ushr_long.S */
4919/* File: mips64/binopWide.S */
4920 /*
4921 * Generic 64-bit binary operation. Provide an "instr" line that
4922 * specifies an instruction that performs "result = a0 op a1".
4923 * This could be a MIPS instruction or a function call. (If the result
4924 * comes back in a register other than a0, you can override "result".)
4925 *
4926 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4927 * vCC (a1). Useful for integer division and modulus. Note that we
4928 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
4929 * correctly.
4930 *
4931 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long,
4932 * xor-long, shl-long, shr-long, ushr-long
4933 */
4934 /* binop vAA, vBB, vCC */
4935 srl a4, rINST, 8 # a4 <- AA
4936 lbu a2, 2(rPC) # a2 <- BB
4937 lbu a3, 3(rPC) # a3 <- CC
4938 GET_VREG_WIDE a0, a2 # a0 <- vBB
4939 GET_VREG_WIDE a1, a3 # a1 <- vCC
4940 .if 0
4941 beqz a1, common_errDivideByZero # is second operand zero?
4942 .endif
4943 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4944 # optional op
4945 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed
4946 GET_INST_OPCODE v0 # extract opcode from rINST
4947 SET_VREG_WIDE a0, a4 # vAA <- a0
4948 GOTO_OPCODE v0 # jump to next instruction
4949
4950
4951/* ------------------------------ */
4952 .balign 128
4953.L_op_add_float: /* 0xa6 */
4954/* File: mips64/op_add_float.S */
4955/* File: mips64/fbinop.S */
4956 /*:
4957 * Generic 32-bit floating-point operation.
4958 *
4959 * For: add-float, sub-float, mul-float, div-float.
4960 * form: <op> f0, f0, f1
4961 */
4962 /* binop vAA, vBB, vCC */
4963 srl a4, rINST, 8 # a4 <- AA
4964 lbu a2, 2(rPC) # a2 <- BB
4965 lbu a3, 3(rPC) # a3 <- CC
4966 GET_VREG_FLOAT f0, a2 # f0 <- vBB
4967 GET_VREG_FLOAT f1, a3 # f1 <- vCC
4968 add.s f0, f0, f1 # f0 <- f0 op f1
4969 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4970 GET_INST_OPCODE v0 # extract opcode from rINST
4971 SET_VREG_FLOAT f0, a4 # vAA <- f0
4972 GOTO_OPCODE v0 # jump to next instruction
4973
4974
4975/* ------------------------------ */
4976 .balign 128
4977.L_op_sub_float: /* 0xa7 */
4978/* File: mips64/op_sub_float.S */
4979/* File: mips64/fbinop.S */
4980 /*:
4981 * Generic 32-bit floating-point operation.
4982 *
4983 * For: add-float, sub-float, mul-float, div-float.
4984 * form: <op> f0, f0, f1
4985 */
4986 /* binop vAA, vBB, vCC */
4987 srl a4, rINST, 8 # a4 <- AA
4988 lbu a2, 2(rPC) # a2 <- BB
4989 lbu a3, 3(rPC) # a3 <- CC
4990 GET_VREG_FLOAT f0, a2 # f0 <- vBB
4991 GET_VREG_FLOAT f1, a3 # f1 <- vCC
4992 sub.s f0, f0, f1 # f0 <- f0 op f1
4993 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
4994 GET_INST_OPCODE v0 # extract opcode from rINST
4995 SET_VREG_FLOAT f0, a4 # vAA <- f0
4996 GOTO_OPCODE v0 # jump to next instruction
4997
4998
4999/* ------------------------------ */
5000 .balign 128
5001.L_op_mul_float: /* 0xa8 */
5002/* File: mips64/op_mul_float.S */
5003/* File: mips64/fbinop.S */
5004 /*:
5005 * Generic 32-bit floating-point operation.
5006 *
5007 * For: add-float, sub-float, mul-float, div-float.
5008 * form: <op> f0, f0, f1
5009 */
5010 /* binop vAA, vBB, vCC */
5011 srl a4, rINST, 8 # a4 <- AA
5012 lbu a2, 2(rPC) # a2 <- BB
5013 lbu a3, 3(rPC) # a3 <- CC
5014 GET_VREG_FLOAT f0, a2 # f0 <- vBB
5015 GET_VREG_FLOAT f1, a3 # f1 <- vCC
5016 mul.s f0, f0, f1 # f0 <- f0 op f1
5017 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5018 GET_INST_OPCODE v0 # extract opcode from rINST
5019 SET_VREG_FLOAT f0, a4 # vAA <- f0
5020 GOTO_OPCODE v0 # jump to next instruction
5021
5022
5023/* ------------------------------ */
5024 .balign 128
5025.L_op_div_float: /* 0xa9 */
5026/* File: mips64/op_div_float.S */
5027/* File: mips64/fbinop.S */
5028 /*:
5029 * Generic 32-bit floating-point operation.
5030 *
5031 * For: add-float, sub-float, mul-float, div-float.
5032 * form: <op> f0, f0, f1
5033 */
5034 /* binop vAA, vBB, vCC */
5035 srl a4, rINST, 8 # a4 <- AA
5036 lbu a2, 2(rPC) # a2 <- BB
5037 lbu a3, 3(rPC) # a3 <- CC
5038 GET_VREG_FLOAT f0, a2 # f0 <- vBB
5039 GET_VREG_FLOAT f1, a3 # f1 <- vCC
5040 div.s f0, f0, f1 # f0 <- f0 op f1
5041 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5042 GET_INST_OPCODE v0 # extract opcode from rINST
5043 SET_VREG_FLOAT f0, a4 # vAA <- f0
5044 GOTO_OPCODE v0 # jump to next instruction
5045
5046
5047/* ------------------------------ */
5048 .balign 128
5049.L_op_rem_float: /* 0xaa */
5050/* File: mips64/op_rem_float.S */
5051 /* rem-float vAA, vBB, vCC */
5052 .extern fmodf
5053 lbu a2, 2(rPC) # a2 <- BB
5054 lbu a3, 3(rPC) # a3 <- CC
5055 GET_VREG_FLOAT f12, a2 # f12 <- vBB
5056 GET_VREG_FLOAT f13, a3 # f13 <- vCC
5057 jal fmodf # f0 <- f12 op f13
5058 srl a4, rINST, 8 # a4 <- AA
5059 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5060 GET_INST_OPCODE v0 # extract opcode from rINST
5061 SET_VREG_FLOAT f0, a4 # vAA <- f0
5062 GOTO_OPCODE v0 # jump to next instruction
5063
5064/* ------------------------------ */
5065 .balign 128
5066.L_op_add_double: /* 0xab */
5067/* File: mips64/op_add_double.S */
5068/* File: mips64/fbinopWide.S */
5069 /*:
5070 * Generic 64-bit floating-point operation.
5071 *
5072 * For: add-double, sub-double, mul-double, div-double.
5073 * form: <op> f0, f0, f1
5074 */
5075 /* binop vAA, vBB, vCC */
5076 srl a4, rINST, 8 # a4 <- AA
5077 lbu a2, 2(rPC) # a2 <- BB
5078 lbu a3, 3(rPC) # a3 <- CC
5079 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
5080 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
5081 add.d f0, f0, f1 # f0 <- f0 op f1
5082 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5083 GET_INST_OPCODE v0 # extract opcode from rINST
5084 SET_VREG_DOUBLE f0, a4 # vAA <- f0
5085 GOTO_OPCODE v0 # jump to next instruction
5086
5087
5088/* ------------------------------ */
5089 .balign 128
5090.L_op_sub_double: /* 0xac */
5091/* File: mips64/op_sub_double.S */
5092/* File: mips64/fbinopWide.S */
5093 /*:
5094 * Generic 64-bit floating-point operation.
5095 *
5096 * For: add-double, sub-double, mul-double, div-double.
5097 * form: <op> f0, f0, f1
5098 */
5099 /* binop vAA, vBB, vCC */
5100 srl a4, rINST, 8 # a4 <- AA
5101 lbu a2, 2(rPC) # a2 <- BB
5102 lbu a3, 3(rPC) # a3 <- CC
5103 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
5104 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
5105 sub.d f0, f0, f1 # f0 <- f0 op f1
5106 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5107 GET_INST_OPCODE v0 # extract opcode from rINST
5108 SET_VREG_DOUBLE f0, a4 # vAA <- f0
5109 GOTO_OPCODE v0 # jump to next instruction
5110
5111
5112/* ------------------------------ */
5113 .balign 128
5114.L_op_mul_double: /* 0xad */
5115/* File: mips64/op_mul_double.S */
5116/* File: mips64/fbinopWide.S */
5117 /*:
5118 * Generic 64-bit floating-point operation.
5119 *
5120 * For: add-double, sub-double, mul-double, div-double.
5121 * form: <op> f0, f0, f1
5122 */
5123 /* binop vAA, vBB, vCC */
5124 srl a4, rINST, 8 # a4 <- AA
5125 lbu a2, 2(rPC) # a2 <- BB
5126 lbu a3, 3(rPC) # a3 <- CC
5127 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
5128 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
5129 mul.d f0, f0, f1 # f0 <- f0 op f1
5130 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5131 GET_INST_OPCODE v0 # extract opcode from rINST
5132 SET_VREG_DOUBLE f0, a4 # vAA <- f0
5133 GOTO_OPCODE v0 # jump to next instruction
5134
5135
5136/* ------------------------------ */
5137 .balign 128
5138.L_op_div_double: /* 0xae */
5139/* File: mips64/op_div_double.S */
5140/* File: mips64/fbinopWide.S */
5141 /*:
5142 * Generic 64-bit floating-point operation.
5143 *
5144 * For: add-double, sub-double, mul-double, div-double.
5145 * form: <op> f0, f0, f1
5146 */
5147 /* binop vAA, vBB, vCC */
5148 srl a4, rINST, 8 # a4 <- AA
5149 lbu a2, 2(rPC) # a2 <- BB
5150 lbu a3, 3(rPC) # a3 <- CC
5151 GET_VREG_DOUBLE f0, a2 # f0 <- vBB
5152 GET_VREG_DOUBLE f1, a3 # f1 <- vCC
5153 div.d f0, f0, f1 # f0 <- f0 op f1
5154 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5155 GET_INST_OPCODE v0 # extract opcode from rINST
5156 SET_VREG_DOUBLE f0, a4 # vAA <- f0
5157 GOTO_OPCODE v0 # jump to next instruction
5158
5159
5160/* ------------------------------ */
5161 .balign 128
5162.L_op_rem_double: /* 0xaf */
5163/* File: mips64/op_rem_double.S */
5164 /* rem-double vAA, vBB, vCC */
5165 .extern fmod
5166 lbu a2, 2(rPC) # a2 <- BB
5167 lbu a3, 3(rPC) # a3 <- CC
5168 GET_VREG_DOUBLE f12, a2 # f12 <- vBB
5169 GET_VREG_DOUBLE f13, a3 # f13 <- vCC
5170 jal fmod # f0 <- f12 op f13
5171 srl a4, rINST, 8 # a4 <- AA
5172 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
5173 GET_INST_OPCODE v0 # extract opcode from rINST
5174 SET_VREG_DOUBLE f0, a4 # vAA <- f0
5175 GOTO_OPCODE v0 # jump to next instruction
5176
5177/* ------------------------------ */
5178 .balign 128
5179.L_op_add_int_2addr: /* 0xb0 */
5180/* File: mips64/op_add_int_2addr.S */
5181/* File: mips64/binop2addr.S */
5182 /*
5183 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5184 * that specifies an instruction that performs "result = a0 op a1".
5185 * This could be a MIPS instruction or a function call. (If the result
5186 * comes back in a register other than a0, you can override "result".)
5187 *
5188 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5189 * vB (a1). Useful for integer division and modulus. Note that we
5190 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5191 * correctly.
5192 *
5193 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5194 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5195 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5196 */
5197 /* binop/2addr vA, vB */
5198 ext a2, rINST, 8, 4 # a2 <- A
5199 ext a3, rINST, 12, 4 # a3 <- B
5200 GET_VREG a0, a2 # a0 <- vA
5201 GET_VREG a1, a3 # a1 <- vB
5202 .if 0
5203 beqz a1, common_errDivideByZero # is second operand zero?
5204 .endif
5205 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5206 # optional op
5207 addu a0, a0, a1 # a0 <- op, a0-a3 changed
5208 GET_INST_OPCODE v0 # extract opcode from rINST
5209 SET_VREG a0, a2 # vA <- a0
5210 GOTO_OPCODE v0 # jump to next instruction
5211
5212
5213/* ------------------------------ */
5214 .balign 128
5215.L_op_sub_int_2addr: /* 0xb1 */
5216/* File: mips64/op_sub_int_2addr.S */
5217/* File: mips64/binop2addr.S */
5218 /*
5219 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5220 * that specifies an instruction that performs "result = a0 op a1".
5221 * This could be a MIPS instruction or a function call. (If the result
5222 * comes back in a register other than a0, you can override "result".)
5223 *
5224 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5225 * vB (a1). Useful for integer division and modulus. Note that we
5226 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5227 * correctly.
5228 *
5229 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5230 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5231 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5232 */
5233 /* binop/2addr vA, vB */
5234 ext a2, rINST, 8, 4 # a2 <- A
5235 ext a3, rINST, 12, 4 # a3 <- B
5236 GET_VREG a0, a2 # a0 <- vA
5237 GET_VREG a1, a3 # a1 <- vB
5238 .if 0
5239 beqz a1, common_errDivideByZero # is second operand zero?
5240 .endif
5241 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5242 # optional op
5243 subu a0, a0, a1 # a0 <- op, a0-a3 changed
5244 GET_INST_OPCODE v0 # extract opcode from rINST
5245 SET_VREG a0, a2 # vA <- a0
5246 GOTO_OPCODE v0 # jump to next instruction
5247
5248
5249/* ------------------------------ */
5250 .balign 128
5251.L_op_mul_int_2addr: /* 0xb2 */
5252/* File: mips64/op_mul_int_2addr.S */
5253/* File: mips64/binop2addr.S */
5254 /*
5255 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5256 * that specifies an instruction that performs "result = a0 op a1".
5257 * This could be a MIPS instruction or a function call. (If the result
5258 * comes back in a register other than a0, you can override "result".)
5259 *
5260 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5261 * vB (a1). Useful for integer division and modulus. Note that we
5262 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5263 * correctly.
5264 *
5265 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5266 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5267 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5268 */
5269 /* binop/2addr vA, vB */
5270 ext a2, rINST, 8, 4 # a2 <- A
5271 ext a3, rINST, 12, 4 # a3 <- B
5272 GET_VREG a0, a2 # a0 <- vA
5273 GET_VREG a1, a3 # a1 <- vB
5274 .if 0
5275 beqz a1, common_errDivideByZero # is second operand zero?
5276 .endif
5277 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5278 # optional op
5279 mul a0, a0, a1 # a0 <- op, a0-a3 changed
5280 GET_INST_OPCODE v0 # extract opcode from rINST
5281 SET_VREG a0, a2 # vA <- a0
5282 GOTO_OPCODE v0 # jump to next instruction
5283
5284
5285/* ------------------------------ */
5286 .balign 128
5287.L_op_div_int_2addr: /* 0xb3 */
5288/* File: mips64/op_div_int_2addr.S */
5289/* File: mips64/binop2addr.S */
5290 /*
5291 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5292 * that specifies an instruction that performs "result = a0 op a1".
5293 * This could be a MIPS instruction or a function call. (If the result
5294 * comes back in a register other than a0, you can override "result".)
5295 *
5296 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5297 * vB (a1). Useful for integer division and modulus. Note that we
5298 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5299 * correctly.
5300 *
5301 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5302 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5303 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5304 */
5305 /* binop/2addr vA, vB */
5306 ext a2, rINST, 8, 4 # a2 <- A
5307 ext a3, rINST, 12, 4 # a3 <- B
5308 GET_VREG a0, a2 # a0 <- vA
5309 GET_VREG a1, a3 # a1 <- vB
5310 .if 1
5311 beqz a1, common_errDivideByZero # is second operand zero?
5312 .endif
5313 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5314 # optional op
5315 div a0, a0, a1 # a0 <- op, a0-a3 changed
5316 GET_INST_OPCODE v0 # extract opcode from rINST
5317 SET_VREG a0, a2 # vA <- a0
5318 GOTO_OPCODE v0 # jump to next instruction
5319
5320
5321/* ------------------------------ */
5322 .balign 128
5323.L_op_rem_int_2addr: /* 0xb4 */
5324/* File: mips64/op_rem_int_2addr.S */
5325/* File: mips64/binop2addr.S */
5326 /*
5327 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5328 * that specifies an instruction that performs "result = a0 op a1".
5329 * This could be a MIPS instruction or a function call. (If the result
5330 * comes back in a register other than a0, you can override "result".)
5331 *
5332 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5333 * vB (a1). Useful for integer division and modulus. Note that we
5334 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5335 * correctly.
5336 *
5337 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5338 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5339 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5340 */
5341 /* binop/2addr vA, vB */
5342 ext a2, rINST, 8, 4 # a2 <- A
5343 ext a3, rINST, 12, 4 # a3 <- B
5344 GET_VREG a0, a2 # a0 <- vA
5345 GET_VREG a1, a3 # a1 <- vB
5346 .if 1
5347 beqz a1, common_errDivideByZero # is second operand zero?
5348 .endif
5349 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5350 # optional op
5351 mod a0, a0, a1 # a0 <- op, a0-a3 changed
5352 GET_INST_OPCODE v0 # extract opcode from rINST
5353 SET_VREG a0, a2 # vA <- a0
5354 GOTO_OPCODE v0 # jump to next instruction
5355
5356
5357/* ------------------------------ */
5358 .balign 128
5359.L_op_and_int_2addr: /* 0xb5 */
5360/* File: mips64/op_and_int_2addr.S */
5361/* File: mips64/binop2addr.S */
5362 /*
5363 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5364 * that specifies an instruction that performs "result = a0 op a1".
5365 * This could be a MIPS instruction or a function call. (If the result
5366 * comes back in a register other than a0, you can override "result".)
5367 *
5368 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5369 * vB (a1). Useful for integer division and modulus. Note that we
5370 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5371 * correctly.
5372 *
5373 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5374 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5375 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5376 */
5377 /* binop/2addr vA, vB */
5378 ext a2, rINST, 8, 4 # a2 <- A
5379 ext a3, rINST, 12, 4 # a3 <- B
5380 GET_VREG a0, a2 # a0 <- vA
5381 GET_VREG a1, a3 # a1 <- vB
5382 .if 0
5383 beqz a1, common_errDivideByZero # is second operand zero?
5384 .endif
5385 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5386 # optional op
5387 and a0, a0, a1 # a0 <- op, a0-a3 changed
5388 GET_INST_OPCODE v0 # extract opcode from rINST
5389 SET_VREG a0, a2 # vA <- a0
5390 GOTO_OPCODE v0 # jump to next instruction
5391
5392
5393/* ------------------------------ */
5394 .balign 128
5395.L_op_or_int_2addr: /* 0xb6 */
5396/* File: mips64/op_or_int_2addr.S */
5397/* File: mips64/binop2addr.S */
5398 /*
5399 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5400 * that specifies an instruction that performs "result = a0 op a1".
5401 * This could be a MIPS instruction or a function call. (If the result
5402 * comes back in a register other than a0, you can override "result".)
5403 *
5404 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5405 * vB (a1). Useful for integer division and modulus. Note that we
5406 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5407 * correctly.
5408 *
5409 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5410 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5411 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5412 */
5413 /* binop/2addr vA, vB */
5414 ext a2, rINST, 8, 4 # a2 <- A
5415 ext a3, rINST, 12, 4 # a3 <- B
5416 GET_VREG a0, a2 # a0 <- vA
5417 GET_VREG a1, a3 # a1 <- vB
5418 .if 0
5419 beqz a1, common_errDivideByZero # is second operand zero?
5420 .endif
5421 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5422 # optional op
5423 or a0, a0, a1 # a0 <- op, a0-a3 changed
5424 GET_INST_OPCODE v0 # extract opcode from rINST
5425 SET_VREG a0, a2 # vA <- a0
5426 GOTO_OPCODE v0 # jump to next instruction
5427
5428
5429/* ------------------------------ */
5430 .balign 128
5431.L_op_xor_int_2addr: /* 0xb7 */
5432/* File: mips64/op_xor_int_2addr.S */
5433/* File: mips64/binop2addr.S */
5434 /*
5435 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5436 * that specifies an instruction that performs "result = a0 op a1".
5437 * This could be a MIPS instruction or a function call. (If the result
5438 * comes back in a register other than a0, you can override "result".)
5439 *
5440 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5441 * vB (a1). Useful for integer division and modulus. Note that we
5442 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5443 * correctly.
5444 *
5445 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5446 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5447 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5448 */
5449 /* binop/2addr vA, vB */
5450 ext a2, rINST, 8, 4 # a2 <- A
5451 ext a3, rINST, 12, 4 # a3 <- B
5452 GET_VREG a0, a2 # a0 <- vA
5453 GET_VREG a1, a3 # a1 <- vB
5454 .if 0
5455 beqz a1, common_errDivideByZero # is second operand zero?
5456 .endif
5457 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5458 # optional op
5459 xor a0, a0, a1 # a0 <- op, a0-a3 changed
5460 GET_INST_OPCODE v0 # extract opcode from rINST
5461 SET_VREG a0, a2 # vA <- a0
5462 GOTO_OPCODE v0 # jump to next instruction
5463
5464
5465/* ------------------------------ */
5466 .balign 128
5467.L_op_shl_int_2addr: /* 0xb8 */
5468/* File: mips64/op_shl_int_2addr.S */
5469/* File: mips64/binop2addr.S */
5470 /*
5471 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5472 * that specifies an instruction that performs "result = a0 op a1".
5473 * This could be a MIPS instruction or a function call. (If the result
5474 * comes back in a register other than a0, you can override "result".)
5475 *
5476 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5477 * vB (a1). Useful for integer division and modulus. Note that we
5478 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5479 * correctly.
5480 *
5481 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5482 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5483 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5484 */
5485 /* binop/2addr vA, vB */
5486 ext a2, rINST, 8, 4 # a2 <- A
5487 ext a3, rINST, 12, 4 # a3 <- B
5488 GET_VREG a0, a2 # a0 <- vA
5489 GET_VREG a1, a3 # a1 <- vB
5490 .if 0
5491 beqz a1, common_errDivideByZero # is second operand zero?
5492 .endif
5493 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5494 # optional op
5495 sll a0, a0, a1 # a0 <- op, a0-a3 changed
5496 GET_INST_OPCODE v0 # extract opcode from rINST
5497 SET_VREG a0, a2 # vA <- a0
5498 GOTO_OPCODE v0 # jump to next instruction
5499
5500
5501/* ------------------------------ */
5502 .balign 128
5503.L_op_shr_int_2addr: /* 0xb9 */
5504/* File: mips64/op_shr_int_2addr.S */
5505/* File: mips64/binop2addr.S */
5506 /*
5507 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5508 * that specifies an instruction that performs "result = a0 op a1".
5509 * This could be a MIPS instruction or a function call. (If the result
5510 * comes back in a register other than a0, you can override "result".)
5511 *
5512 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5513 * vB (a1). Useful for integer division and modulus. Note that we
5514 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5515 * correctly.
5516 *
5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5520 */
5521 /* binop/2addr vA, vB */
5522 ext a2, rINST, 8, 4 # a2 <- A
5523 ext a3, rINST, 12, 4 # a3 <- B
5524 GET_VREG a0, a2 # a0 <- vA
5525 GET_VREG a1, a3 # a1 <- vB
5526 .if 0
5527 beqz a1, common_errDivideByZero # is second operand zero?
5528 .endif
5529 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5530 # optional op
5531 sra a0, a0, a1 # a0 <- op, a0-a3 changed
5532 GET_INST_OPCODE v0 # extract opcode from rINST
5533 SET_VREG a0, a2 # vA <- a0
5534 GOTO_OPCODE v0 # jump to next instruction
5535
5536
5537/* ------------------------------ */
5538 .balign 128
5539.L_op_ushr_int_2addr: /* 0xba */
5540/* File: mips64/op_ushr_int_2addr.S */
5541/* File: mips64/binop2addr.S */
5542 /*
5543 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5544 * that specifies an instruction that performs "result = a0 op a1".
5545 * This could be a MIPS instruction or a function call. (If the result
5546 * comes back in a register other than a0, you can override "result".)
5547 *
5548 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5549 * vB (a1). Useful for integer division and modulus. Note that we
5550 * *don't* check for (INT_MIN / -1) here, because the CPU handles it
5551 * correctly.
5552 *
5553 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5554 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5555 * shl-int/2addr, shr-int/2addr, ushr-int/2addr
5556 */
5557 /* binop/2addr vA, vB */
5558 ext a2, rINST, 8, 4 # a2 <- A
5559 ext a3, rINST, 12, 4 # a3 <- B
5560 GET_VREG a0, a2 # a0 <- vA
5561 GET_VREG a1, a3 # a1 <- vB
5562 .if 0
5563 beqz a1, common_errDivideByZero # is second operand zero?
5564 .endif
5565 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5566 # optional op
5567 srl a0, a0, a1 # a0 <- op, a0-a3 changed
5568 GET_INST_OPCODE v0 # extract opcode from rINST
5569 SET_VREG a0, a2 # vA <- a0
5570 GOTO_OPCODE v0 # jump to next instruction
5571
5572
5573/* ------------------------------ */
5574 .balign 128
5575.L_op_add_long_2addr: /* 0xbb */
5576/* File: mips64/op_add_long_2addr.S */
5577/* File: mips64/binopWide2addr.S */
5578 /*
5579 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5580 * that specifies an instruction that performs "result = a0 op a1".
5581 * This could be a MIPS instruction or a function call. (If the result
5582 * comes back in a register other than a0, you can override "result".)
5583 *
5584 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5585 * vB (a1). Useful for integer division and modulus. Note that we
5586 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5587 * correctly.
5588 *
5589 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5590 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5591 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5592 */
5593 /* binop/2addr vA, vB */
5594 ext a2, rINST, 8, 4 # a2 <- A
5595 ext a3, rINST, 12, 4 # a3 <- B
5596 GET_VREG_WIDE a0, a2 # a0 <- vA
5597 GET_VREG_WIDE a1, a3 # a1 <- vB
5598 .if 0
5599 beqz a1, common_errDivideByZero # is second operand zero?
5600 .endif
5601 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5602 # optional op
5603 daddu a0, a0, a1 # a0 <- op, a0-a3 changed
5604 GET_INST_OPCODE v0 # extract opcode from rINST
5605 SET_VREG_WIDE a0, a2 # vA <- a0
5606 GOTO_OPCODE v0 # jump to next instruction
5607
5608
5609/* ------------------------------ */
5610 .balign 128
5611.L_op_sub_long_2addr: /* 0xbc */
5612/* File: mips64/op_sub_long_2addr.S */
5613/* File: mips64/binopWide2addr.S */
5614 /*
5615 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5616 * that specifies an instruction that performs "result = a0 op a1".
5617 * This could be a MIPS instruction or a function call. (If the result
5618 * comes back in a register other than a0, you can override "result".)
5619 *
5620 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5621 * vB (a1). Useful for integer division and modulus. Note that we
5622 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5623 * correctly.
5624 *
5625 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5626 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5627 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5628 */
5629 /* binop/2addr vA, vB */
5630 ext a2, rINST, 8, 4 # a2 <- A
5631 ext a3, rINST, 12, 4 # a3 <- B
5632 GET_VREG_WIDE a0, a2 # a0 <- vA
5633 GET_VREG_WIDE a1, a3 # a1 <- vB
5634 .if 0
5635 beqz a1, common_errDivideByZero # is second operand zero?
5636 .endif
5637 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5638 # optional op
5639 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed
5640 GET_INST_OPCODE v0 # extract opcode from rINST
5641 SET_VREG_WIDE a0, a2 # vA <- a0
5642 GOTO_OPCODE v0 # jump to next instruction
5643
5644
5645/* ------------------------------ */
5646 .balign 128
5647.L_op_mul_long_2addr: /* 0xbd */
5648/* File: mips64/op_mul_long_2addr.S */
5649/* File: mips64/binopWide2addr.S */
5650 /*
5651 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5652 * that specifies an instruction that performs "result = a0 op a1".
5653 * This could be a MIPS instruction or a function call. (If the result
5654 * comes back in a register other than a0, you can override "result".)
5655 *
5656 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5657 * vB (a1). Useful for integer division and modulus. Note that we
5658 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5659 * correctly.
5660 *
5661 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5662 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5663 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5664 */
5665 /* binop/2addr vA, vB */
5666 ext a2, rINST, 8, 4 # a2 <- A
5667 ext a3, rINST, 12, 4 # a3 <- B
5668 GET_VREG_WIDE a0, a2 # a0 <- vA
5669 GET_VREG_WIDE a1, a3 # a1 <- vB
5670 .if 0
5671 beqz a1, common_errDivideByZero # is second operand zero?
5672 .endif
5673 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5674 # optional op
5675 dmul a0, a0, a1 # a0 <- op, a0-a3 changed
5676 GET_INST_OPCODE v0 # extract opcode from rINST
5677 SET_VREG_WIDE a0, a2 # vA <- a0
5678 GOTO_OPCODE v0 # jump to next instruction
5679
5680
5681/* ------------------------------ */
5682 .balign 128
5683.L_op_div_long_2addr: /* 0xbe */
5684/* File: mips64/op_div_long_2addr.S */
5685/* File: mips64/binopWide2addr.S */
5686 /*
5687 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5688 * that specifies an instruction that performs "result = a0 op a1".
5689 * This could be a MIPS instruction or a function call. (If the result
5690 * comes back in a register other than a0, you can override "result".)
5691 *
5692 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5693 * vB (a1). Useful for integer division and modulus. Note that we
5694 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5695 * correctly.
5696 *
5697 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5698 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5699 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5700 */
5701 /* binop/2addr vA, vB */
5702 ext a2, rINST, 8, 4 # a2 <- A
5703 ext a3, rINST, 12, 4 # a3 <- B
5704 GET_VREG_WIDE a0, a2 # a0 <- vA
5705 GET_VREG_WIDE a1, a3 # a1 <- vB
5706 .if 1
5707 beqz a1, common_errDivideByZero # is second operand zero?
5708 .endif
5709 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5710 # optional op
5711 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed
5712 GET_INST_OPCODE v0 # extract opcode from rINST
5713 SET_VREG_WIDE a0, a2 # vA <- a0
5714 GOTO_OPCODE v0 # jump to next instruction
5715
5716
5717/* ------------------------------ */
5718 .balign 128
5719.L_op_rem_long_2addr: /* 0xbf */
5720/* File: mips64/op_rem_long_2addr.S */
5721/* File: mips64/binopWide2addr.S */
5722 /*
5723 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5724 * that specifies an instruction that performs "result = a0 op a1".
5725 * This could be a MIPS instruction or a function call. (If the result
5726 * comes back in a register other than a0, you can override "result".)
5727 *
5728 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5729 * vB (a1). Useful for integer division and modulus. Note that we
5730 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5731 * correctly.
5732 *
5733 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5734 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5735 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5736 */
5737 /* binop/2addr vA, vB */
5738 ext a2, rINST, 8, 4 # a2 <- A
5739 ext a3, rINST, 12, 4 # a3 <- B
5740 GET_VREG_WIDE a0, a2 # a0 <- vA
5741 GET_VREG_WIDE a1, a3 # a1 <- vB
5742 .if 1
5743 beqz a1, common_errDivideByZero # is second operand zero?
5744 .endif
5745 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5746 # optional op
5747 dmod a0, a0, a1 # a0 <- op, a0-a3 changed
5748 GET_INST_OPCODE v0 # extract opcode from rINST
5749 SET_VREG_WIDE a0, a2 # vA <- a0
5750 GOTO_OPCODE v0 # jump to next instruction
5751
5752
5753/* ------------------------------ */
5754 .balign 128
5755.L_op_and_long_2addr: /* 0xc0 */
5756/* File: mips64/op_and_long_2addr.S */
5757/* File: mips64/binopWide2addr.S */
5758 /*
5759 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5760 * that specifies an instruction that performs "result = a0 op a1".
5761 * This could be a MIPS instruction or a function call. (If the result
5762 * comes back in a register other than a0, you can override "result".)
5763 *
5764 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5765 * vB (a1). Useful for integer division and modulus. Note that we
5766 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5767 * correctly.
5768 *
5769 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5770 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5771 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5772 */
5773 /* binop/2addr vA, vB */
5774 ext a2, rINST, 8, 4 # a2 <- A
5775 ext a3, rINST, 12, 4 # a3 <- B
5776 GET_VREG_WIDE a0, a2 # a0 <- vA
5777 GET_VREG_WIDE a1, a3 # a1 <- vB
5778 .if 0
5779 beqz a1, common_errDivideByZero # is second operand zero?
5780 .endif
5781 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5782 # optional op
5783 and a0, a0, a1 # a0 <- op, a0-a3 changed
5784 GET_INST_OPCODE v0 # extract opcode from rINST
5785 SET_VREG_WIDE a0, a2 # vA <- a0
5786 GOTO_OPCODE v0 # jump to next instruction
5787
5788
5789/* ------------------------------ */
5790 .balign 128
5791.L_op_or_long_2addr: /* 0xc1 */
5792/* File: mips64/op_or_long_2addr.S */
5793/* File: mips64/binopWide2addr.S */
5794 /*
5795 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5796 * that specifies an instruction that performs "result = a0 op a1".
5797 * This could be a MIPS instruction or a function call. (If the result
5798 * comes back in a register other than a0, you can override "result".)
5799 *
5800 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5801 * vB (a1). Useful for integer division and modulus. Note that we
5802 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5803 * correctly.
5804 *
5805 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5806 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5807 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5808 */
5809 /* binop/2addr vA, vB */
5810 ext a2, rINST, 8, 4 # a2 <- A
5811 ext a3, rINST, 12, 4 # a3 <- B
5812 GET_VREG_WIDE a0, a2 # a0 <- vA
5813 GET_VREG_WIDE a1, a3 # a1 <- vB
5814 .if 0
5815 beqz a1, common_errDivideByZero # is second operand zero?
5816 .endif
5817 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5818 # optional op
5819 or a0, a0, a1 # a0 <- op, a0-a3 changed
5820 GET_INST_OPCODE v0 # extract opcode from rINST
5821 SET_VREG_WIDE a0, a2 # vA <- a0
5822 GOTO_OPCODE v0 # jump to next instruction
5823
5824
5825/* ------------------------------ */
5826 .balign 128
5827.L_op_xor_long_2addr: /* 0xc2 */
5828/* File: mips64/op_xor_long_2addr.S */
5829/* File: mips64/binopWide2addr.S */
5830 /*
5831 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5832 * that specifies an instruction that performs "result = a0 op a1".
5833 * This could be a MIPS instruction or a function call. (If the result
5834 * comes back in a register other than a0, you can override "result".)
5835 *
5836 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5837 * vB (a1). Useful for integer division and modulus. Note that we
5838 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5839 * correctly.
5840 *
5841 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5842 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5843 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5844 */
5845 /* binop/2addr vA, vB */
5846 ext a2, rINST, 8, 4 # a2 <- A
5847 ext a3, rINST, 12, 4 # a3 <- B
5848 GET_VREG_WIDE a0, a2 # a0 <- vA
5849 GET_VREG_WIDE a1, a3 # a1 <- vB
5850 .if 0
5851 beqz a1, common_errDivideByZero # is second operand zero?
5852 .endif
5853 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5854 # optional op
5855 xor a0, a0, a1 # a0 <- op, a0-a3 changed
5856 GET_INST_OPCODE v0 # extract opcode from rINST
5857 SET_VREG_WIDE a0, a2 # vA <- a0
5858 GOTO_OPCODE v0 # jump to next instruction
5859
5860
5861/* ------------------------------ */
5862 .balign 128
5863.L_op_shl_long_2addr: /* 0xc3 */
5864/* File: mips64/op_shl_long_2addr.S */
5865/* File: mips64/binopWide2addr.S */
5866 /*
5867 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5868 * that specifies an instruction that performs "result = a0 op a1".
5869 * This could be a MIPS instruction or a function call. (If the result
5870 * comes back in a register other than a0, you can override "result".)
5871 *
5872 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5873 * vB (a1). Useful for integer division and modulus. Note that we
5874 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5875 * correctly.
5876 *
5877 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5878 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5879 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5880 */
5881 /* binop/2addr vA, vB */
5882 ext a2, rINST, 8, 4 # a2 <- A
5883 ext a3, rINST, 12, 4 # a3 <- B
5884 GET_VREG_WIDE a0, a2 # a0 <- vA
5885 GET_VREG_WIDE a1, a3 # a1 <- vB
5886 .if 0
5887 beqz a1, common_errDivideByZero # is second operand zero?
5888 .endif
5889 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5890 # optional op
5891 dsll a0, a0, a1 # a0 <- op, a0-a3 changed
5892 GET_INST_OPCODE v0 # extract opcode from rINST
5893 SET_VREG_WIDE a0, a2 # vA <- a0
5894 GOTO_OPCODE v0 # jump to next instruction
5895
5896
5897/* ------------------------------ */
5898 .balign 128
5899.L_op_shr_long_2addr: /* 0xc4 */
5900/* File: mips64/op_shr_long_2addr.S */
5901/* File: mips64/binopWide2addr.S */
5902 /*
5903 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5904 * that specifies an instruction that performs "result = a0 op a1".
5905 * This could be a MIPS instruction or a function call. (If the result
5906 * comes back in a register other than a0, you can override "result".)
5907 *
5908 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5909 * vB (a1). Useful for integer division and modulus. Note that we
5910 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5911 * correctly.
5912 *
5913 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5914 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5915 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5916 */
5917 /* binop/2addr vA, vB */
5918 ext a2, rINST, 8, 4 # a2 <- A
5919 ext a3, rINST, 12, 4 # a3 <- B
5920 GET_VREG_WIDE a0, a2 # a0 <- vA
5921 GET_VREG_WIDE a1, a3 # a1 <- vB
5922 .if 0
5923 beqz a1, common_errDivideByZero # is second operand zero?
5924 .endif
5925 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5926 # optional op
5927 dsra a0, a0, a1 # a0 <- op, a0-a3 changed
5928 GET_INST_OPCODE v0 # extract opcode from rINST
5929 SET_VREG_WIDE a0, a2 # vA <- a0
5930 GOTO_OPCODE v0 # jump to next instruction
5931
5932
5933/* ------------------------------ */
5934 .balign 128
5935.L_op_ushr_long_2addr: /* 0xc5 */
5936/* File: mips64/op_ushr_long_2addr.S */
5937/* File: mips64/binopWide2addr.S */
5938 /*
5939 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5940 * that specifies an instruction that performs "result = a0 op a1".
5941 * This could be a MIPS instruction or a function call. (If the result
5942 * comes back in a register other than a0, you can override "result".)
5943 *
5944 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5945 * vB (a1). Useful for integer division and modulus. Note that we
5946 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it
5947 * correctly.
5948 *
5949 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr,
5950 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr,
5951 * shl-long/2addr, shr-long/2addr, ushr-long/2addr
5952 */
5953 /* binop/2addr vA, vB */
5954 ext a2, rINST, 8, 4 # a2 <- A
5955 ext a3, rINST, 12, 4 # a3 <- B
5956 GET_VREG_WIDE a0, a2 # a0 <- vA
5957 GET_VREG_WIDE a1, a3 # a1 <- vB
5958 .if 0
5959 beqz a1, common_errDivideByZero # is second operand zero?
5960 .endif
5961 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5962 # optional op
5963 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed
5964 GET_INST_OPCODE v0 # extract opcode from rINST
5965 SET_VREG_WIDE a0, a2 # vA <- a0
5966 GOTO_OPCODE v0 # jump to next instruction
5967
5968
5969/* ------------------------------ */
5970 .balign 128
5971.L_op_add_float_2addr: /* 0xc6 */
5972/* File: mips64/op_add_float_2addr.S */
5973/* File: mips64/fbinop2addr.S */
5974 /*:
5975 * Generic 32-bit "/2addr" floating-point operation.
5976 *
5977 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr.
5978 * form: <op> f0, f0, f1
5979 */
5980 /* binop/2addr vA, vB */
5981 ext a2, rINST, 8, 4 # a2 <- A
5982 ext a3, rINST, 12, 4 # a3 <- B
5983 GET_VREG_FLOAT f0, a2 # f0 <- vA
5984 GET_VREG_FLOAT f1, a3 # f1 <- vB
5985 add.s f0, f0, f1 # f0 <- f0 op f1
5986 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
5987 GET_INST_OPCODE v0 # extract opcode from rINST
5988 SET_VREG_FLOAT f0, a2 # vA <- f0
5989 GOTO_OPCODE v0 # jump to next instruction
5990
5991
5992/* ------------------------------ */
5993 .balign 128
5994.L_op_sub_float_2addr: /* 0xc7 */
5995/* File: mips64/op_sub_float_2addr.S */
5996/* File: mips64/fbinop2addr.S */
5997 /*:
5998 * Generic 32-bit "/2addr" floating-point operation.
5999 *
6000 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr.
6001 * form: <op> f0, f0, f1
6002 */
6003 /* binop/2addr vA, vB */
6004 ext a2, rINST, 8, 4 # a2 <- A
6005 ext a3, rINST, 12, 4 # a3 <- B
6006 GET_VREG_FLOAT f0, a2 # f0 <- vA
6007 GET_VREG_FLOAT f1, a3 # f1 <- vB
6008 sub.s f0, f0, f1 # f0 <- f0 op f1
6009 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6010 GET_INST_OPCODE v0 # extract opcode from rINST
6011 SET_VREG_FLOAT f0, a2 # vA <- f0
6012 GOTO_OPCODE v0 # jump to next instruction
6013
6014
6015/* ------------------------------ */
6016 .balign 128
6017.L_op_mul_float_2addr: /* 0xc8 */
6018/* File: mips64/op_mul_float_2addr.S */
6019/* File: mips64/fbinop2addr.S */
6020 /*:
6021 * Generic 32-bit "/2addr" floating-point operation.
6022 *
6023 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr.
6024 * form: <op> f0, f0, f1
6025 */
6026 /* binop/2addr vA, vB */
6027 ext a2, rINST, 8, 4 # a2 <- A
6028 ext a3, rINST, 12, 4 # a3 <- B
6029 GET_VREG_FLOAT f0, a2 # f0 <- vA
6030 GET_VREG_FLOAT f1, a3 # f1 <- vB
6031 mul.s f0, f0, f1 # f0 <- f0 op f1
6032 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6033 GET_INST_OPCODE v0 # extract opcode from rINST
6034 SET_VREG_FLOAT f0, a2 # vA <- f0
6035 GOTO_OPCODE v0 # jump to next instruction
6036
6037
6038/* ------------------------------ */
6039 .balign 128
6040.L_op_div_float_2addr: /* 0xc9 */
6041/* File: mips64/op_div_float_2addr.S */
6042/* File: mips64/fbinop2addr.S */
6043 /*:
6044 * Generic 32-bit "/2addr" floating-point operation.
6045 *
6046 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr.
6047 * form: <op> f0, f0, f1
6048 */
6049 /* binop/2addr vA, vB */
6050 ext a2, rINST, 8, 4 # a2 <- A
6051 ext a3, rINST, 12, 4 # a3 <- B
6052 GET_VREG_FLOAT f0, a2 # f0 <- vA
6053 GET_VREG_FLOAT f1, a3 # f1 <- vB
6054 div.s f0, f0, f1 # f0 <- f0 op f1
6055 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6056 GET_INST_OPCODE v0 # extract opcode from rINST
6057 SET_VREG_FLOAT f0, a2 # vA <- f0
6058 GOTO_OPCODE v0 # jump to next instruction
6059
6060
6061/* ------------------------------ */
6062 .balign 128
6063.L_op_rem_float_2addr: /* 0xca */
6064/* File: mips64/op_rem_float_2addr.S */
6065 /* rem-float/2addr vA, vB */
6066 .extern fmodf
6067 ext a2, rINST, 8, 4 # a2 <- A
6068 ext a3, rINST, 12, 4 # a3 <- B
6069 GET_VREG_FLOAT f12, a2 # f12 <- vA
6070 GET_VREG_FLOAT f13, a3 # f13 <- vB
6071 jal fmodf # f0 <- f12 op f13
6072 ext a2, rINST, 8, 4 # a2 <- A
6073 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6074 GET_INST_OPCODE v0 # extract opcode from rINST
6075 SET_VREG_FLOAT f0, a2 # vA <- f0
6076 GOTO_OPCODE v0 # jump to next instruction
6077
6078/* ------------------------------ */
6079 .balign 128
6080.L_op_add_double_2addr: /* 0xcb */
6081/* File: mips64/op_add_double_2addr.S */
6082/* File: mips64/fbinopWide2addr.S */
6083 /*:
6084 * Generic 64-bit "/2addr" floating-point operation.
6085 *
6086 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr.
6087 * form: <op> f0, f0, f1
6088 */
6089 /* binop/2addr vA, vB */
6090 ext a2, rINST, 8, 4 # a2 <- A
6091 ext a3, rINST, 12, 4 # a3 <- B
6092 GET_VREG_DOUBLE f0, a2 # f0 <- vA
6093 GET_VREG_DOUBLE f1, a3 # f1 <- vB
6094 add.d f0, f0, f1 # f0 <- f0 op f1
6095 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6096 GET_INST_OPCODE v0 # extract opcode from rINST
6097 SET_VREG_DOUBLE f0, a2 # vA <- f0
6098 GOTO_OPCODE v0 # jump to next instruction
6099
6100
6101/* ------------------------------ */
6102 .balign 128
6103.L_op_sub_double_2addr: /* 0xcc */
6104/* File: mips64/op_sub_double_2addr.S */
6105/* File: mips64/fbinopWide2addr.S */
6106 /*:
6107 * Generic 64-bit "/2addr" floating-point operation.
6108 *
6109 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr.
6110 * form: <op> f0, f0, f1
6111 */
6112 /* binop/2addr vA, vB */
6113 ext a2, rINST, 8, 4 # a2 <- A
6114 ext a3, rINST, 12, 4 # a3 <- B
6115 GET_VREG_DOUBLE f0, a2 # f0 <- vA
6116 GET_VREG_DOUBLE f1, a3 # f1 <- vB
6117 sub.d f0, f0, f1 # f0 <- f0 op f1
6118 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6119 GET_INST_OPCODE v0 # extract opcode from rINST
6120 SET_VREG_DOUBLE f0, a2 # vA <- f0
6121 GOTO_OPCODE v0 # jump to next instruction
6122
6123
6124/* ------------------------------ */
6125 .balign 128
6126.L_op_mul_double_2addr: /* 0xcd */
6127/* File: mips64/op_mul_double_2addr.S */
6128/* File: mips64/fbinopWide2addr.S */
6129 /*:
6130 * Generic 64-bit "/2addr" floating-point operation.
6131 *
6132 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr.
6133 * form: <op> f0, f0, f1
6134 */
6135 /* binop/2addr vA, vB */
6136 ext a2, rINST, 8, 4 # a2 <- A
6137 ext a3, rINST, 12, 4 # a3 <- B
6138 GET_VREG_DOUBLE f0, a2 # f0 <- vA
6139 GET_VREG_DOUBLE f1, a3 # f1 <- vB
6140 mul.d f0, f0, f1 # f0 <- f0 op f1
6141 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6142 GET_INST_OPCODE v0 # extract opcode from rINST
6143 SET_VREG_DOUBLE f0, a2 # vA <- f0
6144 GOTO_OPCODE v0 # jump to next instruction
6145
6146
6147/* ------------------------------ */
6148 .balign 128
6149.L_op_div_double_2addr: /* 0xce */
6150/* File: mips64/op_div_double_2addr.S */
6151/* File: mips64/fbinopWide2addr.S */
6152 /*:
6153 * Generic 64-bit "/2addr" floating-point operation.
6154 *
6155 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr.
6156 * form: <op> f0, f0, f1
6157 */
6158 /* binop/2addr vA, vB */
6159 ext a2, rINST, 8, 4 # a2 <- A
6160 ext a3, rINST, 12, 4 # a3 <- B
6161 GET_VREG_DOUBLE f0, a2 # f0 <- vA
6162 GET_VREG_DOUBLE f1, a3 # f1 <- vB
6163 div.d f0, f0, f1 # f0 <- f0 op f1
6164 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6165 GET_INST_OPCODE v0 # extract opcode from rINST
6166 SET_VREG_DOUBLE f0, a2 # vA <- f0
6167 GOTO_OPCODE v0 # jump to next instruction
6168
6169
6170/* ------------------------------ */
6171 .balign 128
6172.L_op_rem_double_2addr: /* 0xcf */
6173/* File: mips64/op_rem_double_2addr.S */
6174 /* rem-double/2addr vA, vB */
6175 .extern fmod
6176 ext a2, rINST, 8, 4 # a2 <- A
6177 ext a3, rINST, 12, 4 # a3 <- B
6178 GET_VREG_DOUBLE f12, a2 # f12 <- vA
6179 GET_VREG_DOUBLE f13, a3 # f13 <- vB
6180 jal fmod # f0 <- f12 op f13
6181 ext a2, rINST, 8, 4 # a2 <- A
6182 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
6183 GET_INST_OPCODE v0 # extract opcode from rINST
6184 SET_VREG_DOUBLE f0, a2 # vA <- f0
6185 GOTO_OPCODE v0 # jump to next instruction
6186
6187/* ------------------------------ */
6188 .balign 128
6189.L_op_add_int_lit16: /* 0xd0 */
6190/* File: mips64/op_add_int_lit16.S */
6191/* File: mips64/binopLit16.S */
6192 /*
6193 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6194 * that specifies an instruction that performs "result = a0 op a1".
6195 * This could be an MIPS instruction or a function call. (If the result
6196 * comes back in a register other than a0, you can override "result".)
6197 *
6198 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6199 * CCCC (a1). Useful for integer division and modulus.
6200 *
6201 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6202 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6203 */
6204 /* binop/lit16 vA, vB, #+CCCC */
6205 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6206 ext a2, rINST, 8, 4 # a2 <- A
6207 ext a3, rINST, 12, 4 # a3 <- B
6208 GET_VREG a0, a3 # a0 <- vB
6209 .if 0
6210 beqz a1, common_errDivideByZero # is second operand zero?
6211 .endif
6212 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6213 # optional op
6214 addu a0, a0, a1 # a0 <- op, a0-a3 changed
6215 GET_INST_OPCODE v0 # extract opcode from rINST
6216 SET_VREG a0, a2 # vA <- a0
6217 GOTO_OPCODE v0 # jump to next instruction
6218
6219
6220
6221/* ------------------------------ */
6222 .balign 128
6223.L_op_rsub_int: /* 0xd1 */
6224/* File: mips64/op_rsub_int.S */
6225/* File: mips64/binopLit16.S */
6226 /*
6227 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6228 * that specifies an instruction that performs "result = a0 op a1".
6229 * This could be an MIPS instruction or a function call. (If the result
6230 * comes back in a register other than a0, you can override "result".)
6231 *
6232 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6233 * CCCC (a1). Useful for integer division and modulus.
6234 *
6235 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6236 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6237 */
6238 /* binop/lit16 vA, vB, #+CCCC */
6239 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6240 ext a2, rINST, 8, 4 # a2 <- A
6241 ext a3, rINST, 12, 4 # a3 <- B
6242 GET_VREG a0, a3 # a0 <- vB
6243 .if 0
6244 beqz a1, common_errDivideByZero # is second operand zero?
6245 .endif
6246 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6247 # optional op
6248 subu a0, a1, a0 # a0 <- op, a0-a3 changed
6249 GET_INST_OPCODE v0 # extract opcode from rINST
6250 SET_VREG a0, a2 # vA <- a0
6251 GOTO_OPCODE v0 # jump to next instruction
6252
6253
6254
6255/* ------------------------------ */
6256 .balign 128
6257.L_op_mul_int_lit16: /* 0xd2 */
6258/* File: mips64/op_mul_int_lit16.S */
6259/* File: mips64/binopLit16.S */
6260 /*
6261 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6262 * that specifies an instruction that performs "result = a0 op a1".
6263 * This could be an MIPS instruction or a function call. (If the result
6264 * comes back in a register other than a0, you can override "result".)
6265 *
6266 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6267 * CCCC (a1). Useful for integer division and modulus.
6268 *
6269 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6270 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6271 */
6272 /* binop/lit16 vA, vB, #+CCCC */
6273 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6274 ext a2, rINST, 8, 4 # a2 <- A
6275 ext a3, rINST, 12, 4 # a3 <- B
6276 GET_VREG a0, a3 # a0 <- vB
6277 .if 0
6278 beqz a1, common_errDivideByZero # is second operand zero?
6279 .endif
6280 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6281 # optional op
6282 mul a0, a0, a1 # a0 <- op, a0-a3 changed
6283 GET_INST_OPCODE v0 # extract opcode from rINST
6284 SET_VREG a0, a2 # vA <- a0
6285 GOTO_OPCODE v0 # jump to next instruction
6286
6287
6288
6289/* ------------------------------ */
6290 .balign 128
6291.L_op_div_int_lit16: /* 0xd3 */
6292/* File: mips64/op_div_int_lit16.S */
6293/* File: mips64/binopLit16.S */
6294 /*
6295 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6296 * that specifies an instruction that performs "result = a0 op a1".
6297 * This could be an MIPS instruction or a function call. (If the result
6298 * comes back in a register other than a0, you can override "result".)
6299 *
6300 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6301 * CCCC (a1). Useful for integer division and modulus.
6302 *
6303 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6304 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6305 */
6306 /* binop/lit16 vA, vB, #+CCCC */
6307 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6308 ext a2, rINST, 8, 4 # a2 <- A
6309 ext a3, rINST, 12, 4 # a3 <- B
6310 GET_VREG a0, a3 # a0 <- vB
6311 .if 1
6312 beqz a1, common_errDivideByZero # is second operand zero?
6313 .endif
6314 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6315 # optional op
6316 div a0, a0, a1 # a0 <- op, a0-a3 changed
6317 GET_INST_OPCODE v0 # extract opcode from rINST
6318 SET_VREG a0, a2 # vA <- a0
6319 GOTO_OPCODE v0 # jump to next instruction
6320
6321
6322
6323/* ------------------------------ */
6324 .balign 128
6325.L_op_rem_int_lit16: /* 0xd4 */
6326/* File: mips64/op_rem_int_lit16.S */
6327/* File: mips64/binopLit16.S */
6328 /*
6329 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6330 * that specifies an instruction that performs "result = a0 op a1".
6331 * This could be an MIPS instruction or a function call. (If the result
6332 * comes back in a register other than a0, you can override "result".)
6333 *
6334 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6335 * CCCC (a1). Useful for integer division and modulus.
6336 *
6337 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6338 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6339 */
6340 /* binop/lit16 vA, vB, #+CCCC */
6341 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6342 ext a2, rINST, 8, 4 # a2 <- A
6343 ext a3, rINST, 12, 4 # a3 <- B
6344 GET_VREG a0, a3 # a0 <- vB
6345 .if 1
6346 beqz a1, common_errDivideByZero # is second operand zero?
6347 .endif
6348 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6349 # optional op
6350 mod a0, a0, a1 # a0 <- op, a0-a3 changed
6351 GET_INST_OPCODE v0 # extract opcode from rINST
6352 SET_VREG a0, a2 # vA <- a0
6353 GOTO_OPCODE v0 # jump to next instruction
6354
6355
6356
6357/* ------------------------------ */
6358 .balign 128
6359.L_op_and_int_lit16: /* 0xd5 */
6360/* File: mips64/op_and_int_lit16.S */
6361/* File: mips64/binopLit16.S */
6362 /*
6363 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6364 * that specifies an instruction that performs "result = a0 op a1".
6365 * This could be an MIPS instruction or a function call. (If the result
6366 * comes back in a register other than a0, you can override "result".)
6367 *
6368 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6369 * CCCC (a1). Useful for integer division and modulus.
6370 *
6371 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6372 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6373 */
6374 /* binop/lit16 vA, vB, #+CCCC */
6375 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6376 ext a2, rINST, 8, 4 # a2 <- A
6377 ext a3, rINST, 12, 4 # a3 <- B
6378 GET_VREG a0, a3 # a0 <- vB
6379 .if 0
6380 beqz a1, common_errDivideByZero # is second operand zero?
6381 .endif
6382 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6383 # optional op
6384 and a0, a0, a1 # a0 <- op, a0-a3 changed
6385 GET_INST_OPCODE v0 # extract opcode from rINST
6386 SET_VREG a0, a2 # vA <- a0
6387 GOTO_OPCODE v0 # jump to next instruction
6388
6389
6390
6391/* ------------------------------ */
6392 .balign 128
6393.L_op_or_int_lit16: /* 0xd6 */
6394/* File: mips64/op_or_int_lit16.S */
6395/* File: mips64/binopLit16.S */
6396 /*
6397 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6398 * that specifies an instruction that performs "result = a0 op a1".
6399 * This could be an MIPS instruction or a function call. (If the result
6400 * comes back in a register other than a0, you can override "result".)
6401 *
6402 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6403 * CCCC (a1). Useful for integer division and modulus.
6404 *
6405 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6406 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6407 */
6408 /* binop/lit16 vA, vB, #+CCCC */
6409 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6410 ext a2, rINST, 8, 4 # a2 <- A
6411 ext a3, rINST, 12, 4 # a3 <- B
6412 GET_VREG a0, a3 # a0 <- vB
6413 .if 0
6414 beqz a1, common_errDivideByZero # is second operand zero?
6415 .endif
6416 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6417 # optional op
6418 or a0, a0, a1 # a0 <- op, a0-a3 changed
6419 GET_INST_OPCODE v0 # extract opcode from rINST
6420 SET_VREG a0, a2 # vA <- a0
6421 GOTO_OPCODE v0 # jump to next instruction
6422
6423
6424
6425/* ------------------------------ */
6426 .balign 128
6427.L_op_xor_int_lit16: /* 0xd7 */
6428/* File: mips64/op_xor_int_lit16.S */
6429/* File: mips64/binopLit16.S */
6430 /*
6431 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6432 * that specifies an instruction that performs "result = a0 op a1".
6433 * This could be an MIPS instruction or a function call. (If the result
6434 * comes back in a register other than a0, you can override "result".)
6435 *
6436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6437 * CCCC (a1). Useful for integer division and modulus.
6438 *
6439 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6440 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6441 */
6442 /* binop/lit16 vA, vB, #+CCCC */
6443 lh a1, 2(rPC) # a1 <- sign-extended CCCC
6444 ext a2, rINST, 8, 4 # a2 <- A
6445 ext a3, rINST, 12, 4 # a3 <- B
6446 GET_VREG a0, a3 # a0 <- vB
6447 .if 0
6448 beqz a1, common_errDivideByZero # is second operand zero?
6449 .endif
6450 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6451 # optional op
6452 xor a0, a0, a1 # a0 <- op, a0-a3 changed
6453 GET_INST_OPCODE v0 # extract opcode from rINST
6454 SET_VREG a0, a2 # vA <- a0
6455 GOTO_OPCODE v0 # jump to next instruction
6456
6457
6458
6459/* ------------------------------ */
6460 .balign 128
6461.L_op_add_int_lit8: /* 0xd8 */
6462/* File: mips64/op_add_int_lit8.S */
6463/* File: mips64/binopLit8.S */
6464 /*
6465 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6466 * that specifies an instruction that performs "result = a0 op a1".
6467 * This could be an MIPS instruction or a function call. (If the result
6468 * comes back in a register other than a0, you can override "result".)
6469 *
6470 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6471 * CC (a1). Useful for integer division and modulus.
6472 *
6473 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6474 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6475 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6476 */
6477 /* binop/lit8 vAA, vBB, #+CC */
6478 lbu a3, 2(rPC) # a3 <- BB
6479 lb a1, 3(rPC) # a1 <- sign-extended CC
6480 srl a2, rINST, 8 # a2 <- AA
6481 GET_VREG a0, a3 # a0 <- vBB
6482 .if 0
6483 beqz a1, common_errDivideByZero # is second operand zero?
6484 .endif
6485 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6486 # optional op
6487 addu a0, a0, a1 # a0 <- op, a0-a3 changed
6488 GET_INST_OPCODE v0 # extract opcode from rINST
6489 SET_VREG a0, a2 # vAA <- a0
6490 GOTO_OPCODE v0 # jump to next instruction
6491
6492
6493
6494/* ------------------------------ */
6495 .balign 128
6496.L_op_rsub_int_lit8: /* 0xd9 */
6497/* File: mips64/op_rsub_int_lit8.S */
6498/* File: mips64/binopLit8.S */
6499 /*
6500 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6501 * that specifies an instruction that performs "result = a0 op a1".
6502 * This could be an MIPS instruction or a function call. (If the result
6503 * comes back in a register other than a0, you can override "result".)
6504 *
6505 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6506 * CC (a1). Useful for integer division and modulus.
6507 *
6508 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6509 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6510 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6511 */
6512 /* binop/lit8 vAA, vBB, #+CC */
6513 lbu a3, 2(rPC) # a3 <- BB
6514 lb a1, 3(rPC) # a1 <- sign-extended CC
6515 srl a2, rINST, 8 # a2 <- AA
6516 GET_VREG a0, a3 # a0 <- vBB
6517 .if 0
6518 beqz a1, common_errDivideByZero # is second operand zero?
6519 .endif
6520 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6521 # optional op
6522 subu a0, a1, a0 # a0 <- op, a0-a3 changed
6523 GET_INST_OPCODE v0 # extract opcode from rINST
6524 SET_VREG a0, a2 # vAA <- a0
6525 GOTO_OPCODE v0 # jump to next instruction
6526
6527
6528
6529/* ------------------------------ */
6530 .balign 128
6531.L_op_mul_int_lit8: /* 0xda */
6532/* File: mips64/op_mul_int_lit8.S */
6533/* File: mips64/binopLit8.S */
6534 /*
6535 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6536 * that specifies an instruction that performs "result = a0 op a1".
6537 * This could be an MIPS instruction or a function call. (If the result
6538 * comes back in a register other than a0, you can override "result".)
6539 *
6540 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6541 * CC (a1). Useful for integer division and modulus.
6542 *
6543 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6544 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6545 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6546 */
6547 /* binop/lit8 vAA, vBB, #+CC */
6548 lbu a3, 2(rPC) # a3 <- BB
6549 lb a1, 3(rPC) # a1 <- sign-extended CC
6550 srl a2, rINST, 8 # a2 <- AA
6551 GET_VREG a0, a3 # a0 <- vBB
6552 .if 0
6553 beqz a1, common_errDivideByZero # is second operand zero?
6554 .endif
6555 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6556 # optional op
6557 mul a0, a0, a1 # a0 <- op, a0-a3 changed
6558 GET_INST_OPCODE v0 # extract opcode from rINST
6559 SET_VREG a0, a2 # vAA <- a0
6560 GOTO_OPCODE v0 # jump to next instruction
6561
6562
6563
6564/* ------------------------------ */
6565 .balign 128
6566.L_op_div_int_lit8: /* 0xdb */
6567/* File: mips64/op_div_int_lit8.S */
6568/* File: mips64/binopLit8.S */
6569 /*
6570 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6571 * that specifies an instruction that performs "result = a0 op a1".
6572 * This could be an MIPS instruction or a function call. (If the result
6573 * comes back in a register other than a0, you can override "result".)
6574 *
6575 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6576 * CC (a1). Useful for integer division and modulus.
6577 *
6578 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6579 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6580 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6581 */
6582 /* binop/lit8 vAA, vBB, #+CC */
6583 lbu a3, 2(rPC) # a3 <- BB
6584 lb a1, 3(rPC) # a1 <- sign-extended CC
6585 srl a2, rINST, 8 # a2 <- AA
6586 GET_VREG a0, a3 # a0 <- vBB
6587 .if 1
6588 beqz a1, common_errDivideByZero # is second operand zero?
6589 .endif
6590 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6591 # optional op
6592 div a0, a0, a1 # a0 <- op, a0-a3 changed
6593 GET_INST_OPCODE v0 # extract opcode from rINST
6594 SET_VREG a0, a2 # vAA <- a0
6595 GOTO_OPCODE v0 # jump to next instruction
6596
6597
6598
6599/* ------------------------------ */
6600 .balign 128
6601.L_op_rem_int_lit8: /* 0xdc */
6602/* File: mips64/op_rem_int_lit8.S */
6603/* File: mips64/binopLit8.S */
6604 /*
6605 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6606 * that specifies an instruction that performs "result = a0 op a1".
6607 * This could be an MIPS instruction or a function call. (If the result
6608 * comes back in a register other than a0, you can override "result".)
6609 *
6610 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6611 * CC (a1). Useful for integer division and modulus.
6612 *
6613 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6614 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6615 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6616 */
6617 /* binop/lit8 vAA, vBB, #+CC */
6618 lbu a3, 2(rPC) # a3 <- BB
6619 lb a1, 3(rPC) # a1 <- sign-extended CC
6620 srl a2, rINST, 8 # a2 <- AA
6621 GET_VREG a0, a3 # a0 <- vBB
6622 .if 1
6623 beqz a1, common_errDivideByZero # is second operand zero?
6624 .endif
6625 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6626 # optional op
6627 mod a0, a0, a1 # a0 <- op, a0-a3 changed
6628 GET_INST_OPCODE v0 # extract opcode from rINST
6629 SET_VREG a0, a2 # vAA <- a0
6630 GOTO_OPCODE v0 # jump to next instruction
6631
6632
6633
6634/* ------------------------------ */
6635 .balign 128
6636.L_op_and_int_lit8: /* 0xdd */
6637/* File: mips64/op_and_int_lit8.S */
6638/* File: mips64/binopLit8.S */
6639 /*
6640 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6641 * that specifies an instruction that performs "result = a0 op a1".
6642 * This could be an MIPS instruction or a function call. (If the result
6643 * comes back in a register other than a0, you can override "result".)
6644 *
6645 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6646 * CC (a1). Useful for integer division and modulus.
6647 *
6648 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6649 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6650 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6651 */
6652 /* binop/lit8 vAA, vBB, #+CC */
6653 lbu a3, 2(rPC) # a3 <- BB
6654 lb a1, 3(rPC) # a1 <- sign-extended CC
6655 srl a2, rINST, 8 # a2 <- AA
6656 GET_VREG a0, a3 # a0 <- vBB
6657 .if 0
6658 beqz a1, common_errDivideByZero # is second operand zero?
6659 .endif
6660 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6661 # optional op
6662 and a0, a0, a1 # a0 <- op, a0-a3 changed
6663 GET_INST_OPCODE v0 # extract opcode from rINST
6664 SET_VREG a0, a2 # vAA <- a0
6665 GOTO_OPCODE v0 # jump to next instruction
6666
6667
6668
6669/* ------------------------------ */
6670 .balign 128
6671.L_op_or_int_lit8: /* 0xde */
6672/* File: mips64/op_or_int_lit8.S */
6673/* File: mips64/binopLit8.S */
6674 /*
6675 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6676 * that specifies an instruction that performs "result = a0 op a1".
6677 * This could be an MIPS instruction or a function call. (If the result
6678 * comes back in a register other than a0, you can override "result".)
6679 *
6680 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6681 * CC (a1). Useful for integer division and modulus.
6682 *
6683 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6684 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6685 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6686 */
6687 /* binop/lit8 vAA, vBB, #+CC */
6688 lbu a3, 2(rPC) # a3 <- BB
6689 lb a1, 3(rPC) # a1 <- sign-extended CC
6690 srl a2, rINST, 8 # a2 <- AA
6691 GET_VREG a0, a3 # a0 <- vBB
6692 .if 0
6693 beqz a1, common_errDivideByZero # is second operand zero?
6694 .endif
6695 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6696 # optional op
6697 or a0, a0, a1 # a0 <- op, a0-a3 changed
6698 GET_INST_OPCODE v0 # extract opcode from rINST
6699 SET_VREG a0, a2 # vAA <- a0
6700 GOTO_OPCODE v0 # jump to next instruction
6701
6702
6703
6704/* ------------------------------ */
6705 .balign 128
6706.L_op_xor_int_lit8: /* 0xdf */
6707/* File: mips64/op_xor_int_lit8.S */
6708/* File: mips64/binopLit8.S */
6709 /*
6710 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6711 * that specifies an instruction that performs "result = a0 op a1".
6712 * This could be an MIPS instruction or a function call. (If the result
6713 * comes back in a register other than a0, you can override "result".)
6714 *
6715 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6716 * CC (a1). Useful for integer division and modulus.
6717 *
6718 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6719 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6720 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6721 */
6722 /* binop/lit8 vAA, vBB, #+CC */
6723 lbu a3, 2(rPC) # a3 <- BB
6724 lb a1, 3(rPC) # a1 <- sign-extended CC
6725 srl a2, rINST, 8 # a2 <- AA
6726 GET_VREG a0, a3 # a0 <- vBB
6727 .if 0
6728 beqz a1, common_errDivideByZero # is second operand zero?
6729 .endif
6730 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6731 # optional op
6732 xor a0, a0, a1 # a0 <- op, a0-a3 changed
6733 GET_INST_OPCODE v0 # extract opcode from rINST
6734 SET_VREG a0, a2 # vAA <- a0
6735 GOTO_OPCODE v0 # jump to next instruction
6736
6737
6738
6739/* ------------------------------ */
6740 .balign 128
6741.L_op_shl_int_lit8: /* 0xe0 */
6742/* File: mips64/op_shl_int_lit8.S */
6743/* File: mips64/binopLit8.S */
6744 /*
6745 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6746 * that specifies an instruction that performs "result = a0 op a1".
6747 * This could be an MIPS instruction or a function call. (If the result
6748 * comes back in a register other than a0, you can override "result".)
6749 *
6750 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6751 * CC (a1). Useful for integer division and modulus.
6752 *
6753 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6754 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6755 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6756 */
6757 /* binop/lit8 vAA, vBB, #+CC */
6758 lbu a3, 2(rPC) # a3 <- BB
6759 lb a1, 3(rPC) # a1 <- sign-extended CC
6760 srl a2, rINST, 8 # a2 <- AA
6761 GET_VREG a0, a3 # a0 <- vBB
6762 .if 0
6763 beqz a1, common_errDivideByZero # is second operand zero?
6764 .endif
6765 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6766 # optional op
6767 sll a0, a0, a1 # a0 <- op, a0-a3 changed
6768 GET_INST_OPCODE v0 # extract opcode from rINST
6769 SET_VREG a0, a2 # vAA <- a0
6770 GOTO_OPCODE v0 # jump to next instruction
6771
6772
6773
6774/* ------------------------------ */
6775 .balign 128
6776.L_op_shr_int_lit8: /* 0xe1 */
6777/* File: mips64/op_shr_int_lit8.S */
6778/* File: mips64/binopLit8.S */
6779 /*
6780 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6781 * that specifies an instruction that performs "result = a0 op a1".
6782 * This could be an MIPS instruction or a function call. (If the result
6783 * comes back in a register other than a0, you can override "result".)
6784 *
6785 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6786 * CC (a1). Useful for integer division and modulus.
6787 *
6788 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6789 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6790 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6791 */
6792 /* binop/lit8 vAA, vBB, #+CC */
6793 lbu a3, 2(rPC) # a3 <- BB
6794 lb a1, 3(rPC) # a1 <- sign-extended CC
6795 srl a2, rINST, 8 # a2 <- AA
6796 GET_VREG a0, a3 # a0 <- vBB
6797 .if 0
6798 beqz a1, common_errDivideByZero # is second operand zero?
6799 .endif
6800 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6801 # optional op
6802 sra a0, a0, a1 # a0 <- op, a0-a3 changed
6803 GET_INST_OPCODE v0 # extract opcode from rINST
6804 SET_VREG a0, a2 # vAA <- a0
6805 GOTO_OPCODE v0 # jump to next instruction
6806
6807
6808
6809/* ------------------------------ */
6810 .balign 128
6811.L_op_ushr_int_lit8: /* 0xe2 */
6812/* File: mips64/op_ushr_int_lit8.S */
6813/* File: mips64/binopLit8.S */
6814 /*
6815 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6816 * that specifies an instruction that performs "result = a0 op a1".
6817 * This could be an MIPS instruction or a function call. (If the result
6818 * comes back in a register other than a0, you can override "result".)
6819 *
6820 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6821 * CC (a1). Useful for integer division and modulus.
6822 *
6823 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6824 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6825 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6826 */
6827 /* binop/lit8 vAA, vBB, #+CC */
6828 lbu a3, 2(rPC) # a3 <- BB
6829 lb a1, 3(rPC) # a1 <- sign-extended CC
6830 srl a2, rINST, 8 # a2 <- AA
6831 GET_VREG a0, a3 # a0 <- vBB
6832 .if 0
6833 beqz a1, common_errDivideByZero # is second operand zero?
6834 .endif
6835 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6836 # optional op
6837 srl a0, a0, a1 # a0 <- op, a0-a3 changed
6838 GET_INST_OPCODE v0 # extract opcode from rINST
6839 SET_VREG a0, a2 # vAA <- a0
6840 GOTO_OPCODE v0 # jump to next instruction
6841
6842
6843
6844/* ------------------------------ */
6845 .balign 128
6846.L_op_iget_quick: /* 0xe3 */
6847/* File: mips64/op_iget_quick.S */
6848 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
6849 /* op vA, vB, offset//CCCC */
6850 srl a2, rINST, 12 # a2 <- B
6851 lhu a1, 2(rPC) # a1 <- field byte offset
6852 GET_VREG_U a3, a2 # a3 <- object we're operating on
6853 ext a4, rINST, 8, 4 # a4 <- A
6854 daddu a1, a1, a3
6855 beqz a3, common_errNullObject # object was null
6856 lw a0, 0(a1) # a0 <- obj.field
6857 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6858 SET_VREG a0, a4 # fp[A] <- a0
6859 GET_INST_OPCODE v0 # extract opcode from rINST
6860 GOTO_OPCODE v0 # jump to next instruction
6861
6862/* ------------------------------ */
6863 .balign 128
6864.L_op_iget_wide_quick: /* 0xe4 */
6865/* File: mips64/op_iget_wide_quick.S */
6866 /* iget-wide-quick vA, vB, offset//CCCC */
6867 srl a2, rINST, 12 # a2 <- B
6868 lhu a4, 2(rPC) # a4 <- field byte offset
6869 GET_VREG_U a3, a2 # a3 <- object we're operating on
6870 ext a2, rINST, 8, 4 # a2 <- A
6871 beqz a3, common_errNullObject # object was null
6872 daddu a4, a3, a4 # create direct pointer
6873 lw a0, 0(a4)
6874 lw a1, 4(a4)
6875 dinsu a0, a1, 32, 32
6876 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6877 SET_VREG_WIDE a0, a2
6878 GET_INST_OPCODE v0 # extract opcode from rINST
6879 GOTO_OPCODE v0 # jump to next instruction
6880
6881/* ------------------------------ */
6882 .balign 128
6883.L_op_iget_object_quick: /* 0xe5 */
6884/* File: mips64/op_iget_object_quick.S */
6885 /* For: iget-object-quick */
6886 /* op vA, vB, offset//CCCC */
6887 .extern artIGetObjectFromMterp
6888 srl a2, rINST, 12 # a2 <- B
6889 lhu a1, 2(rPC) # a1 <- field byte offset
6890 EXPORT_PC
6891 GET_VREG_U a0, a2 # a0 <- object we're operating on
6892 jal artIGetObjectFromMterp # (obj, offset)
6893 ld a3, THREAD_EXCEPTION_OFFSET(rSELF)
6894 ext a2, rINST, 8, 4 # a2 <- A
6895 PREFETCH_INST 2
6896 bnez a3, MterpPossibleException # bail out
6897 SET_VREG_OBJECT v0, a2 # fp[A] <- v0
6898 ADVANCE 2 # advance rPC
6899 GET_INST_OPCODE v0 # extract opcode from rINST
6900 GOTO_OPCODE v0 # jump to next instruction
6901
6902/* ------------------------------ */
6903 .balign 128
6904.L_op_iput_quick: /* 0xe6 */
6905/* File: mips64/op_iput_quick.S */
6906 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
6907 /* op vA, vB, offset//CCCC */
6908 srl a2, rINST, 12 # a2 <- B
6909 lhu a1, 2(rPC) # a1 <- field byte offset
6910 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer
6911 ext a2, rINST, 8, 4 # a2 <- A
6912 beqz a3, common_errNullObject # object was null
6913 GET_VREG a0, a2 # a0 <- fp[A]
6914 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6915 daddu a1, a1, a3
6916 sw a0, 0(a1) # obj.field <- a0
6917 GET_INST_OPCODE v0 # extract opcode from rINST
6918 GOTO_OPCODE v0 # jump to next instruction
6919
6920/* ------------------------------ */
6921 .balign 128
6922.L_op_iput_wide_quick: /* 0xe7 */
6923/* File: mips64/op_iput_wide_quick.S */
6924 /* iput-wide-quick vA, vB, offset//CCCC */
6925 srl a2, rINST, 12 # a2 <- B
6926 lhu a3, 2(rPC) # a3 <- field byte offset
6927 GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer
6928 ext a0, rINST, 8, 4 # a0 <- A
6929 beqz a2, common_errNullObject # object was null
6930 GET_VREG_WIDE a0, a0 # a0 <- fp[A]
6931 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6932 daddu a1, a2, a3 # create a direct pointer
6933 sw a0, 0(a1)
6934 dsrl32 a0, a0, 0
6935 sw a0, 4(a1)
6936 GET_INST_OPCODE v0 # extract opcode from rINST
6937 GOTO_OPCODE v0 # jump to next instruction
6938
6939/* ------------------------------ */
6940 .balign 128
6941.L_op_iput_object_quick: /* 0xe8 */
6942/* File: mips64/op_iput_object_quick.S */
6943 .extern MterpIputObjectQuick
6944 EXPORT_PC
6945 daddu a0, rFP, OFF_FP_SHADOWFRAME
6946 move a1, rPC
6947 move a2, rINST
6948 jal MterpIputObjectQuick
6949 beqzc v0, MterpException
6950 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
6951 GET_INST_OPCODE v0 # extract opcode from rINST
6952 GOTO_OPCODE v0 # jump to next instruction
6953
6954/* ------------------------------ */
6955 .balign 128
6956.L_op_invoke_virtual_quick: /* 0xe9 */
6957/* File: mips64/op_invoke_virtual_quick.S */
6958/* File: mips64/invoke.S */
6959 /*
6960 * Generic invoke handler wrapper.
6961 */
6962 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
6963 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
6964 .extern MterpInvokeVirtualQuick
6965 EXPORT_PC
6966 move a0, rSELF
6967 daddu a1, rFP, OFF_FP_SHADOWFRAME
6968 move a2, rPC
6969 move a3, rINST
6970 jal MterpInvokeVirtualQuick
6971 beqzc v0, MterpException
6972 FETCH_ADVANCE_INST 3
6973 GET_INST_OPCODE v0
6974 GOTO_OPCODE v0
6975
6976
6977/* ------------------------------ */
6978 .balign 128
6979.L_op_invoke_virtual_range_quick: /* 0xea */
6980/* File: mips64/op_invoke_virtual_range_quick.S */
6981/* File: mips64/invoke.S */
6982 /*
6983 * Generic invoke handler wrapper.
6984 */
6985 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
6986 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
6987 .extern MterpInvokeVirtualQuickRange
6988 EXPORT_PC
6989 move a0, rSELF
6990 daddu a1, rFP, OFF_FP_SHADOWFRAME
6991 move a2, rPC
6992 move a3, rINST
6993 jal MterpInvokeVirtualQuickRange
6994 beqzc v0, MterpException
6995 FETCH_ADVANCE_INST 3
6996 GET_INST_OPCODE v0
6997 GOTO_OPCODE v0
6998
6999
7000/* ------------------------------ */
7001 .balign 128
7002.L_op_iput_boolean_quick: /* 0xeb */
7003/* File: mips64/op_iput_boolean_quick.S */
7004/* File: mips64/op_iput_quick.S */
7005 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
7006 /* op vA, vB, offset//CCCC */
7007 srl a2, rINST, 12 # a2 <- B
7008 lhu a1, 2(rPC) # a1 <- field byte offset
7009 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer
7010 ext a2, rINST, 8, 4 # a2 <- A
7011 beqz a3, common_errNullObject # object was null
7012 GET_VREG a0, a2 # a0 <- fp[A]
7013 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7014 daddu a1, a1, a3
7015 sb a0, 0(a1) # obj.field <- a0
7016 GET_INST_OPCODE v0 # extract opcode from rINST
7017 GOTO_OPCODE v0 # jump to next instruction
7018
7019
7020/* ------------------------------ */
7021 .balign 128
7022.L_op_iput_byte_quick: /* 0xec */
7023/* File: mips64/op_iput_byte_quick.S */
7024/* File: mips64/op_iput_quick.S */
7025 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
7026 /* op vA, vB, offset//CCCC */
7027 srl a2, rINST, 12 # a2 <- B
7028 lhu a1, 2(rPC) # a1 <- field byte offset
7029 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer
7030 ext a2, rINST, 8, 4 # a2 <- A
7031 beqz a3, common_errNullObject # object was null
7032 GET_VREG a0, a2 # a0 <- fp[A]
7033 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7034 daddu a1, a1, a3
7035 sb a0, 0(a1) # obj.field <- a0
7036 GET_INST_OPCODE v0 # extract opcode from rINST
7037 GOTO_OPCODE v0 # jump to next instruction
7038
7039
7040/* ------------------------------ */
7041 .balign 128
7042.L_op_iput_char_quick: /* 0xed */
7043/* File: mips64/op_iput_char_quick.S */
7044/* File: mips64/op_iput_quick.S */
7045 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
7046 /* op vA, vB, offset//CCCC */
7047 srl a2, rINST, 12 # a2 <- B
7048 lhu a1, 2(rPC) # a1 <- field byte offset
7049 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer
7050 ext a2, rINST, 8, 4 # a2 <- A
7051 beqz a3, common_errNullObject # object was null
7052 GET_VREG a0, a2 # a0 <- fp[A]
7053 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7054 daddu a1, a1, a3
7055 sh a0, 0(a1) # obj.field <- a0
7056 GET_INST_OPCODE v0 # extract opcode from rINST
7057 GOTO_OPCODE v0 # jump to next instruction
7058
7059
7060/* ------------------------------ */
7061 .balign 128
7062.L_op_iput_short_quick: /* 0xee */
7063/* File: mips64/op_iput_short_quick.S */
7064/* File: mips64/op_iput_quick.S */
7065 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */
7066 /* op vA, vB, offset//CCCC */
7067 srl a2, rINST, 12 # a2 <- B
7068 lhu a1, 2(rPC) # a1 <- field byte offset
7069 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer
7070 ext a2, rINST, 8, 4 # a2 <- A
7071 beqz a3, common_errNullObject # object was null
7072 GET_VREG a0, a2 # a0 <- fp[A]
7073 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7074 daddu a1, a1, a3
7075 sh a0, 0(a1) # obj.field <- a0
7076 GET_INST_OPCODE v0 # extract opcode from rINST
7077 GOTO_OPCODE v0 # jump to next instruction
7078
7079
7080/* ------------------------------ */
7081 .balign 128
7082.L_op_iget_boolean_quick: /* 0xef */
7083/* File: mips64/op_iget_boolean_quick.S */
7084/* File: mips64/op_iget_quick.S */
7085 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7086 /* op vA, vB, offset//CCCC */
7087 srl a2, rINST, 12 # a2 <- B
7088 lhu a1, 2(rPC) # a1 <- field byte offset
7089 GET_VREG_U a3, a2 # a3 <- object we're operating on
7090 ext a4, rINST, 8, 4 # a4 <- A
7091 daddu a1, a1, a3
7092 beqz a3, common_errNullObject # object was null
7093 lbu a0, 0(a1) # a0 <- obj.field
7094 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7095 SET_VREG a0, a4 # fp[A] <- a0
7096 GET_INST_OPCODE v0 # extract opcode from rINST
7097 GOTO_OPCODE v0 # jump to next instruction
7098
7099
7100/* ------------------------------ */
7101 .balign 128
7102.L_op_iget_byte_quick: /* 0xf0 */
7103/* File: mips64/op_iget_byte_quick.S */
7104/* File: mips64/op_iget_quick.S */
7105 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7106 /* op vA, vB, offset//CCCC */
7107 srl a2, rINST, 12 # a2 <- B
7108 lhu a1, 2(rPC) # a1 <- field byte offset
7109 GET_VREG_U a3, a2 # a3 <- object we're operating on
7110 ext a4, rINST, 8, 4 # a4 <- A
7111 daddu a1, a1, a3
7112 beqz a3, common_errNullObject # object was null
7113 lb a0, 0(a1) # a0 <- obj.field
7114 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7115 SET_VREG a0, a4 # fp[A] <- a0
7116 GET_INST_OPCODE v0 # extract opcode from rINST
7117 GOTO_OPCODE v0 # jump to next instruction
7118
7119
7120/* ------------------------------ */
7121 .balign 128
7122.L_op_iget_char_quick: /* 0xf1 */
7123/* File: mips64/op_iget_char_quick.S */
7124/* File: mips64/op_iget_quick.S */
7125 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7126 /* op vA, vB, offset//CCCC */
7127 srl a2, rINST, 12 # a2 <- B
7128 lhu a1, 2(rPC) # a1 <- field byte offset
7129 GET_VREG_U a3, a2 # a3 <- object we're operating on
7130 ext a4, rINST, 8, 4 # a4 <- A
7131 daddu a1, a1, a3
7132 beqz a3, common_errNullObject # object was null
7133 lhu a0, 0(a1) # a0 <- obj.field
7134 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7135 SET_VREG a0, a4 # fp[A] <- a0
7136 GET_INST_OPCODE v0 # extract opcode from rINST
7137 GOTO_OPCODE v0 # jump to next instruction
7138
7139
7140/* ------------------------------ */
7141 .balign 128
7142.L_op_iget_short_quick: /* 0xf2 */
7143/* File: mips64/op_iget_short_quick.S */
7144/* File: mips64/op_iget_quick.S */
7145 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */
7146 /* op vA, vB, offset//CCCC */
7147 srl a2, rINST, 12 # a2 <- B
7148 lhu a1, 2(rPC) # a1 <- field byte offset
7149 GET_VREG_U a3, a2 # a3 <- object we're operating on
7150 ext a4, rINST, 8, 4 # a4 <- A
7151 daddu a1, a1, a3
7152 beqz a3, common_errNullObject # object was null
7153 lh a0, 0(a1) # a0 <- obj.field
7154 FETCH_ADVANCE_INST 2 # advance rPC, load rINST
7155 SET_VREG a0, a4 # fp[A] <- a0
7156 GET_INST_OPCODE v0 # extract opcode from rINST
7157 GOTO_OPCODE v0 # jump to next instruction
7158
7159
7160/* ------------------------------ */
7161 .balign 128
7162.L_op_invoke_lambda: /* 0xf3 */
7163/* Transfer stub to alternate interpreter */
7164 b MterpFallback
7165
7166/* ------------------------------ */
7167 .balign 128
7168.L_op_unused_f4: /* 0xf4 */
7169/* File: mips64/op_unused_f4.S */
7170/* File: mips64/unused.S */
7171/*
7172 * Bail to reference interpreter to throw.
7173 */
7174 b MterpFallback
7175
7176
7177/* ------------------------------ */
7178 .balign 128
7179.L_op_capture_variable: /* 0xf5 */
7180/* Transfer stub to alternate interpreter */
7181 b MterpFallback
7182
7183/* ------------------------------ */
7184 .balign 128
7185.L_op_create_lambda: /* 0xf6 */
7186/* Transfer stub to alternate interpreter */
7187 b MterpFallback
7188
7189/* ------------------------------ */
7190 .balign 128
7191.L_op_liberate_variable: /* 0xf7 */
7192/* Transfer stub to alternate interpreter */
7193 b MterpFallback
7194
7195/* ------------------------------ */
7196 .balign 128
7197.L_op_box_lambda: /* 0xf8 */
7198/* Transfer stub to alternate interpreter */
7199 b MterpFallback
7200
7201/* ------------------------------ */
7202 .balign 128
7203.L_op_unbox_lambda: /* 0xf9 */
7204/* Transfer stub to alternate interpreter */
7205 b MterpFallback
7206
7207/* ------------------------------ */
7208 .balign 128
7209.L_op_unused_fa: /* 0xfa */
7210/* File: mips64/op_unused_fa.S */
7211/* File: mips64/unused.S */
7212/*
7213 * Bail to reference interpreter to throw.
7214 */
7215 b MterpFallback
7216
7217
7218/* ------------------------------ */
7219 .balign 128
7220.L_op_unused_fb: /* 0xfb */
7221/* File: mips64/op_unused_fb.S */
7222/* File: mips64/unused.S */
7223/*
7224 * Bail to reference interpreter to throw.
7225 */
7226 b MterpFallback
7227
7228
7229/* ------------------------------ */
7230 .balign 128
7231.L_op_unused_fc: /* 0xfc */
7232/* File: mips64/op_unused_fc.S */
7233/* File: mips64/unused.S */
7234/*
7235 * Bail to reference interpreter to throw.
7236 */
7237 b MterpFallback
7238
7239
7240/* ------------------------------ */
7241 .balign 128
7242.L_op_unused_fd: /* 0xfd */
7243/* File: mips64/op_unused_fd.S */
7244/* File: mips64/unused.S */
7245/*
7246 * Bail to reference interpreter to throw.
7247 */
7248 b MterpFallback
7249
7250
7251/* ------------------------------ */
7252 .balign 128
7253.L_op_unused_fe: /* 0xfe */
7254/* File: mips64/op_unused_fe.S */
7255/* File: mips64/unused.S */
7256/*
7257 * Bail to reference interpreter to throw.
7258 */
7259 b MterpFallback
7260
7261
7262/* ------------------------------ */
7263 .balign 128
7264.L_op_unused_ff: /* 0xff */
7265/* File: mips64/op_unused_ff.S */
7266/* File: mips64/unused.S */
7267/*
7268 * Bail to reference interpreter to throw.
7269 */
7270 b MterpFallback
7271
7272
7273 .balign 128
7274 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart
7275 .global artMterpAsmInstructionEnd
7276artMterpAsmInstructionEnd:
7277
7278/*
7279 * ===========================================================================
7280 * Sister implementations
7281 * ===========================================================================
7282 */
7283 .global artMterpAsmSisterStart
7284 .type artMterpAsmSisterStart, %function
7285 .text
7286 .balign 4
7287artMterpAsmSisterStart:
7288
7289/* continuation for op_float_to_int */
7290.Lop_float_to_int_trunc:
7291 trunc.w.s f0, f0
7292 mfc1 t0, f0
7293.Lop_float_to_int_done:
7294 /* Can't include fcvtFooter.S after break */
7295 GET_INST_OPCODE v0 # extract opcode from rINST
7296 SET_VREG t0, a1
7297 GOTO_OPCODE v0 # jump to next instruction
7298
7299/* continuation for op_float_to_long */
7300.Lop_float_to_long_trunc:
7301 trunc.l.s f0, f0
7302 dmfc1 t0, f0
7303.Lop_float_to_long_done:
7304 /* Can't include fcvtFooter.S after break */
7305 GET_INST_OPCODE v0 # extract opcode from rINST
7306 SET_VREG_WIDE t0, a1
7307 GOTO_OPCODE v0 # jump to next instruction
7308
7309/* continuation for op_double_to_int */
7310.Lop_double_to_int_trunc:
7311 trunc.w.d f0, f0
7312 mfc1 t0, f0
7313.Lop_double_to_int_done:
7314 /* Can't include fcvtFooter.S after break */
7315 GET_INST_OPCODE v0 # extract opcode from rINST
7316 SET_VREG t0, a1
7317 GOTO_OPCODE v0 # jump to next instruction
7318
7319/* continuation for op_double_to_long */
7320.Lop_double_to_long_trunc:
7321 trunc.l.d f0, f0
7322 dmfc1 t0, f0
7323.Lop_double_to_long_done:
7324 /* Can't include fcvtFooter.S after break */
7325 GET_INST_OPCODE v0 # extract opcode from rINST
7326 SET_VREG_WIDE t0, a1
7327 GOTO_OPCODE v0 # jump to next instruction
7328
7329 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart
7330 .global artMterpAsmSisterEnd
7331artMterpAsmSisterEnd:
7332
7333
7334 .global artMterpAsmAltInstructionStart
7335 .type artMterpAsmAltInstructionStart, %function
7336 .text
7337
7338artMterpAsmAltInstructionStart = .L_ALT_op_nop
7339/* ------------------------------ */
7340 .balign 128
7341.L_ALT_op_nop: /* 0x00 */
7342/* File: mips64/alt_stub.S */
7343/*
7344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7345 * any interesting requests and then jump to the real instruction
7346 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7347 */
7348 .extern MterpCheckBefore
7349 EXPORT_PC
7350 REFRESH_IBASE
7351 dla ra, artMterpAsmInstructionStart
7352 dla t9, MterpCheckBefore
7353 move a0, rSELF
7354 daddu a1, rFP, OFF_FP_SHADOWFRAME
7355 daddu ra, ra, (0 * 128) # Addr of primary handler.
7356 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7357
7358/* ------------------------------ */
7359 .balign 128
7360.L_ALT_op_move: /* 0x01 */
7361/* File: mips64/alt_stub.S */
7362/*
7363 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7364 * any interesting requests and then jump to the real instruction
7365 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7366 */
7367 .extern MterpCheckBefore
7368 EXPORT_PC
7369 REFRESH_IBASE
7370 dla ra, artMterpAsmInstructionStart
7371 dla t9, MterpCheckBefore
7372 move a0, rSELF
7373 daddu a1, rFP, OFF_FP_SHADOWFRAME
7374 daddu ra, ra, (1 * 128) # Addr of primary handler.
7375 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7376
7377/* ------------------------------ */
7378 .balign 128
7379.L_ALT_op_move_from16: /* 0x02 */
7380/* File: mips64/alt_stub.S */
7381/*
7382 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7383 * any interesting requests and then jump to the real instruction
7384 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7385 */
7386 .extern MterpCheckBefore
7387 EXPORT_PC
7388 REFRESH_IBASE
7389 dla ra, artMterpAsmInstructionStart
7390 dla t9, MterpCheckBefore
7391 move a0, rSELF
7392 daddu a1, rFP, OFF_FP_SHADOWFRAME
7393 daddu ra, ra, (2 * 128) # Addr of primary handler.
7394 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7395
7396/* ------------------------------ */
7397 .balign 128
7398.L_ALT_op_move_16: /* 0x03 */
7399/* File: mips64/alt_stub.S */
7400/*
7401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7402 * any interesting requests and then jump to the real instruction
7403 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7404 */
7405 .extern MterpCheckBefore
7406 EXPORT_PC
7407 REFRESH_IBASE
7408 dla ra, artMterpAsmInstructionStart
7409 dla t9, MterpCheckBefore
7410 move a0, rSELF
7411 daddu a1, rFP, OFF_FP_SHADOWFRAME
7412 daddu ra, ra, (3 * 128) # Addr of primary handler.
7413 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7414
7415/* ------------------------------ */
7416 .balign 128
7417.L_ALT_op_move_wide: /* 0x04 */
7418/* File: mips64/alt_stub.S */
7419/*
7420 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7421 * any interesting requests and then jump to the real instruction
7422 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7423 */
7424 .extern MterpCheckBefore
7425 EXPORT_PC
7426 REFRESH_IBASE
7427 dla ra, artMterpAsmInstructionStart
7428 dla t9, MterpCheckBefore
7429 move a0, rSELF
7430 daddu a1, rFP, OFF_FP_SHADOWFRAME
7431 daddu ra, ra, (4 * 128) # Addr of primary handler.
7432 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7433
7434/* ------------------------------ */
7435 .balign 128
7436.L_ALT_op_move_wide_from16: /* 0x05 */
7437/* File: mips64/alt_stub.S */
7438/*
7439 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7440 * any interesting requests and then jump to the real instruction
7441 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7442 */
7443 .extern MterpCheckBefore
7444 EXPORT_PC
7445 REFRESH_IBASE
7446 dla ra, artMterpAsmInstructionStart
7447 dla t9, MterpCheckBefore
7448 move a0, rSELF
7449 daddu a1, rFP, OFF_FP_SHADOWFRAME
7450 daddu ra, ra, (5 * 128) # Addr of primary handler.
7451 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7452
7453/* ------------------------------ */
7454 .balign 128
7455.L_ALT_op_move_wide_16: /* 0x06 */
7456/* File: mips64/alt_stub.S */
7457/*
7458 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7459 * any interesting requests and then jump to the real instruction
7460 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7461 */
7462 .extern MterpCheckBefore
7463 EXPORT_PC
7464 REFRESH_IBASE
7465 dla ra, artMterpAsmInstructionStart
7466 dla t9, MterpCheckBefore
7467 move a0, rSELF
7468 daddu a1, rFP, OFF_FP_SHADOWFRAME
7469 daddu ra, ra, (6 * 128) # Addr of primary handler.
7470 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7471
7472/* ------------------------------ */
7473 .balign 128
7474.L_ALT_op_move_object: /* 0x07 */
7475/* File: mips64/alt_stub.S */
7476/*
7477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7478 * any interesting requests and then jump to the real instruction
7479 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7480 */
7481 .extern MterpCheckBefore
7482 EXPORT_PC
7483 REFRESH_IBASE
7484 dla ra, artMterpAsmInstructionStart
7485 dla t9, MterpCheckBefore
7486 move a0, rSELF
7487 daddu a1, rFP, OFF_FP_SHADOWFRAME
7488 daddu ra, ra, (7 * 128) # Addr of primary handler.
7489 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7490
7491/* ------------------------------ */
7492 .balign 128
7493.L_ALT_op_move_object_from16: /* 0x08 */
7494/* File: mips64/alt_stub.S */
7495/*
7496 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7497 * any interesting requests and then jump to the real instruction
7498 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7499 */
7500 .extern MterpCheckBefore
7501 EXPORT_PC
7502 REFRESH_IBASE
7503 dla ra, artMterpAsmInstructionStart
7504 dla t9, MterpCheckBefore
7505 move a0, rSELF
7506 daddu a1, rFP, OFF_FP_SHADOWFRAME
7507 daddu ra, ra, (8 * 128) # Addr of primary handler.
7508 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7509
7510/* ------------------------------ */
7511 .balign 128
7512.L_ALT_op_move_object_16: /* 0x09 */
7513/* File: mips64/alt_stub.S */
7514/*
7515 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7516 * any interesting requests and then jump to the real instruction
7517 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7518 */
7519 .extern MterpCheckBefore
7520 EXPORT_PC
7521 REFRESH_IBASE
7522 dla ra, artMterpAsmInstructionStart
7523 dla t9, MterpCheckBefore
7524 move a0, rSELF
7525 daddu a1, rFP, OFF_FP_SHADOWFRAME
7526 daddu ra, ra, (9 * 128) # Addr of primary handler.
7527 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7528
7529/* ------------------------------ */
7530 .balign 128
7531.L_ALT_op_move_result: /* 0x0a */
7532/* File: mips64/alt_stub.S */
7533/*
7534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7535 * any interesting requests and then jump to the real instruction
7536 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7537 */
7538 .extern MterpCheckBefore
7539 EXPORT_PC
7540 REFRESH_IBASE
7541 dla ra, artMterpAsmInstructionStart
7542 dla t9, MterpCheckBefore
7543 move a0, rSELF
7544 daddu a1, rFP, OFF_FP_SHADOWFRAME
7545 daddu ra, ra, (10 * 128) # Addr of primary handler.
7546 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7547
7548/* ------------------------------ */
7549 .balign 128
7550.L_ALT_op_move_result_wide: /* 0x0b */
7551/* File: mips64/alt_stub.S */
7552/*
7553 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7554 * any interesting requests and then jump to the real instruction
7555 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7556 */
7557 .extern MterpCheckBefore
7558 EXPORT_PC
7559 REFRESH_IBASE
7560 dla ra, artMterpAsmInstructionStart
7561 dla t9, MterpCheckBefore
7562 move a0, rSELF
7563 daddu a1, rFP, OFF_FP_SHADOWFRAME
7564 daddu ra, ra, (11 * 128) # Addr of primary handler.
7565 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7566
7567/* ------------------------------ */
7568 .balign 128
7569.L_ALT_op_move_result_object: /* 0x0c */
7570/* File: mips64/alt_stub.S */
7571/*
7572 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7573 * any interesting requests and then jump to the real instruction
7574 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7575 */
7576 .extern MterpCheckBefore
7577 EXPORT_PC
7578 REFRESH_IBASE
7579 dla ra, artMterpAsmInstructionStart
7580 dla t9, MterpCheckBefore
7581 move a0, rSELF
7582 daddu a1, rFP, OFF_FP_SHADOWFRAME
7583 daddu ra, ra, (12 * 128) # Addr of primary handler.
7584 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7585
7586/* ------------------------------ */
7587 .balign 128
7588.L_ALT_op_move_exception: /* 0x0d */
7589/* File: mips64/alt_stub.S */
7590/*
7591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7592 * any interesting requests and then jump to the real instruction
7593 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7594 */
7595 .extern MterpCheckBefore
7596 EXPORT_PC
7597 REFRESH_IBASE
7598 dla ra, artMterpAsmInstructionStart
7599 dla t9, MterpCheckBefore
7600 move a0, rSELF
7601 daddu a1, rFP, OFF_FP_SHADOWFRAME
7602 daddu ra, ra, (13 * 128) # Addr of primary handler.
7603 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7604
7605/* ------------------------------ */
7606 .balign 128
7607.L_ALT_op_return_void: /* 0x0e */
7608/* File: mips64/alt_stub.S */
7609/*
7610 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7611 * any interesting requests and then jump to the real instruction
7612 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7613 */
7614 .extern MterpCheckBefore
7615 EXPORT_PC
7616 REFRESH_IBASE
7617 dla ra, artMterpAsmInstructionStart
7618 dla t9, MterpCheckBefore
7619 move a0, rSELF
7620 daddu a1, rFP, OFF_FP_SHADOWFRAME
7621 daddu ra, ra, (14 * 128) # Addr of primary handler.
7622 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7623
7624/* ------------------------------ */
7625 .balign 128
7626.L_ALT_op_return: /* 0x0f */
7627/* File: mips64/alt_stub.S */
7628/*
7629 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7630 * any interesting requests and then jump to the real instruction
7631 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7632 */
7633 .extern MterpCheckBefore
7634 EXPORT_PC
7635 REFRESH_IBASE
7636 dla ra, artMterpAsmInstructionStart
7637 dla t9, MterpCheckBefore
7638 move a0, rSELF
7639 daddu a1, rFP, OFF_FP_SHADOWFRAME
7640 daddu ra, ra, (15 * 128) # Addr of primary handler.
7641 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7642
7643/* ------------------------------ */
7644 .balign 128
7645.L_ALT_op_return_wide: /* 0x10 */
7646/* File: mips64/alt_stub.S */
7647/*
7648 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7649 * any interesting requests and then jump to the real instruction
7650 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7651 */
7652 .extern MterpCheckBefore
7653 EXPORT_PC
7654 REFRESH_IBASE
7655 dla ra, artMterpAsmInstructionStart
7656 dla t9, MterpCheckBefore
7657 move a0, rSELF
7658 daddu a1, rFP, OFF_FP_SHADOWFRAME
7659 daddu ra, ra, (16 * 128) # Addr of primary handler.
7660 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7661
7662/* ------------------------------ */
7663 .balign 128
7664.L_ALT_op_return_object: /* 0x11 */
7665/* File: mips64/alt_stub.S */
7666/*
7667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7668 * any interesting requests and then jump to the real instruction
7669 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7670 */
7671 .extern MterpCheckBefore
7672 EXPORT_PC
7673 REFRESH_IBASE
7674 dla ra, artMterpAsmInstructionStart
7675 dla t9, MterpCheckBefore
7676 move a0, rSELF
7677 daddu a1, rFP, OFF_FP_SHADOWFRAME
7678 daddu ra, ra, (17 * 128) # Addr of primary handler.
7679 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7680
7681/* ------------------------------ */
7682 .balign 128
7683.L_ALT_op_const_4: /* 0x12 */
7684/* File: mips64/alt_stub.S */
7685/*
7686 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7687 * any interesting requests and then jump to the real instruction
7688 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7689 */
7690 .extern MterpCheckBefore
7691 EXPORT_PC
7692 REFRESH_IBASE
7693 dla ra, artMterpAsmInstructionStart
7694 dla t9, MterpCheckBefore
7695 move a0, rSELF
7696 daddu a1, rFP, OFF_FP_SHADOWFRAME
7697 daddu ra, ra, (18 * 128) # Addr of primary handler.
7698 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7699
7700/* ------------------------------ */
7701 .balign 128
7702.L_ALT_op_const_16: /* 0x13 */
7703/* File: mips64/alt_stub.S */
7704/*
7705 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7706 * any interesting requests and then jump to the real instruction
7707 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7708 */
7709 .extern MterpCheckBefore
7710 EXPORT_PC
7711 REFRESH_IBASE
7712 dla ra, artMterpAsmInstructionStart
7713 dla t9, MterpCheckBefore
7714 move a0, rSELF
7715 daddu a1, rFP, OFF_FP_SHADOWFRAME
7716 daddu ra, ra, (19 * 128) # Addr of primary handler.
7717 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7718
7719/* ------------------------------ */
7720 .balign 128
7721.L_ALT_op_const: /* 0x14 */
7722/* File: mips64/alt_stub.S */
7723/*
7724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7725 * any interesting requests and then jump to the real instruction
7726 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7727 */
7728 .extern MterpCheckBefore
7729 EXPORT_PC
7730 REFRESH_IBASE
7731 dla ra, artMterpAsmInstructionStart
7732 dla t9, MterpCheckBefore
7733 move a0, rSELF
7734 daddu a1, rFP, OFF_FP_SHADOWFRAME
7735 daddu ra, ra, (20 * 128) # Addr of primary handler.
7736 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7737
7738/* ------------------------------ */
7739 .balign 128
7740.L_ALT_op_const_high16: /* 0x15 */
7741/* File: mips64/alt_stub.S */
7742/*
7743 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7744 * any interesting requests and then jump to the real instruction
7745 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7746 */
7747 .extern MterpCheckBefore
7748 EXPORT_PC
7749 REFRESH_IBASE
7750 dla ra, artMterpAsmInstructionStart
7751 dla t9, MterpCheckBefore
7752 move a0, rSELF
7753 daddu a1, rFP, OFF_FP_SHADOWFRAME
7754 daddu ra, ra, (21 * 128) # Addr of primary handler.
7755 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7756
7757/* ------------------------------ */
7758 .balign 128
7759.L_ALT_op_const_wide_16: /* 0x16 */
7760/* File: mips64/alt_stub.S */
7761/*
7762 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7763 * any interesting requests and then jump to the real instruction
7764 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7765 */
7766 .extern MterpCheckBefore
7767 EXPORT_PC
7768 REFRESH_IBASE
7769 dla ra, artMterpAsmInstructionStart
7770 dla t9, MterpCheckBefore
7771 move a0, rSELF
7772 daddu a1, rFP, OFF_FP_SHADOWFRAME
7773 daddu ra, ra, (22 * 128) # Addr of primary handler.
7774 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7775
7776/* ------------------------------ */
7777 .balign 128
7778.L_ALT_op_const_wide_32: /* 0x17 */
7779/* File: mips64/alt_stub.S */
7780/*
7781 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7782 * any interesting requests and then jump to the real instruction
7783 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7784 */
7785 .extern MterpCheckBefore
7786 EXPORT_PC
7787 REFRESH_IBASE
7788 dla ra, artMterpAsmInstructionStart
7789 dla t9, MterpCheckBefore
7790 move a0, rSELF
7791 daddu a1, rFP, OFF_FP_SHADOWFRAME
7792 daddu ra, ra, (23 * 128) # Addr of primary handler.
7793 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7794
7795/* ------------------------------ */
7796 .balign 128
7797.L_ALT_op_const_wide: /* 0x18 */
7798/* File: mips64/alt_stub.S */
7799/*
7800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7801 * any interesting requests and then jump to the real instruction
7802 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7803 */
7804 .extern MterpCheckBefore
7805 EXPORT_PC
7806 REFRESH_IBASE
7807 dla ra, artMterpAsmInstructionStart
7808 dla t9, MterpCheckBefore
7809 move a0, rSELF
7810 daddu a1, rFP, OFF_FP_SHADOWFRAME
7811 daddu ra, ra, (24 * 128) # Addr of primary handler.
7812 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7813
7814/* ------------------------------ */
7815 .balign 128
7816.L_ALT_op_const_wide_high16: /* 0x19 */
7817/* File: mips64/alt_stub.S */
7818/*
7819 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7820 * any interesting requests and then jump to the real instruction
7821 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7822 */
7823 .extern MterpCheckBefore
7824 EXPORT_PC
7825 REFRESH_IBASE
7826 dla ra, artMterpAsmInstructionStart
7827 dla t9, MterpCheckBefore
7828 move a0, rSELF
7829 daddu a1, rFP, OFF_FP_SHADOWFRAME
7830 daddu ra, ra, (25 * 128) # Addr of primary handler.
7831 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7832
7833/* ------------------------------ */
7834 .balign 128
7835.L_ALT_op_const_string: /* 0x1a */
7836/* File: mips64/alt_stub.S */
7837/*
7838 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7839 * any interesting requests and then jump to the real instruction
7840 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7841 */
7842 .extern MterpCheckBefore
7843 EXPORT_PC
7844 REFRESH_IBASE
7845 dla ra, artMterpAsmInstructionStart
7846 dla t9, MterpCheckBefore
7847 move a0, rSELF
7848 daddu a1, rFP, OFF_FP_SHADOWFRAME
7849 daddu ra, ra, (26 * 128) # Addr of primary handler.
7850 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7851
7852/* ------------------------------ */
7853 .balign 128
7854.L_ALT_op_const_string_jumbo: /* 0x1b */
7855/* File: mips64/alt_stub.S */
7856/*
7857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7858 * any interesting requests and then jump to the real instruction
7859 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7860 */
7861 .extern MterpCheckBefore
7862 EXPORT_PC
7863 REFRESH_IBASE
7864 dla ra, artMterpAsmInstructionStart
7865 dla t9, MterpCheckBefore
7866 move a0, rSELF
7867 daddu a1, rFP, OFF_FP_SHADOWFRAME
7868 daddu ra, ra, (27 * 128) # Addr of primary handler.
7869 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7870
7871/* ------------------------------ */
7872 .balign 128
7873.L_ALT_op_const_class: /* 0x1c */
7874/* File: mips64/alt_stub.S */
7875/*
7876 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7877 * any interesting requests and then jump to the real instruction
7878 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7879 */
7880 .extern MterpCheckBefore
7881 EXPORT_PC
7882 REFRESH_IBASE
7883 dla ra, artMterpAsmInstructionStart
7884 dla t9, MterpCheckBefore
7885 move a0, rSELF
7886 daddu a1, rFP, OFF_FP_SHADOWFRAME
7887 daddu ra, ra, (28 * 128) # Addr of primary handler.
7888 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7889
7890/* ------------------------------ */
7891 .balign 128
7892.L_ALT_op_monitor_enter: /* 0x1d */
7893/* File: mips64/alt_stub.S */
7894/*
7895 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7896 * any interesting requests and then jump to the real instruction
7897 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7898 */
7899 .extern MterpCheckBefore
7900 EXPORT_PC
7901 REFRESH_IBASE
7902 dla ra, artMterpAsmInstructionStart
7903 dla t9, MterpCheckBefore
7904 move a0, rSELF
7905 daddu a1, rFP, OFF_FP_SHADOWFRAME
7906 daddu ra, ra, (29 * 128) # Addr of primary handler.
7907 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7908
7909/* ------------------------------ */
7910 .balign 128
7911.L_ALT_op_monitor_exit: /* 0x1e */
7912/* File: mips64/alt_stub.S */
7913/*
7914 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7915 * any interesting requests and then jump to the real instruction
7916 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7917 */
7918 .extern MterpCheckBefore
7919 EXPORT_PC
7920 REFRESH_IBASE
7921 dla ra, artMterpAsmInstructionStart
7922 dla t9, MterpCheckBefore
7923 move a0, rSELF
7924 daddu a1, rFP, OFF_FP_SHADOWFRAME
7925 daddu ra, ra, (30 * 128) # Addr of primary handler.
7926 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7927
7928/* ------------------------------ */
7929 .balign 128
7930.L_ALT_op_check_cast: /* 0x1f */
7931/* File: mips64/alt_stub.S */
7932/*
7933 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7934 * any interesting requests and then jump to the real instruction
7935 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7936 */
7937 .extern MterpCheckBefore
7938 EXPORT_PC
7939 REFRESH_IBASE
7940 dla ra, artMterpAsmInstructionStart
7941 dla t9, MterpCheckBefore
7942 move a0, rSELF
7943 daddu a1, rFP, OFF_FP_SHADOWFRAME
7944 daddu ra, ra, (31 * 128) # Addr of primary handler.
7945 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7946
7947/* ------------------------------ */
7948 .balign 128
7949.L_ALT_op_instance_of: /* 0x20 */
7950/* File: mips64/alt_stub.S */
7951/*
7952 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7953 * any interesting requests and then jump to the real instruction
7954 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7955 */
7956 .extern MterpCheckBefore
7957 EXPORT_PC
7958 REFRESH_IBASE
7959 dla ra, artMterpAsmInstructionStart
7960 dla t9, MterpCheckBefore
7961 move a0, rSELF
7962 daddu a1, rFP, OFF_FP_SHADOWFRAME
7963 daddu ra, ra, (32 * 128) # Addr of primary handler.
7964 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7965
7966/* ------------------------------ */
7967 .balign 128
7968.L_ALT_op_array_length: /* 0x21 */
7969/* File: mips64/alt_stub.S */
7970/*
7971 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7972 * any interesting requests and then jump to the real instruction
7973 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7974 */
7975 .extern MterpCheckBefore
7976 EXPORT_PC
7977 REFRESH_IBASE
7978 dla ra, artMterpAsmInstructionStart
7979 dla t9, MterpCheckBefore
7980 move a0, rSELF
7981 daddu a1, rFP, OFF_FP_SHADOWFRAME
7982 daddu ra, ra, (33 * 128) # Addr of primary handler.
7983 jalr zero, t9 # (self, shadow_frame) Note: tail call.
7984
7985/* ------------------------------ */
7986 .balign 128
7987.L_ALT_op_new_instance: /* 0x22 */
7988/* File: mips64/alt_stub.S */
7989/*
7990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
7991 * any interesting requests and then jump to the real instruction
7992 * handler. Note that the call to MterpCheckBefore is done as a tail call.
7993 */
7994 .extern MterpCheckBefore
7995 EXPORT_PC
7996 REFRESH_IBASE
7997 dla ra, artMterpAsmInstructionStart
7998 dla t9, MterpCheckBefore
7999 move a0, rSELF
8000 daddu a1, rFP, OFF_FP_SHADOWFRAME
8001 daddu ra, ra, (34 * 128) # Addr of primary handler.
8002 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8003
8004/* ------------------------------ */
8005 .balign 128
8006.L_ALT_op_new_array: /* 0x23 */
8007/* File: mips64/alt_stub.S */
8008/*
8009 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8010 * any interesting requests and then jump to the real instruction
8011 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8012 */
8013 .extern MterpCheckBefore
8014 EXPORT_PC
8015 REFRESH_IBASE
8016 dla ra, artMterpAsmInstructionStart
8017 dla t9, MterpCheckBefore
8018 move a0, rSELF
8019 daddu a1, rFP, OFF_FP_SHADOWFRAME
8020 daddu ra, ra, (35 * 128) # Addr of primary handler.
8021 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8022
8023/* ------------------------------ */
8024 .balign 128
8025.L_ALT_op_filled_new_array: /* 0x24 */
8026/* File: mips64/alt_stub.S */
8027/*
8028 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8029 * any interesting requests and then jump to the real instruction
8030 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8031 */
8032 .extern MterpCheckBefore
8033 EXPORT_PC
8034 REFRESH_IBASE
8035 dla ra, artMterpAsmInstructionStart
8036 dla t9, MterpCheckBefore
8037 move a0, rSELF
8038 daddu a1, rFP, OFF_FP_SHADOWFRAME
8039 daddu ra, ra, (36 * 128) # Addr of primary handler.
8040 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8041
8042/* ------------------------------ */
8043 .balign 128
8044.L_ALT_op_filled_new_array_range: /* 0x25 */
8045/* File: mips64/alt_stub.S */
8046/*
8047 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8048 * any interesting requests and then jump to the real instruction
8049 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8050 */
8051 .extern MterpCheckBefore
8052 EXPORT_PC
8053 REFRESH_IBASE
8054 dla ra, artMterpAsmInstructionStart
8055 dla t9, MterpCheckBefore
8056 move a0, rSELF
8057 daddu a1, rFP, OFF_FP_SHADOWFRAME
8058 daddu ra, ra, (37 * 128) # Addr of primary handler.
8059 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8060
8061/* ------------------------------ */
8062 .balign 128
8063.L_ALT_op_fill_array_data: /* 0x26 */
8064/* File: mips64/alt_stub.S */
8065/*
8066 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8067 * any interesting requests and then jump to the real instruction
8068 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8069 */
8070 .extern MterpCheckBefore
8071 EXPORT_PC
8072 REFRESH_IBASE
8073 dla ra, artMterpAsmInstructionStart
8074 dla t9, MterpCheckBefore
8075 move a0, rSELF
8076 daddu a1, rFP, OFF_FP_SHADOWFRAME
8077 daddu ra, ra, (38 * 128) # Addr of primary handler.
8078 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8079
8080/* ------------------------------ */
8081 .balign 128
8082.L_ALT_op_throw: /* 0x27 */
8083/* File: mips64/alt_stub.S */
8084/*
8085 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8086 * any interesting requests and then jump to the real instruction
8087 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8088 */
8089 .extern MterpCheckBefore
8090 EXPORT_PC
8091 REFRESH_IBASE
8092 dla ra, artMterpAsmInstructionStart
8093 dla t9, MterpCheckBefore
8094 move a0, rSELF
8095 daddu a1, rFP, OFF_FP_SHADOWFRAME
8096 daddu ra, ra, (39 * 128) # Addr of primary handler.
8097 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8098
8099/* ------------------------------ */
8100 .balign 128
8101.L_ALT_op_goto: /* 0x28 */
8102/* File: mips64/alt_stub.S */
8103/*
8104 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8105 * any interesting requests and then jump to the real instruction
8106 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8107 */
8108 .extern MterpCheckBefore
8109 EXPORT_PC
8110 REFRESH_IBASE
8111 dla ra, artMterpAsmInstructionStart
8112 dla t9, MterpCheckBefore
8113 move a0, rSELF
8114 daddu a1, rFP, OFF_FP_SHADOWFRAME
8115 daddu ra, ra, (40 * 128) # Addr of primary handler.
8116 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8117
8118/* ------------------------------ */
8119 .balign 128
8120.L_ALT_op_goto_16: /* 0x29 */
8121/* File: mips64/alt_stub.S */
8122/*
8123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8124 * any interesting requests and then jump to the real instruction
8125 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8126 */
8127 .extern MterpCheckBefore
8128 EXPORT_PC
8129 REFRESH_IBASE
8130 dla ra, artMterpAsmInstructionStart
8131 dla t9, MterpCheckBefore
8132 move a0, rSELF
8133 daddu a1, rFP, OFF_FP_SHADOWFRAME
8134 daddu ra, ra, (41 * 128) # Addr of primary handler.
8135 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8136
8137/* ------------------------------ */
8138 .balign 128
8139.L_ALT_op_goto_32: /* 0x2a */
8140/* File: mips64/alt_stub.S */
8141/*
8142 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8143 * any interesting requests and then jump to the real instruction
8144 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8145 */
8146 .extern MterpCheckBefore
8147 EXPORT_PC
8148 REFRESH_IBASE
8149 dla ra, artMterpAsmInstructionStart
8150 dla t9, MterpCheckBefore
8151 move a0, rSELF
8152 daddu a1, rFP, OFF_FP_SHADOWFRAME
8153 daddu ra, ra, (42 * 128) # Addr of primary handler.
8154 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8155
8156/* ------------------------------ */
8157 .balign 128
8158.L_ALT_op_packed_switch: /* 0x2b */
8159/* File: mips64/alt_stub.S */
8160/*
8161 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8162 * any interesting requests and then jump to the real instruction
8163 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8164 */
8165 .extern MterpCheckBefore
8166 EXPORT_PC
8167 REFRESH_IBASE
8168 dla ra, artMterpAsmInstructionStart
8169 dla t9, MterpCheckBefore
8170 move a0, rSELF
8171 daddu a1, rFP, OFF_FP_SHADOWFRAME
8172 daddu ra, ra, (43 * 128) # Addr of primary handler.
8173 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8174
8175/* ------------------------------ */
8176 .balign 128
8177.L_ALT_op_sparse_switch: /* 0x2c */
8178/* File: mips64/alt_stub.S */
8179/*
8180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8181 * any interesting requests and then jump to the real instruction
8182 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8183 */
8184 .extern MterpCheckBefore
8185 EXPORT_PC
8186 REFRESH_IBASE
8187 dla ra, artMterpAsmInstructionStart
8188 dla t9, MterpCheckBefore
8189 move a0, rSELF
8190 daddu a1, rFP, OFF_FP_SHADOWFRAME
8191 daddu ra, ra, (44 * 128) # Addr of primary handler.
8192 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8193
8194/* ------------------------------ */
8195 .balign 128
8196.L_ALT_op_cmpl_float: /* 0x2d */
8197/* File: mips64/alt_stub.S */
8198/*
8199 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8200 * any interesting requests and then jump to the real instruction
8201 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8202 */
8203 .extern MterpCheckBefore
8204 EXPORT_PC
8205 REFRESH_IBASE
8206 dla ra, artMterpAsmInstructionStart
8207 dla t9, MterpCheckBefore
8208 move a0, rSELF
8209 daddu a1, rFP, OFF_FP_SHADOWFRAME
8210 daddu ra, ra, (45 * 128) # Addr of primary handler.
8211 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8212
8213/* ------------------------------ */
8214 .balign 128
8215.L_ALT_op_cmpg_float: /* 0x2e */
8216/* File: mips64/alt_stub.S */
8217/*
8218 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8219 * any interesting requests and then jump to the real instruction
8220 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8221 */
8222 .extern MterpCheckBefore
8223 EXPORT_PC
8224 REFRESH_IBASE
8225 dla ra, artMterpAsmInstructionStart
8226 dla t9, MterpCheckBefore
8227 move a0, rSELF
8228 daddu a1, rFP, OFF_FP_SHADOWFRAME
8229 daddu ra, ra, (46 * 128) # Addr of primary handler.
8230 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8231
8232/* ------------------------------ */
8233 .balign 128
8234.L_ALT_op_cmpl_double: /* 0x2f */
8235/* File: mips64/alt_stub.S */
8236/*
8237 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8238 * any interesting requests and then jump to the real instruction
8239 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8240 */
8241 .extern MterpCheckBefore
8242 EXPORT_PC
8243 REFRESH_IBASE
8244 dla ra, artMterpAsmInstructionStart
8245 dla t9, MterpCheckBefore
8246 move a0, rSELF
8247 daddu a1, rFP, OFF_FP_SHADOWFRAME
8248 daddu ra, ra, (47 * 128) # Addr of primary handler.
8249 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8250
8251/* ------------------------------ */
8252 .balign 128
8253.L_ALT_op_cmpg_double: /* 0x30 */
8254/* File: mips64/alt_stub.S */
8255/*
8256 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8257 * any interesting requests and then jump to the real instruction
8258 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8259 */
8260 .extern MterpCheckBefore
8261 EXPORT_PC
8262 REFRESH_IBASE
8263 dla ra, artMterpAsmInstructionStart
8264 dla t9, MterpCheckBefore
8265 move a0, rSELF
8266 daddu a1, rFP, OFF_FP_SHADOWFRAME
8267 daddu ra, ra, (48 * 128) # Addr of primary handler.
8268 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8269
8270/* ------------------------------ */
8271 .balign 128
8272.L_ALT_op_cmp_long: /* 0x31 */
8273/* File: mips64/alt_stub.S */
8274/*
8275 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8276 * any interesting requests and then jump to the real instruction
8277 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8278 */
8279 .extern MterpCheckBefore
8280 EXPORT_PC
8281 REFRESH_IBASE
8282 dla ra, artMterpAsmInstructionStart
8283 dla t9, MterpCheckBefore
8284 move a0, rSELF
8285 daddu a1, rFP, OFF_FP_SHADOWFRAME
8286 daddu ra, ra, (49 * 128) # Addr of primary handler.
8287 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8288
8289/* ------------------------------ */
8290 .balign 128
8291.L_ALT_op_if_eq: /* 0x32 */
8292/* File: mips64/alt_stub.S */
8293/*
8294 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8295 * any interesting requests and then jump to the real instruction
8296 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8297 */
8298 .extern MterpCheckBefore
8299 EXPORT_PC
8300 REFRESH_IBASE
8301 dla ra, artMterpAsmInstructionStart
8302 dla t9, MterpCheckBefore
8303 move a0, rSELF
8304 daddu a1, rFP, OFF_FP_SHADOWFRAME
8305 daddu ra, ra, (50 * 128) # Addr of primary handler.
8306 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8307
8308/* ------------------------------ */
8309 .balign 128
8310.L_ALT_op_if_ne: /* 0x33 */
8311/* File: mips64/alt_stub.S */
8312/*
8313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8314 * any interesting requests and then jump to the real instruction
8315 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8316 */
8317 .extern MterpCheckBefore
8318 EXPORT_PC
8319 REFRESH_IBASE
8320 dla ra, artMterpAsmInstructionStart
8321 dla t9, MterpCheckBefore
8322 move a0, rSELF
8323 daddu a1, rFP, OFF_FP_SHADOWFRAME
8324 daddu ra, ra, (51 * 128) # Addr of primary handler.
8325 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8326
8327/* ------------------------------ */
8328 .balign 128
8329.L_ALT_op_if_lt: /* 0x34 */
8330/* File: mips64/alt_stub.S */
8331/*
8332 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8333 * any interesting requests and then jump to the real instruction
8334 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8335 */
8336 .extern MterpCheckBefore
8337 EXPORT_PC
8338 REFRESH_IBASE
8339 dla ra, artMterpAsmInstructionStart
8340 dla t9, MterpCheckBefore
8341 move a0, rSELF
8342 daddu a1, rFP, OFF_FP_SHADOWFRAME
8343 daddu ra, ra, (52 * 128) # Addr of primary handler.
8344 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8345
8346/* ------------------------------ */
8347 .balign 128
8348.L_ALT_op_if_ge: /* 0x35 */
8349/* File: mips64/alt_stub.S */
8350/*
8351 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8352 * any interesting requests and then jump to the real instruction
8353 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8354 */
8355 .extern MterpCheckBefore
8356 EXPORT_PC
8357 REFRESH_IBASE
8358 dla ra, artMterpAsmInstructionStart
8359 dla t9, MterpCheckBefore
8360 move a0, rSELF
8361 daddu a1, rFP, OFF_FP_SHADOWFRAME
8362 daddu ra, ra, (53 * 128) # Addr of primary handler.
8363 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8364
8365/* ------------------------------ */
8366 .balign 128
8367.L_ALT_op_if_gt: /* 0x36 */
8368/* File: mips64/alt_stub.S */
8369/*
8370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8371 * any interesting requests and then jump to the real instruction
8372 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8373 */
8374 .extern MterpCheckBefore
8375 EXPORT_PC
8376 REFRESH_IBASE
8377 dla ra, artMterpAsmInstructionStart
8378 dla t9, MterpCheckBefore
8379 move a0, rSELF
8380 daddu a1, rFP, OFF_FP_SHADOWFRAME
8381 daddu ra, ra, (54 * 128) # Addr of primary handler.
8382 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8383
8384/* ------------------------------ */
8385 .balign 128
8386.L_ALT_op_if_le: /* 0x37 */
8387/* File: mips64/alt_stub.S */
8388/*
8389 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8390 * any interesting requests and then jump to the real instruction
8391 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8392 */
8393 .extern MterpCheckBefore
8394 EXPORT_PC
8395 REFRESH_IBASE
8396 dla ra, artMterpAsmInstructionStart
8397 dla t9, MterpCheckBefore
8398 move a0, rSELF
8399 daddu a1, rFP, OFF_FP_SHADOWFRAME
8400 daddu ra, ra, (55 * 128) # Addr of primary handler.
8401 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8402
8403/* ------------------------------ */
8404 .balign 128
8405.L_ALT_op_if_eqz: /* 0x38 */
8406/* File: mips64/alt_stub.S */
8407/*
8408 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8409 * any interesting requests and then jump to the real instruction
8410 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8411 */
8412 .extern MterpCheckBefore
8413 EXPORT_PC
8414 REFRESH_IBASE
8415 dla ra, artMterpAsmInstructionStart
8416 dla t9, MterpCheckBefore
8417 move a0, rSELF
8418 daddu a1, rFP, OFF_FP_SHADOWFRAME
8419 daddu ra, ra, (56 * 128) # Addr of primary handler.
8420 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8421
8422/* ------------------------------ */
8423 .balign 128
8424.L_ALT_op_if_nez: /* 0x39 */
8425/* File: mips64/alt_stub.S */
8426/*
8427 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8428 * any interesting requests and then jump to the real instruction
8429 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8430 */
8431 .extern MterpCheckBefore
8432 EXPORT_PC
8433 REFRESH_IBASE
8434 dla ra, artMterpAsmInstructionStart
8435 dla t9, MterpCheckBefore
8436 move a0, rSELF
8437 daddu a1, rFP, OFF_FP_SHADOWFRAME
8438 daddu ra, ra, (57 * 128) # Addr of primary handler.
8439 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8440
8441/* ------------------------------ */
8442 .balign 128
8443.L_ALT_op_if_ltz: /* 0x3a */
8444/* File: mips64/alt_stub.S */
8445/*
8446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8447 * any interesting requests and then jump to the real instruction
8448 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8449 */
8450 .extern MterpCheckBefore
8451 EXPORT_PC
8452 REFRESH_IBASE
8453 dla ra, artMterpAsmInstructionStart
8454 dla t9, MterpCheckBefore
8455 move a0, rSELF
8456 daddu a1, rFP, OFF_FP_SHADOWFRAME
8457 daddu ra, ra, (58 * 128) # Addr of primary handler.
8458 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8459
8460/* ------------------------------ */
8461 .balign 128
8462.L_ALT_op_if_gez: /* 0x3b */
8463/* File: mips64/alt_stub.S */
8464/*
8465 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8466 * any interesting requests and then jump to the real instruction
8467 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8468 */
8469 .extern MterpCheckBefore
8470 EXPORT_PC
8471 REFRESH_IBASE
8472 dla ra, artMterpAsmInstructionStart
8473 dla t9, MterpCheckBefore
8474 move a0, rSELF
8475 daddu a1, rFP, OFF_FP_SHADOWFRAME
8476 daddu ra, ra, (59 * 128) # Addr of primary handler.
8477 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8478
8479/* ------------------------------ */
8480 .balign 128
8481.L_ALT_op_if_gtz: /* 0x3c */
8482/* File: mips64/alt_stub.S */
8483/*
8484 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8485 * any interesting requests and then jump to the real instruction
8486 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8487 */
8488 .extern MterpCheckBefore
8489 EXPORT_PC
8490 REFRESH_IBASE
8491 dla ra, artMterpAsmInstructionStart
8492 dla t9, MterpCheckBefore
8493 move a0, rSELF
8494 daddu a1, rFP, OFF_FP_SHADOWFRAME
8495 daddu ra, ra, (60 * 128) # Addr of primary handler.
8496 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8497
8498/* ------------------------------ */
8499 .balign 128
8500.L_ALT_op_if_lez: /* 0x3d */
8501/* File: mips64/alt_stub.S */
8502/*
8503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8504 * any interesting requests and then jump to the real instruction
8505 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8506 */
8507 .extern MterpCheckBefore
8508 EXPORT_PC
8509 REFRESH_IBASE
8510 dla ra, artMterpAsmInstructionStart
8511 dla t9, MterpCheckBefore
8512 move a0, rSELF
8513 daddu a1, rFP, OFF_FP_SHADOWFRAME
8514 daddu ra, ra, (61 * 128) # Addr of primary handler.
8515 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8516
8517/* ------------------------------ */
8518 .balign 128
8519.L_ALT_op_unused_3e: /* 0x3e */
8520/* File: mips64/alt_stub.S */
8521/*
8522 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8523 * any interesting requests and then jump to the real instruction
8524 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8525 */
8526 .extern MterpCheckBefore
8527 EXPORT_PC
8528 REFRESH_IBASE
8529 dla ra, artMterpAsmInstructionStart
8530 dla t9, MterpCheckBefore
8531 move a0, rSELF
8532 daddu a1, rFP, OFF_FP_SHADOWFRAME
8533 daddu ra, ra, (62 * 128) # Addr of primary handler.
8534 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8535
8536/* ------------------------------ */
8537 .balign 128
8538.L_ALT_op_unused_3f: /* 0x3f */
8539/* File: mips64/alt_stub.S */
8540/*
8541 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8542 * any interesting requests and then jump to the real instruction
8543 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8544 */
8545 .extern MterpCheckBefore
8546 EXPORT_PC
8547 REFRESH_IBASE
8548 dla ra, artMterpAsmInstructionStart
8549 dla t9, MterpCheckBefore
8550 move a0, rSELF
8551 daddu a1, rFP, OFF_FP_SHADOWFRAME
8552 daddu ra, ra, (63 * 128) # Addr of primary handler.
8553 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8554
8555/* ------------------------------ */
8556 .balign 128
8557.L_ALT_op_unused_40: /* 0x40 */
8558/* File: mips64/alt_stub.S */
8559/*
8560 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8561 * any interesting requests and then jump to the real instruction
8562 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8563 */
8564 .extern MterpCheckBefore
8565 EXPORT_PC
8566 REFRESH_IBASE
8567 dla ra, artMterpAsmInstructionStart
8568 dla t9, MterpCheckBefore
8569 move a0, rSELF
8570 daddu a1, rFP, OFF_FP_SHADOWFRAME
8571 daddu ra, ra, (64 * 128) # Addr of primary handler.
8572 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8573
8574/* ------------------------------ */
8575 .balign 128
8576.L_ALT_op_unused_41: /* 0x41 */
8577/* File: mips64/alt_stub.S */
8578/*
8579 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8580 * any interesting requests and then jump to the real instruction
8581 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8582 */
8583 .extern MterpCheckBefore
8584 EXPORT_PC
8585 REFRESH_IBASE
8586 dla ra, artMterpAsmInstructionStart
8587 dla t9, MterpCheckBefore
8588 move a0, rSELF
8589 daddu a1, rFP, OFF_FP_SHADOWFRAME
8590 daddu ra, ra, (65 * 128) # Addr of primary handler.
8591 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8592
8593/* ------------------------------ */
8594 .balign 128
8595.L_ALT_op_unused_42: /* 0x42 */
8596/* File: mips64/alt_stub.S */
8597/*
8598 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8599 * any interesting requests and then jump to the real instruction
8600 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8601 */
8602 .extern MterpCheckBefore
8603 EXPORT_PC
8604 REFRESH_IBASE
8605 dla ra, artMterpAsmInstructionStart
8606 dla t9, MterpCheckBefore
8607 move a0, rSELF
8608 daddu a1, rFP, OFF_FP_SHADOWFRAME
8609 daddu ra, ra, (66 * 128) # Addr of primary handler.
8610 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8611
8612/* ------------------------------ */
8613 .balign 128
8614.L_ALT_op_unused_43: /* 0x43 */
8615/* File: mips64/alt_stub.S */
8616/*
8617 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8618 * any interesting requests and then jump to the real instruction
8619 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8620 */
8621 .extern MterpCheckBefore
8622 EXPORT_PC
8623 REFRESH_IBASE
8624 dla ra, artMterpAsmInstructionStart
8625 dla t9, MterpCheckBefore
8626 move a0, rSELF
8627 daddu a1, rFP, OFF_FP_SHADOWFRAME
8628 daddu ra, ra, (67 * 128) # Addr of primary handler.
8629 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8630
8631/* ------------------------------ */
8632 .balign 128
8633.L_ALT_op_aget: /* 0x44 */
8634/* File: mips64/alt_stub.S */
8635/*
8636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8637 * any interesting requests and then jump to the real instruction
8638 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8639 */
8640 .extern MterpCheckBefore
8641 EXPORT_PC
8642 REFRESH_IBASE
8643 dla ra, artMterpAsmInstructionStart
8644 dla t9, MterpCheckBefore
8645 move a0, rSELF
8646 daddu a1, rFP, OFF_FP_SHADOWFRAME
8647 daddu ra, ra, (68 * 128) # Addr of primary handler.
8648 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8649
8650/* ------------------------------ */
8651 .balign 128
8652.L_ALT_op_aget_wide: /* 0x45 */
8653/* File: mips64/alt_stub.S */
8654/*
8655 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8656 * any interesting requests and then jump to the real instruction
8657 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8658 */
8659 .extern MterpCheckBefore
8660 EXPORT_PC
8661 REFRESH_IBASE
8662 dla ra, artMterpAsmInstructionStart
8663 dla t9, MterpCheckBefore
8664 move a0, rSELF
8665 daddu a1, rFP, OFF_FP_SHADOWFRAME
8666 daddu ra, ra, (69 * 128) # Addr of primary handler.
8667 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8668
8669/* ------------------------------ */
8670 .balign 128
8671.L_ALT_op_aget_object: /* 0x46 */
8672/* File: mips64/alt_stub.S */
8673/*
8674 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8675 * any interesting requests and then jump to the real instruction
8676 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8677 */
8678 .extern MterpCheckBefore
8679 EXPORT_PC
8680 REFRESH_IBASE
8681 dla ra, artMterpAsmInstructionStart
8682 dla t9, MterpCheckBefore
8683 move a0, rSELF
8684 daddu a1, rFP, OFF_FP_SHADOWFRAME
8685 daddu ra, ra, (70 * 128) # Addr of primary handler.
8686 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8687
8688/* ------------------------------ */
8689 .balign 128
8690.L_ALT_op_aget_boolean: /* 0x47 */
8691/* File: mips64/alt_stub.S */
8692/*
8693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8694 * any interesting requests and then jump to the real instruction
8695 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8696 */
8697 .extern MterpCheckBefore
8698 EXPORT_PC
8699 REFRESH_IBASE
8700 dla ra, artMterpAsmInstructionStart
8701 dla t9, MterpCheckBefore
8702 move a0, rSELF
8703 daddu a1, rFP, OFF_FP_SHADOWFRAME
8704 daddu ra, ra, (71 * 128) # Addr of primary handler.
8705 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8706
8707/* ------------------------------ */
8708 .balign 128
8709.L_ALT_op_aget_byte: /* 0x48 */
8710/* File: mips64/alt_stub.S */
8711/*
8712 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8713 * any interesting requests and then jump to the real instruction
8714 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8715 */
8716 .extern MterpCheckBefore
8717 EXPORT_PC
8718 REFRESH_IBASE
8719 dla ra, artMterpAsmInstructionStart
8720 dla t9, MterpCheckBefore
8721 move a0, rSELF
8722 daddu a1, rFP, OFF_FP_SHADOWFRAME
8723 daddu ra, ra, (72 * 128) # Addr of primary handler.
8724 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8725
8726/* ------------------------------ */
8727 .balign 128
8728.L_ALT_op_aget_char: /* 0x49 */
8729/* File: mips64/alt_stub.S */
8730/*
8731 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8732 * any interesting requests and then jump to the real instruction
8733 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8734 */
8735 .extern MterpCheckBefore
8736 EXPORT_PC
8737 REFRESH_IBASE
8738 dla ra, artMterpAsmInstructionStart
8739 dla t9, MterpCheckBefore
8740 move a0, rSELF
8741 daddu a1, rFP, OFF_FP_SHADOWFRAME
8742 daddu ra, ra, (73 * 128) # Addr of primary handler.
8743 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8744
8745/* ------------------------------ */
8746 .balign 128
8747.L_ALT_op_aget_short: /* 0x4a */
8748/* File: mips64/alt_stub.S */
8749/*
8750 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8751 * any interesting requests and then jump to the real instruction
8752 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8753 */
8754 .extern MterpCheckBefore
8755 EXPORT_PC
8756 REFRESH_IBASE
8757 dla ra, artMterpAsmInstructionStart
8758 dla t9, MterpCheckBefore
8759 move a0, rSELF
8760 daddu a1, rFP, OFF_FP_SHADOWFRAME
8761 daddu ra, ra, (74 * 128) # Addr of primary handler.
8762 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8763
8764/* ------------------------------ */
8765 .balign 128
8766.L_ALT_op_aput: /* 0x4b */
8767/* File: mips64/alt_stub.S */
8768/*
8769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8770 * any interesting requests and then jump to the real instruction
8771 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8772 */
8773 .extern MterpCheckBefore
8774 EXPORT_PC
8775 REFRESH_IBASE
8776 dla ra, artMterpAsmInstructionStart
8777 dla t9, MterpCheckBefore
8778 move a0, rSELF
8779 daddu a1, rFP, OFF_FP_SHADOWFRAME
8780 daddu ra, ra, (75 * 128) # Addr of primary handler.
8781 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8782
8783/* ------------------------------ */
8784 .balign 128
8785.L_ALT_op_aput_wide: /* 0x4c */
8786/* File: mips64/alt_stub.S */
8787/*
8788 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8789 * any interesting requests and then jump to the real instruction
8790 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8791 */
8792 .extern MterpCheckBefore
8793 EXPORT_PC
8794 REFRESH_IBASE
8795 dla ra, artMterpAsmInstructionStart
8796 dla t9, MterpCheckBefore
8797 move a0, rSELF
8798 daddu a1, rFP, OFF_FP_SHADOWFRAME
8799 daddu ra, ra, (76 * 128) # Addr of primary handler.
8800 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8801
8802/* ------------------------------ */
8803 .balign 128
8804.L_ALT_op_aput_object: /* 0x4d */
8805/* File: mips64/alt_stub.S */
8806/*
8807 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8808 * any interesting requests and then jump to the real instruction
8809 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8810 */
8811 .extern MterpCheckBefore
8812 EXPORT_PC
8813 REFRESH_IBASE
8814 dla ra, artMterpAsmInstructionStart
8815 dla t9, MterpCheckBefore
8816 move a0, rSELF
8817 daddu a1, rFP, OFF_FP_SHADOWFRAME
8818 daddu ra, ra, (77 * 128) # Addr of primary handler.
8819 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8820
8821/* ------------------------------ */
8822 .balign 128
8823.L_ALT_op_aput_boolean: /* 0x4e */
8824/* File: mips64/alt_stub.S */
8825/*
8826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8827 * any interesting requests and then jump to the real instruction
8828 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8829 */
8830 .extern MterpCheckBefore
8831 EXPORT_PC
8832 REFRESH_IBASE
8833 dla ra, artMterpAsmInstructionStart
8834 dla t9, MterpCheckBefore
8835 move a0, rSELF
8836 daddu a1, rFP, OFF_FP_SHADOWFRAME
8837 daddu ra, ra, (78 * 128) # Addr of primary handler.
8838 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8839
8840/* ------------------------------ */
8841 .balign 128
8842.L_ALT_op_aput_byte: /* 0x4f */
8843/* File: mips64/alt_stub.S */
8844/*
8845 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8846 * any interesting requests and then jump to the real instruction
8847 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8848 */
8849 .extern MterpCheckBefore
8850 EXPORT_PC
8851 REFRESH_IBASE
8852 dla ra, artMterpAsmInstructionStart
8853 dla t9, MterpCheckBefore
8854 move a0, rSELF
8855 daddu a1, rFP, OFF_FP_SHADOWFRAME
8856 daddu ra, ra, (79 * 128) # Addr of primary handler.
8857 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8858
8859/* ------------------------------ */
8860 .balign 128
8861.L_ALT_op_aput_char: /* 0x50 */
8862/* File: mips64/alt_stub.S */
8863/*
8864 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8865 * any interesting requests and then jump to the real instruction
8866 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8867 */
8868 .extern MterpCheckBefore
8869 EXPORT_PC
8870 REFRESH_IBASE
8871 dla ra, artMterpAsmInstructionStart
8872 dla t9, MterpCheckBefore
8873 move a0, rSELF
8874 daddu a1, rFP, OFF_FP_SHADOWFRAME
8875 daddu ra, ra, (80 * 128) # Addr of primary handler.
8876 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8877
8878/* ------------------------------ */
8879 .balign 128
8880.L_ALT_op_aput_short: /* 0x51 */
8881/* File: mips64/alt_stub.S */
8882/*
8883 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8884 * any interesting requests and then jump to the real instruction
8885 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8886 */
8887 .extern MterpCheckBefore
8888 EXPORT_PC
8889 REFRESH_IBASE
8890 dla ra, artMterpAsmInstructionStart
8891 dla t9, MterpCheckBefore
8892 move a0, rSELF
8893 daddu a1, rFP, OFF_FP_SHADOWFRAME
8894 daddu ra, ra, (81 * 128) # Addr of primary handler.
8895 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8896
8897/* ------------------------------ */
8898 .balign 128
8899.L_ALT_op_iget: /* 0x52 */
8900/* File: mips64/alt_stub.S */
8901/*
8902 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8903 * any interesting requests and then jump to the real instruction
8904 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8905 */
8906 .extern MterpCheckBefore
8907 EXPORT_PC
8908 REFRESH_IBASE
8909 dla ra, artMterpAsmInstructionStart
8910 dla t9, MterpCheckBefore
8911 move a0, rSELF
8912 daddu a1, rFP, OFF_FP_SHADOWFRAME
8913 daddu ra, ra, (82 * 128) # Addr of primary handler.
8914 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8915
8916/* ------------------------------ */
8917 .balign 128
8918.L_ALT_op_iget_wide: /* 0x53 */
8919/* File: mips64/alt_stub.S */
8920/*
8921 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8922 * any interesting requests and then jump to the real instruction
8923 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8924 */
8925 .extern MterpCheckBefore
8926 EXPORT_PC
8927 REFRESH_IBASE
8928 dla ra, artMterpAsmInstructionStart
8929 dla t9, MterpCheckBefore
8930 move a0, rSELF
8931 daddu a1, rFP, OFF_FP_SHADOWFRAME
8932 daddu ra, ra, (83 * 128) # Addr of primary handler.
8933 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8934
8935/* ------------------------------ */
8936 .balign 128
8937.L_ALT_op_iget_object: /* 0x54 */
8938/* File: mips64/alt_stub.S */
8939/*
8940 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8941 * any interesting requests and then jump to the real instruction
8942 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8943 */
8944 .extern MterpCheckBefore
8945 EXPORT_PC
8946 REFRESH_IBASE
8947 dla ra, artMterpAsmInstructionStart
8948 dla t9, MterpCheckBefore
8949 move a0, rSELF
8950 daddu a1, rFP, OFF_FP_SHADOWFRAME
8951 daddu ra, ra, (84 * 128) # Addr of primary handler.
8952 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8953
8954/* ------------------------------ */
8955 .balign 128
8956.L_ALT_op_iget_boolean: /* 0x55 */
8957/* File: mips64/alt_stub.S */
8958/*
8959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8960 * any interesting requests and then jump to the real instruction
8961 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8962 */
8963 .extern MterpCheckBefore
8964 EXPORT_PC
8965 REFRESH_IBASE
8966 dla ra, artMterpAsmInstructionStart
8967 dla t9, MterpCheckBefore
8968 move a0, rSELF
8969 daddu a1, rFP, OFF_FP_SHADOWFRAME
8970 daddu ra, ra, (85 * 128) # Addr of primary handler.
8971 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8972
8973/* ------------------------------ */
8974 .balign 128
8975.L_ALT_op_iget_byte: /* 0x56 */
8976/* File: mips64/alt_stub.S */
8977/*
8978 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8979 * any interesting requests and then jump to the real instruction
8980 * handler. Note that the call to MterpCheckBefore is done as a tail call.
8981 */
8982 .extern MterpCheckBefore
8983 EXPORT_PC
8984 REFRESH_IBASE
8985 dla ra, artMterpAsmInstructionStart
8986 dla t9, MterpCheckBefore
8987 move a0, rSELF
8988 daddu a1, rFP, OFF_FP_SHADOWFRAME
8989 daddu ra, ra, (86 * 128) # Addr of primary handler.
8990 jalr zero, t9 # (self, shadow_frame) Note: tail call.
8991
8992/* ------------------------------ */
8993 .balign 128
8994.L_ALT_op_iget_char: /* 0x57 */
8995/* File: mips64/alt_stub.S */
8996/*
8997 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
8998 * any interesting requests and then jump to the real instruction
8999 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9000 */
9001 .extern MterpCheckBefore
9002 EXPORT_PC
9003 REFRESH_IBASE
9004 dla ra, artMterpAsmInstructionStart
9005 dla t9, MterpCheckBefore
9006 move a0, rSELF
9007 daddu a1, rFP, OFF_FP_SHADOWFRAME
9008 daddu ra, ra, (87 * 128) # Addr of primary handler.
9009 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9010
9011/* ------------------------------ */
9012 .balign 128
9013.L_ALT_op_iget_short: /* 0x58 */
9014/* File: mips64/alt_stub.S */
9015/*
9016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9017 * any interesting requests and then jump to the real instruction
9018 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9019 */
9020 .extern MterpCheckBefore
9021 EXPORT_PC
9022 REFRESH_IBASE
9023 dla ra, artMterpAsmInstructionStart
9024 dla t9, MterpCheckBefore
9025 move a0, rSELF
9026 daddu a1, rFP, OFF_FP_SHADOWFRAME
9027 daddu ra, ra, (88 * 128) # Addr of primary handler.
9028 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9029
9030/* ------------------------------ */
9031 .balign 128
9032.L_ALT_op_iput: /* 0x59 */
9033/* File: mips64/alt_stub.S */
9034/*
9035 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9036 * any interesting requests and then jump to the real instruction
9037 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9038 */
9039 .extern MterpCheckBefore
9040 EXPORT_PC
9041 REFRESH_IBASE
9042 dla ra, artMterpAsmInstructionStart
9043 dla t9, MterpCheckBefore
9044 move a0, rSELF
9045 daddu a1, rFP, OFF_FP_SHADOWFRAME
9046 daddu ra, ra, (89 * 128) # Addr of primary handler.
9047 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9048
9049/* ------------------------------ */
9050 .balign 128
9051.L_ALT_op_iput_wide: /* 0x5a */
9052/* File: mips64/alt_stub.S */
9053/*
9054 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9055 * any interesting requests and then jump to the real instruction
9056 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9057 */
9058 .extern MterpCheckBefore
9059 EXPORT_PC
9060 REFRESH_IBASE
9061 dla ra, artMterpAsmInstructionStart
9062 dla t9, MterpCheckBefore
9063 move a0, rSELF
9064 daddu a1, rFP, OFF_FP_SHADOWFRAME
9065 daddu ra, ra, (90 * 128) # Addr of primary handler.
9066 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9067
9068/* ------------------------------ */
9069 .balign 128
9070.L_ALT_op_iput_object: /* 0x5b */
9071/* File: mips64/alt_stub.S */
9072/*
9073 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9074 * any interesting requests and then jump to the real instruction
9075 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9076 */
9077 .extern MterpCheckBefore
9078 EXPORT_PC
9079 REFRESH_IBASE
9080 dla ra, artMterpAsmInstructionStart
9081 dla t9, MterpCheckBefore
9082 move a0, rSELF
9083 daddu a1, rFP, OFF_FP_SHADOWFRAME
9084 daddu ra, ra, (91 * 128) # Addr of primary handler.
9085 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9086
9087/* ------------------------------ */
9088 .balign 128
9089.L_ALT_op_iput_boolean: /* 0x5c */
9090/* File: mips64/alt_stub.S */
9091/*
9092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9093 * any interesting requests and then jump to the real instruction
9094 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9095 */
9096 .extern MterpCheckBefore
9097 EXPORT_PC
9098 REFRESH_IBASE
9099 dla ra, artMterpAsmInstructionStart
9100 dla t9, MterpCheckBefore
9101 move a0, rSELF
9102 daddu a1, rFP, OFF_FP_SHADOWFRAME
9103 daddu ra, ra, (92 * 128) # Addr of primary handler.
9104 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9105
9106/* ------------------------------ */
9107 .balign 128
9108.L_ALT_op_iput_byte: /* 0x5d */
9109/* File: mips64/alt_stub.S */
9110/*
9111 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9112 * any interesting requests and then jump to the real instruction
9113 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9114 */
9115 .extern MterpCheckBefore
9116 EXPORT_PC
9117 REFRESH_IBASE
9118 dla ra, artMterpAsmInstructionStart
9119 dla t9, MterpCheckBefore
9120 move a0, rSELF
9121 daddu a1, rFP, OFF_FP_SHADOWFRAME
9122 daddu ra, ra, (93 * 128) # Addr of primary handler.
9123 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9124
9125/* ------------------------------ */
9126 .balign 128
9127.L_ALT_op_iput_char: /* 0x5e */
9128/* File: mips64/alt_stub.S */
9129/*
9130 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9131 * any interesting requests and then jump to the real instruction
9132 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9133 */
9134 .extern MterpCheckBefore
9135 EXPORT_PC
9136 REFRESH_IBASE
9137 dla ra, artMterpAsmInstructionStart
9138 dla t9, MterpCheckBefore
9139 move a0, rSELF
9140 daddu a1, rFP, OFF_FP_SHADOWFRAME
9141 daddu ra, ra, (94 * 128) # Addr of primary handler.
9142 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9143
9144/* ------------------------------ */
9145 .balign 128
9146.L_ALT_op_iput_short: /* 0x5f */
9147/* File: mips64/alt_stub.S */
9148/*
9149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9150 * any interesting requests and then jump to the real instruction
9151 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9152 */
9153 .extern MterpCheckBefore
9154 EXPORT_PC
9155 REFRESH_IBASE
9156 dla ra, artMterpAsmInstructionStart
9157 dla t9, MterpCheckBefore
9158 move a0, rSELF
9159 daddu a1, rFP, OFF_FP_SHADOWFRAME
9160 daddu ra, ra, (95 * 128) # Addr of primary handler.
9161 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9162
9163/* ------------------------------ */
9164 .balign 128
9165.L_ALT_op_sget: /* 0x60 */
9166/* File: mips64/alt_stub.S */
9167/*
9168 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9169 * any interesting requests and then jump to the real instruction
9170 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9171 */
9172 .extern MterpCheckBefore
9173 EXPORT_PC
9174 REFRESH_IBASE
9175 dla ra, artMterpAsmInstructionStart
9176 dla t9, MterpCheckBefore
9177 move a0, rSELF
9178 daddu a1, rFP, OFF_FP_SHADOWFRAME
9179 daddu ra, ra, (96 * 128) # Addr of primary handler.
9180 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9181
9182/* ------------------------------ */
9183 .balign 128
9184.L_ALT_op_sget_wide: /* 0x61 */
9185/* File: mips64/alt_stub.S */
9186/*
9187 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9188 * any interesting requests and then jump to the real instruction
9189 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9190 */
9191 .extern MterpCheckBefore
9192 EXPORT_PC
9193 REFRESH_IBASE
9194 dla ra, artMterpAsmInstructionStart
9195 dla t9, MterpCheckBefore
9196 move a0, rSELF
9197 daddu a1, rFP, OFF_FP_SHADOWFRAME
9198 daddu ra, ra, (97 * 128) # Addr of primary handler.
9199 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9200
9201/* ------------------------------ */
9202 .balign 128
9203.L_ALT_op_sget_object: /* 0x62 */
9204/* File: mips64/alt_stub.S */
9205/*
9206 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9207 * any interesting requests and then jump to the real instruction
9208 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9209 */
9210 .extern MterpCheckBefore
9211 EXPORT_PC
9212 REFRESH_IBASE
9213 dla ra, artMterpAsmInstructionStart
9214 dla t9, MterpCheckBefore
9215 move a0, rSELF
9216 daddu a1, rFP, OFF_FP_SHADOWFRAME
9217 daddu ra, ra, (98 * 128) # Addr of primary handler.
9218 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9219
9220/* ------------------------------ */
9221 .balign 128
9222.L_ALT_op_sget_boolean: /* 0x63 */
9223/* File: mips64/alt_stub.S */
9224/*
9225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9226 * any interesting requests and then jump to the real instruction
9227 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9228 */
9229 .extern MterpCheckBefore
9230 EXPORT_PC
9231 REFRESH_IBASE
9232 dla ra, artMterpAsmInstructionStart
9233 dla t9, MterpCheckBefore
9234 move a0, rSELF
9235 daddu a1, rFP, OFF_FP_SHADOWFRAME
9236 daddu ra, ra, (99 * 128) # Addr of primary handler.
9237 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9238
9239/* ------------------------------ */
9240 .balign 128
9241.L_ALT_op_sget_byte: /* 0x64 */
9242/* File: mips64/alt_stub.S */
9243/*
9244 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9245 * any interesting requests and then jump to the real instruction
9246 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9247 */
9248 .extern MterpCheckBefore
9249 EXPORT_PC
9250 REFRESH_IBASE
9251 dla ra, artMterpAsmInstructionStart
9252 dla t9, MterpCheckBefore
9253 move a0, rSELF
9254 daddu a1, rFP, OFF_FP_SHADOWFRAME
9255 daddu ra, ra, (100 * 128) # Addr of primary handler.
9256 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9257
9258/* ------------------------------ */
9259 .balign 128
9260.L_ALT_op_sget_char: /* 0x65 */
9261/* File: mips64/alt_stub.S */
9262/*
9263 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9264 * any interesting requests and then jump to the real instruction
9265 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9266 */
9267 .extern MterpCheckBefore
9268 EXPORT_PC
9269 REFRESH_IBASE
9270 dla ra, artMterpAsmInstructionStart
9271 dla t9, MterpCheckBefore
9272 move a0, rSELF
9273 daddu a1, rFP, OFF_FP_SHADOWFRAME
9274 daddu ra, ra, (101 * 128) # Addr of primary handler.
9275 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9276
9277/* ------------------------------ */
9278 .balign 128
9279.L_ALT_op_sget_short: /* 0x66 */
9280/* File: mips64/alt_stub.S */
9281/*
9282 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9283 * any interesting requests and then jump to the real instruction
9284 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9285 */
9286 .extern MterpCheckBefore
9287 EXPORT_PC
9288 REFRESH_IBASE
9289 dla ra, artMterpAsmInstructionStart
9290 dla t9, MterpCheckBefore
9291 move a0, rSELF
9292 daddu a1, rFP, OFF_FP_SHADOWFRAME
9293 daddu ra, ra, (102 * 128) # Addr of primary handler.
9294 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9295
9296/* ------------------------------ */
9297 .balign 128
9298.L_ALT_op_sput: /* 0x67 */
9299/* File: mips64/alt_stub.S */
9300/*
9301 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9302 * any interesting requests and then jump to the real instruction
9303 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9304 */
9305 .extern MterpCheckBefore
9306 EXPORT_PC
9307 REFRESH_IBASE
9308 dla ra, artMterpAsmInstructionStart
9309 dla t9, MterpCheckBefore
9310 move a0, rSELF
9311 daddu a1, rFP, OFF_FP_SHADOWFRAME
9312 daddu ra, ra, (103 * 128) # Addr of primary handler.
9313 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9314
9315/* ------------------------------ */
9316 .balign 128
9317.L_ALT_op_sput_wide: /* 0x68 */
9318/* File: mips64/alt_stub.S */
9319/*
9320 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9321 * any interesting requests and then jump to the real instruction
9322 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9323 */
9324 .extern MterpCheckBefore
9325 EXPORT_PC
9326 REFRESH_IBASE
9327 dla ra, artMterpAsmInstructionStart
9328 dla t9, MterpCheckBefore
9329 move a0, rSELF
9330 daddu a1, rFP, OFF_FP_SHADOWFRAME
9331 daddu ra, ra, (104 * 128) # Addr of primary handler.
9332 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9333
9334/* ------------------------------ */
9335 .balign 128
9336.L_ALT_op_sput_object: /* 0x69 */
9337/* File: mips64/alt_stub.S */
9338/*
9339 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9340 * any interesting requests and then jump to the real instruction
9341 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9342 */
9343 .extern MterpCheckBefore
9344 EXPORT_PC
9345 REFRESH_IBASE
9346 dla ra, artMterpAsmInstructionStart
9347 dla t9, MterpCheckBefore
9348 move a0, rSELF
9349 daddu a1, rFP, OFF_FP_SHADOWFRAME
9350 daddu ra, ra, (105 * 128) # Addr of primary handler.
9351 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9352
9353/* ------------------------------ */
9354 .balign 128
9355.L_ALT_op_sput_boolean: /* 0x6a */
9356/* File: mips64/alt_stub.S */
9357/*
9358 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9359 * any interesting requests and then jump to the real instruction
9360 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9361 */
9362 .extern MterpCheckBefore
9363 EXPORT_PC
9364 REFRESH_IBASE
9365 dla ra, artMterpAsmInstructionStart
9366 dla t9, MterpCheckBefore
9367 move a0, rSELF
9368 daddu a1, rFP, OFF_FP_SHADOWFRAME
9369 daddu ra, ra, (106 * 128) # Addr of primary handler.
9370 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9371
9372/* ------------------------------ */
9373 .balign 128
9374.L_ALT_op_sput_byte: /* 0x6b */
9375/* File: mips64/alt_stub.S */
9376/*
9377 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9378 * any interesting requests and then jump to the real instruction
9379 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9380 */
9381 .extern MterpCheckBefore
9382 EXPORT_PC
9383 REFRESH_IBASE
9384 dla ra, artMterpAsmInstructionStart
9385 dla t9, MterpCheckBefore
9386 move a0, rSELF
9387 daddu a1, rFP, OFF_FP_SHADOWFRAME
9388 daddu ra, ra, (107 * 128) # Addr of primary handler.
9389 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9390
9391/* ------------------------------ */
9392 .balign 128
9393.L_ALT_op_sput_char: /* 0x6c */
9394/* File: mips64/alt_stub.S */
9395/*
9396 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9397 * any interesting requests and then jump to the real instruction
9398 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9399 */
9400 .extern MterpCheckBefore
9401 EXPORT_PC
9402 REFRESH_IBASE
9403 dla ra, artMterpAsmInstructionStart
9404 dla t9, MterpCheckBefore
9405 move a0, rSELF
9406 daddu a1, rFP, OFF_FP_SHADOWFRAME
9407 daddu ra, ra, (108 * 128) # Addr of primary handler.
9408 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9409
9410/* ------------------------------ */
9411 .balign 128
9412.L_ALT_op_sput_short: /* 0x6d */
9413/* File: mips64/alt_stub.S */
9414/*
9415 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9416 * any interesting requests and then jump to the real instruction
9417 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9418 */
9419 .extern MterpCheckBefore
9420 EXPORT_PC
9421 REFRESH_IBASE
9422 dla ra, artMterpAsmInstructionStart
9423 dla t9, MterpCheckBefore
9424 move a0, rSELF
9425 daddu a1, rFP, OFF_FP_SHADOWFRAME
9426 daddu ra, ra, (109 * 128) # Addr of primary handler.
9427 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9428
9429/* ------------------------------ */
9430 .balign 128
9431.L_ALT_op_invoke_virtual: /* 0x6e */
9432/* File: mips64/alt_stub.S */
9433/*
9434 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9435 * any interesting requests and then jump to the real instruction
9436 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9437 */
9438 .extern MterpCheckBefore
9439 EXPORT_PC
9440 REFRESH_IBASE
9441 dla ra, artMterpAsmInstructionStart
9442 dla t9, MterpCheckBefore
9443 move a0, rSELF
9444 daddu a1, rFP, OFF_FP_SHADOWFRAME
9445 daddu ra, ra, (110 * 128) # Addr of primary handler.
9446 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9447
9448/* ------------------------------ */
9449 .balign 128
9450.L_ALT_op_invoke_super: /* 0x6f */
9451/* File: mips64/alt_stub.S */
9452/*
9453 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9454 * any interesting requests and then jump to the real instruction
9455 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9456 */
9457 .extern MterpCheckBefore
9458 EXPORT_PC
9459 REFRESH_IBASE
9460 dla ra, artMterpAsmInstructionStart
9461 dla t9, MterpCheckBefore
9462 move a0, rSELF
9463 daddu a1, rFP, OFF_FP_SHADOWFRAME
9464 daddu ra, ra, (111 * 128) # Addr of primary handler.
9465 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9466
9467/* ------------------------------ */
9468 .balign 128
9469.L_ALT_op_invoke_direct: /* 0x70 */
9470/* File: mips64/alt_stub.S */
9471/*
9472 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9473 * any interesting requests and then jump to the real instruction
9474 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9475 */
9476 .extern MterpCheckBefore
9477 EXPORT_PC
9478 REFRESH_IBASE
9479 dla ra, artMterpAsmInstructionStart
9480 dla t9, MterpCheckBefore
9481 move a0, rSELF
9482 daddu a1, rFP, OFF_FP_SHADOWFRAME
9483 daddu ra, ra, (112 * 128) # Addr of primary handler.
9484 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9485
9486/* ------------------------------ */
9487 .balign 128
9488.L_ALT_op_invoke_static: /* 0x71 */
9489/* File: mips64/alt_stub.S */
9490/*
9491 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9492 * any interesting requests and then jump to the real instruction
9493 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9494 */
9495 .extern MterpCheckBefore
9496 EXPORT_PC
9497 REFRESH_IBASE
9498 dla ra, artMterpAsmInstructionStart
9499 dla t9, MterpCheckBefore
9500 move a0, rSELF
9501 daddu a1, rFP, OFF_FP_SHADOWFRAME
9502 daddu ra, ra, (113 * 128) # Addr of primary handler.
9503 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9504
9505/* ------------------------------ */
9506 .balign 128
9507.L_ALT_op_invoke_interface: /* 0x72 */
9508/* File: mips64/alt_stub.S */
9509/*
9510 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9511 * any interesting requests and then jump to the real instruction
9512 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9513 */
9514 .extern MterpCheckBefore
9515 EXPORT_PC
9516 REFRESH_IBASE
9517 dla ra, artMterpAsmInstructionStart
9518 dla t9, MterpCheckBefore
9519 move a0, rSELF
9520 daddu a1, rFP, OFF_FP_SHADOWFRAME
9521 daddu ra, ra, (114 * 128) # Addr of primary handler.
9522 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9523
9524/* ------------------------------ */
9525 .balign 128
9526.L_ALT_op_return_void_no_barrier: /* 0x73 */
9527/* File: mips64/alt_stub.S */
9528/*
9529 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9530 * any interesting requests and then jump to the real instruction
9531 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9532 */
9533 .extern MterpCheckBefore
9534 EXPORT_PC
9535 REFRESH_IBASE
9536 dla ra, artMterpAsmInstructionStart
9537 dla t9, MterpCheckBefore
9538 move a0, rSELF
9539 daddu a1, rFP, OFF_FP_SHADOWFRAME
9540 daddu ra, ra, (115 * 128) # Addr of primary handler.
9541 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9542
9543/* ------------------------------ */
9544 .balign 128
9545.L_ALT_op_invoke_virtual_range: /* 0x74 */
9546/* File: mips64/alt_stub.S */
9547/*
9548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9549 * any interesting requests and then jump to the real instruction
9550 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9551 */
9552 .extern MterpCheckBefore
9553 EXPORT_PC
9554 REFRESH_IBASE
9555 dla ra, artMterpAsmInstructionStart
9556 dla t9, MterpCheckBefore
9557 move a0, rSELF
9558 daddu a1, rFP, OFF_FP_SHADOWFRAME
9559 daddu ra, ra, (116 * 128) # Addr of primary handler.
9560 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9561
9562/* ------------------------------ */
9563 .balign 128
9564.L_ALT_op_invoke_super_range: /* 0x75 */
9565/* File: mips64/alt_stub.S */
9566/*
9567 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9568 * any interesting requests and then jump to the real instruction
9569 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9570 */
9571 .extern MterpCheckBefore
9572 EXPORT_PC
9573 REFRESH_IBASE
9574 dla ra, artMterpAsmInstructionStart
9575 dla t9, MterpCheckBefore
9576 move a0, rSELF
9577 daddu a1, rFP, OFF_FP_SHADOWFRAME
9578 daddu ra, ra, (117 * 128) # Addr of primary handler.
9579 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9580
9581/* ------------------------------ */
9582 .balign 128
9583.L_ALT_op_invoke_direct_range: /* 0x76 */
9584/* File: mips64/alt_stub.S */
9585/*
9586 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9587 * any interesting requests and then jump to the real instruction
9588 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9589 */
9590 .extern MterpCheckBefore
9591 EXPORT_PC
9592 REFRESH_IBASE
9593 dla ra, artMterpAsmInstructionStart
9594 dla t9, MterpCheckBefore
9595 move a0, rSELF
9596 daddu a1, rFP, OFF_FP_SHADOWFRAME
9597 daddu ra, ra, (118 * 128) # Addr of primary handler.
9598 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9599
9600/* ------------------------------ */
9601 .balign 128
9602.L_ALT_op_invoke_static_range: /* 0x77 */
9603/* File: mips64/alt_stub.S */
9604/*
9605 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9606 * any interesting requests and then jump to the real instruction
9607 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9608 */
9609 .extern MterpCheckBefore
9610 EXPORT_PC
9611 REFRESH_IBASE
9612 dla ra, artMterpAsmInstructionStart
9613 dla t9, MterpCheckBefore
9614 move a0, rSELF
9615 daddu a1, rFP, OFF_FP_SHADOWFRAME
9616 daddu ra, ra, (119 * 128) # Addr of primary handler.
9617 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9618
9619/* ------------------------------ */
9620 .balign 128
9621.L_ALT_op_invoke_interface_range: /* 0x78 */
9622/* File: mips64/alt_stub.S */
9623/*
9624 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9625 * any interesting requests and then jump to the real instruction
9626 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9627 */
9628 .extern MterpCheckBefore
9629 EXPORT_PC
9630 REFRESH_IBASE
9631 dla ra, artMterpAsmInstructionStart
9632 dla t9, MterpCheckBefore
9633 move a0, rSELF
9634 daddu a1, rFP, OFF_FP_SHADOWFRAME
9635 daddu ra, ra, (120 * 128) # Addr of primary handler.
9636 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9637
9638/* ------------------------------ */
9639 .balign 128
9640.L_ALT_op_unused_79: /* 0x79 */
9641/* File: mips64/alt_stub.S */
9642/*
9643 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9644 * any interesting requests and then jump to the real instruction
9645 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9646 */
9647 .extern MterpCheckBefore
9648 EXPORT_PC
9649 REFRESH_IBASE
9650 dla ra, artMterpAsmInstructionStart
9651 dla t9, MterpCheckBefore
9652 move a0, rSELF
9653 daddu a1, rFP, OFF_FP_SHADOWFRAME
9654 daddu ra, ra, (121 * 128) # Addr of primary handler.
9655 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9656
9657/* ------------------------------ */
9658 .balign 128
9659.L_ALT_op_unused_7a: /* 0x7a */
9660/* File: mips64/alt_stub.S */
9661/*
9662 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9663 * any interesting requests and then jump to the real instruction
9664 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9665 */
9666 .extern MterpCheckBefore
9667 EXPORT_PC
9668 REFRESH_IBASE
9669 dla ra, artMterpAsmInstructionStart
9670 dla t9, MterpCheckBefore
9671 move a0, rSELF
9672 daddu a1, rFP, OFF_FP_SHADOWFRAME
9673 daddu ra, ra, (122 * 128) # Addr of primary handler.
9674 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9675
9676/* ------------------------------ */
9677 .balign 128
9678.L_ALT_op_neg_int: /* 0x7b */
9679/* File: mips64/alt_stub.S */
9680/*
9681 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9682 * any interesting requests and then jump to the real instruction
9683 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9684 */
9685 .extern MterpCheckBefore
9686 EXPORT_PC
9687 REFRESH_IBASE
9688 dla ra, artMterpAsmInstructionStart
9689 dla t9, MterpCheckBefore
9690 move a0, rSELF
9691 daddu a1, rFP, OFF_FP_SHADOWFRAME
9692 daddu ra, ra, (123 * 128) # Addr of primary handler.
9693 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9694
9695/* ------------------------------ */
9696 .balign 128
9697.L_ALT_op_not_int: /* 0x7c */
9698/* File: mips64/alt_stub.S */
9699/*
9700 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9701 * any interesting requests and then jump to the real instruction
9702 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9703 */
9704 .extern MterpCheckBefore
9705 EXPORT_PC
9706 REFRESH_IBASE
9707 dla ra, artMterpAsmInstructionStart
9708 dla t9, MterpCheckBefore
9709 move a0, rSELF
9710 daddu a1, rFP, OFF_FP_SHADOWFRAME
9711 daddu ra, ra, (124 * 128) # Addr of primary handler.
9712 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9713
9714/* ------------------------------ */
9715 .balign 128
9716.L_ALT_op_neg_long: /* 0x7d */
9717/* File: mips64/alt_stub.S */
9718/*
9719 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9720 * any interesting requests and then jump to the real instruction
9721 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9722 */
9723 .extern MterpCheckBefore
9724 EXPORT_PC
9725 REFRESH_IBASE
9726 dla ra, artMterpAsmInstructionStart
9727 dla t9, MterpCheckBefore
9728 move a0, rSELF
9729 daddu a1, rFP, OFF_FP_SHADOWFRAME
9730 daddu ra, ra, (125 * 128) # Addr of primary handler.
9731 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9732
9733/* ------------------------------ */
9734 .balign 128
9735.L_ALT_op_not_long: /* 0x7e */
9736/* File: mips64/alt_stub.S */
9737/*
9738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9739 * any interesting requests and then jump to the real instruction
9740 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9741 */
9742 .extern MterpCheckBefore
9743 EXPORT_PC
9744 REFRESH_IBASE
9745 dla ra, artMterpAsmInstructionStart
9746 dla t9, MterpCheckBefore
9747 move a0, rSELF
9748 daddu a1, rFP, OFF_FP_SHADOWFRAME
9749 daddu ra, ra, (126 * 128) # Addr of primary handler.
9750 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9751
9752/* ------------------------------ */
9753 .balign 128
9754.L_ALT_op_neg_float: /* 0x7f */
9755/* File: mips64/alt_stub.S */
9756/*
9757 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9758 * any interesting requests and then jump to the real instruction
9759 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9760 */
9761 .extern MterpCheckBefore
9762 EXPORT_PC
9763 REFRESH_IBASE
9764 dla ra, artMterpAsmInstructionStart
9765 dla t9, MterpCheckBefore
9766 move a0, rSELF
9767 daddu a1, rFP, OFF_FP_SHADOWFRAME
9768 daddu ra, ra, (127 * 128) # Addr of primary handler.
9769 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9770
9771/* ------------------------------ */
9772 .balign 128
9773.L_ALT_op_neg_double: /* 0x80 */
9774/* File: mips64/alt_stub.S */
9775/*
9776 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9777 * any interesting requests and then jump to the real instruction
9778 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9779 */
9780 .extern MterpCheckBefore
9781 EXPORT_PC
9782 REFRESH_IBASE
9783 dla ra, artMterpAsmInstructionStart
9784 dla t9, MterpCheckBefore
9785 move a0, rSELF
9786 daddu a1, rFP, OFF_FP_SHADOWFRAME
9787 daddu ra, ra, (128 * 128) # Addr of primary handler.
9788 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9789
9790/* ------------------------------ */
9791 .balign 128
9792.L_ALT_op_int_to_long: /* 0x81 */
9793/* File: mips64/alt_stub.S */
9794/*
9795 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9796 * any interesting requests and then jump to the real instruction
9797 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9798 */
9799 .extern MterpCheckBefore
9800 EXPORT_PC
9801 REFRESH_IBASE
9802 dla ra, artMterpAsmInstructionStart
9803 dla t9, MterpCheckBefore
9804 move a0, rSELF
9805 daddu a1, rFP, OFF_FP_SHADOWFRAME
9806 daddu ra, ra, (129 * 128) # Addr of primary handler.
9807 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9808
9809/* ------------------------------ */
9810 .balign 128
9811.L_ALT_op_int_to_float: /* 0x82 */
9812/* File: mips64/alt_stub.S */
9813/*
9814 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9815 * any interesting requests and then jump to the real instruction
9816 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9817 */
9818 .extern MterpCheckBefore
9819 EXPORT_PC
9820 REFRESH_IBASE
9821 dla ra, artMterpAsmInstructionStart
9822 dla t9, MterpCheckBefore
9823 move a0, rSELF
9824 daddu a1, rFP, OFF_FP_SHADOWFRAME
9825 daddu ra, ra, (130 * 128) # Addr of primary handler.
9826 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9827
9828/* ------------------------------ */
9829 .balign 128
9830.L_ALT_op_int_to_double: /* 0x83 */
9831/* File: mips64/alt_stub.S */
9832/*
9833 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9834 * any interesting requests and then jump to the real instruction
9835 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9836 */
9837 .extern MterpCheckBefore
9838 EXPORT_PC
9839 REFRESH_IBASE
9840 dla ra, artMterpAsmInstructionStart
9841 dla t9, MterpCheckBefore
9842 move a0, rSELF
9843 daddu a1, rFP, OFF_FP_SHADOWFRAME
9844 daddu ra, ra, (131 * 128) # Addr of primary handler.
9845 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9846
9847/* ------------------------------ */
9848 .balign 128
9849.L_ALT_op_long_to_int: /* 0x84 */
9850/* File: mips64/alt_stub.S */
9851/*
9852 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9853 * any interesting requests and then jump to the real instruction
9854 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9855 */
9856 .extern MterpCheckBefore
9857 EXPORT_PC
9858 REFRESH_IBASE
9859 dla ra, artMterpAsmInstructionStart
9860 dla t9, MterpCheckBefore
9861 move a0, rSELF
9862 daddu a1, rFP, OFF_FP_SHADOWFRAME
9863 daddu ra, ra, (132 * 128) # Addr of primary handler.
9864 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9865
9866/* ------------------------------ */
9867 .balign 128
9868.L_ALT_op_long_to_float: /* 0x85 */
9869/* File: mips64/alt_stub.S */
9870/*
9871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9872 * any interesting requests and then jump to the real instruction
9873 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9874 */
9875 .extern MterpCheckBefore
9876 EXPORT_PC
9877 REFRESH_IBASE
9878 dla ra, artMterpAsmInstructionStart
9879 dla t9, MterpCheckBefore
9880 move a0, rSELF
9881 daddu a1, rFP, OFF_FP_SHADOWFRAME
9882 daddu ra, ra, (133 * 128) # Addr of primary handler.
9883 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9884
9885/* ------------------------------ */
9886 .balign 128
9887.L_ALT_op_long_to_double: /* 0x86 */
9888/* File: mips64/alt_stub.S */
9889/*
9890 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9891 * any interesting requests and then jump to the real instruction
9892 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9893 */
9894 .extern MterpCheckBefore
9895 EXPORT_PC
9896 REFRESH_IBASE
9897 dla ra, artMterpAsmInstructionStart
9898 dla t9, MterpCheckBefore
9899 move a0, rSELF
9900 daddu a1, rFP, OFF_FP_SHADOWFRAME
9901 daddu ra, ra, (134 * 128) # Addr of primary handler.
9902 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9903
9904/* ------------------------------ */
9905 .balign 128
9906.L_ALT_op_float_to_int: /* 0x87 */
9907/* File: mips64/alt_stub.S */
9908/*
9909 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9910 * any interesting requests and then jump to the real instruction
9911 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9912 */
9913 .extern MterpCheckBefore
9914 EXPORT_PC
9915 REFRESH_IBASE
9916 dla ra, artMterpAsmInstructionStart
9917 dla t9, MterpCheckBefore
9918 move a0, rSELF
9919 daddu a1, rFP, OFF_FP_SHADOWFRAME
9920 daddu ra, ra, (135 * 128) # Addr of primary handler.
9921 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9922
9923/* ------------------------------ */
9924 .balign 128
9925.L_ALT_op_float_to_long: /* 0x88 */
9926/* File: mips64/alt_stub.S */
9927/*
9928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9929 * any interesting requests and then jump to the real instruction
9930 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9931 */
9932 .extern MterpCheckBefore
9933 EXPORT_PC
9934 REFRESH_IBASE
9935 dla ra, artMterpAsmInstructionStart
9936 dla t9, MterpCheckBefore
9937 move a0, rSELF
9938 daddu a1, rFP, OFF_FP_SHADOWFRAME
9939 daddu ra, ra, (136 * 128) # Addr of primary handler.
9940 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9941
9942/* ------------------------------ */
9943 .balign 128
9944.L_ALT_op_float_to_double: /* 0x89 */
9945/* File: mips64/alt_stub.S */
9946/*
9947 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9948 * any interesting requests and then jump to the real instruction
9949 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9950 */
9951 .extern MterpCheckBefore
9952 EXPORT_PC
9953 REFRESH_IBASE
9954 dla ra, artMterpAsmInstructionStart
9955 dla t9, MterpCheckBefore
9956 move a0, rSELF
9957 daddu a1, rFP, OFF_FP_SHADOWFRAME
9958 daddu ra, ra, (137 * 128) # Addr of primary handler.
9959 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9960
9961/* ------------------------------ */
9962 .balign 128
9963.L_ALT_op_double_to_int: /* 0x8a */
9964/* File: mips64/alt_stub.S */
9965/*
9966 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9967 * any interesting requests and then jump to the real instruction
9968 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9969 */
9970 .extern MterpCheckBefore
9971 EXPORT_PC
9972 REFRESH_IBASE
9973 dla ra, artMterpAsmInstructionStart
9974 dla t9, MterpCheckBefore
9975 move a0, rSELF
9976 daddu a1, rFP, OFF_FP_SHADOWFRAME
9977 daddu ra, ra, (138 * 128) # Addr of primary handler.
9978 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9979
9980/* ------------------------------ */
9981 .balign 128
9982.L_ALT_op_double_to_long: /* 0x8b */
9983/* File: mips64/alt_stub.S */
9984/*
9985 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
9986 * any interesting requests and then jump to the real instruction
9987 * handler. Note that the call to MterpCheckBefore is done as a tail call.
9988 */
9989 .extern MterpCheckBefore
9990 EXPORT_PC
9991 REFRESH_IBASE
9992 dla ra, artMterpAsmInstructionStart
9993 dla t9, MterpCheckBefore
9994 move a0, rSELF
9995 daddu a1, rFP, OFF_FP_SHADOWFRAME
9996 daddu ra, ra, (139 * 128) # Addr of primary handler.
9997 jalr zero, t9 # (self, shadow_frame) Note: tail call.
9998
9999/* ------------------------------ */
10000 .balign 128
10001.L_ALT_op_double_to_float: /* 0x8c */
10002/* File: mips64/alt_stub.S */
10003/*
10004 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10005 * any interesting requests and then jump to the real instruction
10006 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10007 */
10008 .extern MterpCheckBefore
10009 EXPORT_PC
10010 REFRESH_IBASE
10011 dla ra, artMterpAsmInstructionStart
10012 dla t9, MterpCheckBefore
10013 move a0, rSELF
10014 daddu a1, rFP, OFF_FP_SHADOWFRAME
10015 daddu ra, ra, (140 * 128) # Addr of primary handler.
10016 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10017
10018/* ------------------------------ */
10019 .balign 128
10020.L_ALT_op_int_to_byte: /* 0x8d */
10021/* File: mips64/alt_stub.S */
10022/*
10023 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10024 * any interesting requests and then jump to the real instruction
10025 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10026 */
10027 .extern MterpCheckBefore
10028 EXPORT_PC
10029 REFRESH_IBASE
10030 dla ra, artMterpAsmInstructionStart
10031 dla t9, MterpCheckBefore
10032 move a0, rSELF
10033 daddu a1, rFP, OFF_FP_SHADOWFRAME
10034 daddu ra, ra, (141 * 128) # Addr of primary handler.
10035 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10036
10037/* ------------------------------ */
10038 .balign 128
10039.L_ALT_op_int_to_char: /* 0x8e */
10040/* File: mips64/alt_stub.S */
10041/*
10042 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10043 * any interesting requests and then jump to the real instruction
10044 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10045 */
10046 .extern MterpCheckBefore
10047 EXPORT_PC
10048 REFRESH_IBASE
10049 dla ra, artMterpAsmInstructionStart
10050 dla t9, MterpCheckBefore
10051 move a0, rSELF
10052 daddu a1, rFP, OFF_FP_SHADOWFRAME
10053 daddu ra, ra, (142 * 128) # Addr of primary handler.
10054 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10055
10056/* ------------------------------ */
10057 .balign 128
10058.L_ALT_op_int_to_short: /* 0x8f */
10059/* File: mips64/alt_stub.S */
10060/*
10061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10062 * any interesting requests and then jump to the real instruction
10063 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10064 */
10065 .extern MterpCheckBefore
10066 EXPORT_PC
10067 REFRESH_IBASE
10068 dla ra, artMterpAsmInstructionStart
10069 dla t9, MterpCheckBefore
10070 move a0, rSELF
10071 daddu a1, rFP, OFF_FP_SHADOWFRAME
10072 daddu ra, ra, (143 * 128) # Addr of primary handler.
10073 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10074
10075/* ------------------------------ */
10076 .balign 128
10077.L_ALT_op_add_int: /* 0x90 */
10078/* File: mips64/alt_stub.S */
10079/*
10080 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10081 * any interesting requests and then jump to the real instruction
10082 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10083 */
10084 .extern MterpCheckBefore
10085 EXPORT_PC
10086 REFRESH_IBASE
10087 dla ra, artMterpAsmInstructionStart
10088 dla t9, MterpCheckBefore
10089 move a0, rSELF
10090 daddu a1, rFP, OFF_FP_SHADOWFRAME
10091 daddu ra, ra, (144 * 128) # Addr of primary handler.
10092 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10093
10094/* ------------------------------ */
10095 .balign 128
10096.L_ALT_op_sub_int: /* 0x91 */
10097/* File: mips64/alt_stub.S */
10098/*
10099 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10100 * any interesting requests and then jump to the real instruction
10101 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10102 */
10103 .extern MterpCheckBefore
10104 EXPORT_PC
10105 REFRESH_IBASE
10106 dla ra, artMterpAsmInstructionStart
10107 dla t9, MterpCheckBefore
10108 move a0, rSELF
10109 daddu a1, rFP, OFF_FP_SHADOWFRAME
10110 daddu ra, ra, (145 * 128) # Addr of primary handler.
10111 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10112
10113/* ------------------------------ */
10114 .balign 128
10115.L_ALT_op_mul_int: /* 0x92 */
10116/* File: mips64/alt_stub.S */
10117/*
10118 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10119 * any interesting requests and then jump to the real instruction
10120 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10121 */
10122 .extern MterpCheckBefore
10123 EXPORT_PC
10124 REFRESH_IBASE
10125 dla ra, artMterpAsmInstructionStart
10126 dla t9, MterpCheckBefore
10127 move a0, rSELF
10128 daddu a1, rFP, OFF_FP_SHADOWFRAME
10129 daddu ra, ra, (146 * 128) # Addr of primary handler.
10130 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10131
10132/* ------------------------------ */
10133 .balign 128
10134.L_ALT_op_div_int: /* 0x93 */
10135/* File: mips64/alt_stub.S */
10136/*
10137 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10138 * any interesting requests and then jump to the real instruction
10139 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10140 */
10141 .extern MterpCheckBefore
10142 EXPORT_PC
10143 REFRESH_IBASE
10144 dla ra, artMterpAsmInstructionStart
10145 dla t9, MterpCheckBefore
10146 move a0, rSELF
10147 daddu a1, rFP, OFF_FP_SHADOWFRAME
10148 daddu ra, ra, (147 * 128) # Addr of primary handler.
10149 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10150
10151/* ------------------------------ */
10152 .balign 128
10153.L_ALT_op_rem_int: /* 0x94 */
10154/* File: mips64/alt_stub.S */
10155/*
10156 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10157 * any interesting requests and then jump to the real instruction
10158 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10159 */
10160 .extern MterpCheckBefore
10161 EXPORT_PC
10162 REFRESH_IBASE
10163 dla ra, artMterpAsmInstructionStart
10164 dla t9, MterpCheckBefore
10165 move a0, rSELF
10166 daddu a1, rFP, OFF_FP_SHADOWFRAME
10167 daddu ra, ra, (148 * 128) # Addr of primary handler.
10168 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10169
10170/* ------------------------------ */
10171 .balign 128
10172.L_ALT_op_and_int: /* 0x95 */
10173/* File: mips64/alt_stub.S */
10174/*
10175 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10176 * any interesting requests and then jump to the real instruction
10177 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10178 */
10179 .extern MterpCheckBefore
10180 EXPORT_PC
10181 REFRESH_IBASE
10182 dla ra, artMterpAsmInstructionStart
10183 dla t9, MterpCheckBefore
10184 move a0, rSELF
10185 daddu a1, rFP, OFF_FP_SHADOWFRAME
10186 daddu ra, ra, (149 * 128) # Addr of primary handler.
10187 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10188
10189/* ------------------------------ */
10190 .balign 128
10191.L_ALT_op_or_int: /* 0x96 */
10192/* File: mips64/alt_stub.S */
10193/*
10194 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10195 * any interesting requests and then jump to the real instruction
10196 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10197 */
10198 .extern MterpCheckBefore
10199 EXPORT_PC
10200 REFRESH_IBASE
10201 dla ra, artMterpAsmInstructionStart
10202 dla t9, MterpCheckBefore
10203 move a0, rSELF
10204 daddu a1, rFP, OFF_FP_SHADOWFRAME
10205 daddu ra, ra, (150 * 128) # Addr of primary handler.
10206 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10207
10208/* ------------------------------ */
10209 .balign 128
10210.L_ALT_op_xor_int: /* 0x97 */
10211/* File: mips64/alt_stub.S */
10212/*
10213 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10214 * any interesting requests and then jump to the real instruction
10215 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10216 */
10217 .extern MterpCheckBefore
10218 EXPORT_PC
10219 REFRESH_IBASE
10220 dla ra, artMterpAsmInstructionStart
10221 dla t9, MterpCheckBefore
10222 move a0, rSELF
10223 daddu a1, rFP, OFF_FP_SHADOWFRAME
10224 daddu ra, ra, (151 * 128) # Addr of primary handler.
10225 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10226
10227/* ------------------------------ */
10228 .balign 128
10229.L_ALT_op_shl_int: /* 0x98 */
10230/* File: mips64/alt_stub.S */
10231/*
10232 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10233 * any interesting requests and then jump to the real instruction
10234 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10235 */
10236 .extern MterpCheckBefore
10237 EXPORT_PC
10238 REFRESH_IBASE
10239 dla ra, artMterpAsmInstructionStart
10240 dla t9, MterpCheckBefore
10241 move a0, rSELF
10242 daddu a1, rFP, OFF_FP_SHADOWFRAME
10243 daddu ra, ra, (152 * 128) # Addr of primary handler.
10244 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10245
10246/* ------------------------------ */
10247 .balign 128
10248.L_ALT_op_shr_int: /* 0x99 */
10249/* File: mips64/alt_stub.S */
10250/*
10251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10252 * any interesting requests and then jump to the real instruction
10253 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10254 */
10255 .extern MterpCheckBefore
10256 EXPORT_PC
10257 REFRESH_IBASE
10258 dla ra, artMterpAsmInstructionStart
10259 dla t9, MterpCheckBefore
10260 move a0, rSELF
10261 daddu a1, rFP, OFF_FP_SHADOWFRAME
10262 daddu ra, ra, (153 * 128) # Addr of primary handler.
10263 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10264
10265/* ------------------------------ */
10266 .balign 128
10267.L_ALT_op_ushr_int: /* 0x9a */
10268/* File: mips64/alt_stub.S */
10269/*
10270 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10271 * any interesting requests and then jump to the real instruction
10272 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10273 */
10274 .extern MterpCheckBefore
10275 EXPORT_PC
10276 REFRESH_IBASE
10277 dla ra, artMterpAsmInstructionStart
10278 dla t9, MterpCheckBefore
10279 move a0, rSELF
10280 daddu a1, rFP, OFF_FP_SHADOWFRAME
10281 daddu ra, ra, (154 * 128) # Addr of primary handler.
10282 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10283
10284/* ------------------------------ */
10285 .balign 128
10286.L_ALT_op_add_long: /* 0x9b */
10287/* File: mips64/alt_stub.S */
10288/*
10289 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10290 * any interesting requests and then jump to the real instruction
10291 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10292 */
10293 .extern MterpCheckBefore
10294 EXPORT_PC
10295 REFRESH_IBASE
10296 dla ra, artMterpAsmInstructionStart
10297 dla t9, MterpCheckBefore
10298 move a0, rSELF
10299 daddu a1, rFP, OFF_FP_SHADOWFRAME
10300 daddu ra, ra, (155 * 128) # Addr of primary handler.
10301 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10302
10303/* ------------------------------ */
10304 .balign 128
10305.L_ALT_op_sub_long: /* 0x9c */
10306/* File: mips64/alt_stub.S */
10307/*
10308 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10309 * any interesting requests and then jump to the real instruction
10310 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10311 */
10312 .extern MterpCheckBefore
10313 EXPORT_PC
10314 REFRESH_IBASE
10315 dla ra, artMterpAsmInstructionStart
10316 dla t9, MterpCheckBefore
10317 move a0, rSELF
10318 daddu a1, rFP, OFF_FP_SHADOWFRAME
10319 daddu ra, ra, (156 * 128) # Addr of primary handler.
10320 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10321
10322/* ------------------------------ */
10323 .balign 128
10324.L_ALT_op_mul_long: /* 0x9d */
10325/* File: mips64/alt_stub.S */
10326/*
10327 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10328 * any interesting requests and then jump to the real instruction
10329 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10330 */
10331 .extern MterpCheckBefore
10332 EXPORT_PC
10333 REFRESH_IBASE
10334 dla ra, artMterpAsmInstructionStart
10335 dla t9, MterpCheckBefore
10336 move a0, rSELF
10337 daddu a1, rFP, OFF_FP_SHADOWFRAME
10338 daddu ra, ra, (157 * 128) # Addr of primary handler.
10339 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10340
10341/* ------------------------------ */
10342 .balign 128
10343.L_ALT_op_div_long: /* 0x9e */
10344/* File: mips64/alt_stub.S */
10345/*
10346 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10347 * any interesting requests and then jump to the real instruction
10348 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10349 */
10350 .extern MterpCheckBefore
10351 EXPORT_PC
10352 REFRESH_IBASE
10353 dla ra, artMterpAsmInstructionStart
10354 dla t9, MterpCheckBefore
10355 move a0, rSELF
10356 daddu a1, rFP, OFF_FP_SHADOWFRAME
10357 daddu ra, ra, (158 * 128) # Addr of primary handler.
10358 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10359
10360/* ------------------------------ */
10361 .balign 128
10362.L_ALT_op_rem_long: /* 0x9f */
10363/* File: mips64/alt_stub.S */
10364/*
10365 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10366 * any interesting requests and then jump to the real instruction
10367 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10368 */
10369 .extern MterpCheckBefore
10370 EXPORT_PC
10371 REFRESH_IBASE
10372 dla ra, artMterpAsmInstructionStart
10373 dla t9, MterpCheckBefore
10374 move a0, rSELF
10375 daddu a1, rFP, OFF_FP_SHADOWFRAME
10376 daddu ra, ra, (159 * 128) # Addr of primary handler.
10377 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10378
10379/* ------------------------------ */
10380 .balign 128
10381.L_ALT_op_and_long: /* 0xa0 */
10382/* File: mips64/alt_stub.S */
10383/*
10384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10385 * any interesting requests and then jump to the real instruction
10386 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10387 */
10388 .extern MterpCheckBefore
10389 EXPORT_PC
10390 REFRESH_IBASE
10391 dla ra, artMterpAsmInstructionStart
10392 dla t9, MterpCheckBefore
10393 move a0, rSELF
10394 daddu a1, rFP, OFF_FP_SHADOWFRAME
10395 daddu ra, ra, (160 * 128) # Addr of primary handler.
10396 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10397
10398/* ------------------------------ */
10399 .balign 128
10400.L_ALT_op_or_long: /* 0xa1 */
10401/* File: mips64/alt_stub.S */
10402/*
10403 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10404 * any interesting requests and then jump to the real instruction
10405 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10406 */
10407 .extern MterpCheckBefore
10408 EXPORT_PC
10409 REFRESH_IBASE
10410 dla ra, artMterpAsmInstructionStart
10411 dla t9, MterpCheckBefore
10412 move a0, rSELF
10413 daddu a1, rFP, OFF_FP_SHADOWFRAME
10414 daddu ra, ra, (161 * 128) # Addr of primary handler.
10415 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10416
10417/* ------------------------------ */
10418 .balign 128
10419.L_ALT_op_xor_long: /* 0xa2 */
10420/* File: mips64/alt_stub.S */
10421/*
10422 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10423 * any interesting requests and then jump to the real instruction
10424 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10425 */
10426 .extern MterpCheckBefore
10427 EXPORT_PC
10428 REFRESH_IBASE
10429 dla ra, artMterpAsmInstructionStart
10430 dla t9, MterpCheckBefore
10431 move a0, rSELF
10432 daddu a1, rFP, OFF_FP_SHADOWFRAME
10433 daddu ra, ra, (162 * 128) # Addr of primary handler.
10434 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10435
10436/* ------------------------------ */
10437 .balign 128
10438.L_ALT_op_shl_long: /* 0xa3 */
10439/* File: mips64/alt_stub.S */
10440/*
10441 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10442 * any interesting requests and then jump to the real instruction
10443 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10444 */
10445 .extern MterpCheckBefore
10446 EXPORT_PC
10447 REFRESH_IBASE
10448 dla ra, artMterpAsmInstructionStart
10449 dla t9, MterpCheckBefore
10450 move a0, rSELF
10451 daddu a1, rFP, OFF_FP_SHADOWFRAME
10452 daddu ra, ra, (163 * 128) # Addr of primary handler.
10453 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10454
10455/* ------------------------------ */
10456 .balign 128
10457.L_ALT_op_shr_long: /* 0xa4 */
10458/* File: mips64/alt_stub.S */
10459/*
10460 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10461 * any interesting requests and then jump to the real instruction
10462 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10463 */
10464 .extern MterpCheckBefore
10465 EXPORT_PC
10466 REFRESH_IBASE
10467 dla ra, artMterpAsmInstructionStart
10468 dla t9, MterpCheckBefore
10469 move a0, rSELF
10470 daddu a1, rFP, OFF_FP_SHADOWFRAME
10471 daddu ra, ra, (164 * 128) # Addr of primary handler.
10472 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10473
10474/* ------------------------------ */
10475 .balign 128
10476.L_ALT_op_ushr_long: /* 0xa5 */
10477/* File: mips64/alt_stub.S */
10478/*
10479 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10480 * any interesting requests and then jump to the real instruction
10481 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10482 */
10483 .extern MterpCheckBefore
10484 EXPORT_PC
10485 REFRESH_IBASE
10486 dla ra, artMterpAsmInstructionStart
10487 dla t9, MterpCheckBefore
10488 move a0, rSELF
10489 daddu a1, rFP, OFF_FP_SHADOWFRAME
10490 daddu ra, ra, (165 * 128) # Addr of primary handler.
10491 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10492
10493/* ------------------------------ */
10494 .balign 128
10495.L_ALT_op_add_float: /* 0xa6 */
10496/* File: mips64/alt_stub.S */
10497/*
10498 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10499 * any interesting requests and then jump to the real instruction
10500 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10501 */
10502 .extern MterpCheckBefore
10503 EXPORT_PC
10504 REFRESH_IBASE
10505 dla ra, artMterpAsmInstructionStart
10506 dla t9, MterpCheckBefore
10507 move a0, rSELF
10508 daddu a1, rFP, OFF_FP_SHADOWFRAME
10509 daddu ra, ra, (166 * 128) # Addr of primary handler.
10510 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10511
10512/* ------------------------------ */
10513 .balign 128
10514.L_ALT_op_sub_float: /* 0xa7 */
10515/* File: mips64/alt_stub.S */
10516/*
10517 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10518 * any interesting requests and then jump to the real instruction
10519 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10520 */
10521 .extern MterpCheckBefore
10522 EXPORT_PC
10523 REFRESH_IBASE
10524 dla ra, artMterpAsmInstructionStart
10525 dla t9, MterpCheckBefore
10526 move a0, rSELF
10527 daddu a1, rFP, OFF_FP_SHADOWFRAME
10528 daddu ra, ra, (167 * 128) # Addr of primary handler.
10529 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10530
10531/* ------------------------------ */
10532 .balign 128
10533.L_ALT_op_mul_float: /* 0xa8 */
10534/* File: mips64/alt_stub.S */
10535/*
10536 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10537 * any interesting requests and then jump to the real instruction
10538 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10539 */
10540 .extern MterpCheckBefore
10541 EXPORT_PC
10542 REFRESH_IBASE
10543 dla ra, artMterpAsmInstructionStart
10544 dla t9, MterpCheckBefore
10545 move a0, rSELF
10546 daddu a1, rFP, OFF_FP_SHADOWFRAME
10547 daddu ra, ra, (168 * 128) # Addr of primary handler.
10548 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10549
10550/* ------------------------------ */
10551 .balign 128
10552.L_ALT_op_div_float: /* 0xa9 */
10553/* File: mips64/alt_stub.S */
10554/*
10555 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10556 * any interesting requests and then jump to the real instruction
10557 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10558 */
10559 .extern MterpCheckBefore
10560 EXPORT_PC
10561 REFRESH_IBASE
10562 dla ra, artMterpAsmInstructionStart
10563 dla t9, MterpCheckBefore
10564 move a0, rSELF
10565 daddu a1, rFP, OFF_FP_SHADOWFRAME
10566 daddu ra, ra, (169 * 128) # Addr of primary handler.
10567 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10568
10569/* ------------------------------ */
10570 .balign 128
10571.L_ALT_op_rem_float: /* 0xaa */
10572/* File: mips64/alt_stub.S */
10573/*
10574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10575 * any interesting requests and then jump to the real instruction
10576 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10577 */
10578 .extern MterpCheckBefore
10579 EXPORT_PC
10580 REFRESH_IBASE
10581 dla ra, artMterpAsmInstructionStart
10582 dla t9, MterpCheckBefore
10583 move a0, rSELF
10584 daddu a1, rFP, OFF_FP_SHADOWFRAME
10585 daddu ra, ra, (170 * 128) # Addr of primary handler.
10586 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10587
10588/* ------------------------------ */
10589 .balign 128
10590.L_ALT_op_add_double: /* 0xab */
10591/* File: mips64/alt_stub.S */
10592/*
10593 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10594 * any interesting requests and then jump to the real instruction
10595 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10596 */
10597 .extern MterpCheckBefore
10598 EXPORT_PC
10599 REFRESH_IBASE
10600 dla ra, artMterpAsmInstructionStart
10601 dla t9, MterpCheckBefore
10602 move a0, rSELF
10603 daddu a1, rFP, OFF_FP_SHADOWFRAME
10604 daddu ra, ra, (171 * 128) # Addr of primary handler.
10605 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10606
10607/* ------------------------------ */
10608 .balign 128
10609.L_ALT_op_sub_double: /* 0xac */
10610/* File: mips64/alt_stub.S */
10611/*
10612 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10613 * any interesting requests and then jump to the real instruction
10614 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10615 */
10616 .extern MterpCheckBefore
10617 EXPORT_PC
10618 REFRESH_IBASE
10619 dla ra, artMterpAsmInstructionStart
10620 dla t9, MterpCheckBefore
10621 move a0, rSELF
10622 daddu a1, rFP, OFF_FP_SHADOWFRAME
10623 daddu ra, ra, (172 * 128) # Addr of primary handler.
10624 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10625
10626/* ------------------------------ */
10627 .balign 128
10628.L_ALT_op_mul_double: /* 0xad */
10629/* File: mips64/alt_stub.S */
10630/*
10631 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10632 * any interesting requests and then jump to the real instruction
10633 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10634 */
10635 .extern MterpCheckBefore
10636 EXPORT_PC
10637 REFRESH_IBASE
10638 dla ra, artMterpAsmInstructionStart
10639 dla t9, MterpCheckBefore
10640 move a0, rSELF
10641 daddu a1, rFP, OFF_FP_SHADOWFRAME
10642 daddu ra, ra, (173 * 128) # Addr of primary handler.
10643 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10644
10645/* ------------------------------ */
10646 .balign 128
10647.L_ALT_op_div_double: /* 0xae */
10648/* File: mips64/alt_stub.S */
10649/*
10650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10651 * any interesting requests and then jump to the real instruction
10652 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10653 */
10654 .extern MterpCheckBefore
10655 EXPORT_PC
10656 REFRESH_IBASE
10657 dla ra, artMterpAsmInstructionStart
10658 dla t9, MterpCheckBefore
10659 move a0, rSELF
10660 daddu a1, rFP, OFF_FP_SHADOWFRAME
10661 daddu ra, ra, (174 * 128) # Addr of primary handler.
10662 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10663
10664/* ------------------------------ */
10665 .balign 128
10666.L_ALT_op_rem_double: /* 0xaf */
10667/* File: mips64/alt_stub.S */
10668/*
10669 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10670 * any interesting requests and then jump to the real instruction
10671 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10672 */
10673 .extern MterpCheckBefore
10674 EXPORT_PC
10675 REFRESH_IBASE
10676 dla ra, artMterpAsmInstructionStart
10677 dla t9, MterpCheckBefore
10678 move a0, rSELF
10679 daddu a1, rFP, OFF_FP_SHADOWFRAME
10680 daddu ra, ra, (175 * 128) # Addr of primary handler.
10681 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10682
10683/* ------------------------------ */
10684 .balign 128
10685.L_ALT_op_add_int_2addr: /* 0xb0 */
10686/* File: mips64/alt_stub.S */
10687/*
10688 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10689 * any interesting requests and then jump to the real instruction
10690 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10691 */
10692 .extern MterpCheckBefore
10693 EXPORT_PC
10694 REFRESH_IBASE
10695 dla ra, artMterpAsmInstructionStart
10696 dla t9, MterpCheckBefore
10697 move a0, rSELF
10698 daddu a1, rFP, OFF_FP_SHADOWFRAME
10699 daddu ra, ra, (176 * 128) # Addr of primary handler.
10700 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10701
10702/* ------------------------------ */
10703 .balign 128
10704.L_ALT_op_sub_int_2addr: /* 0xb1 */
10705/* File: mips64/alt_stub.S */
10706/*
10707 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10708 * any interesting requests and then jump to the real instruction
10709 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10710 */
10711 .extern MterpCheckBefore
10712 EXPORT_PC
10713 REFRESH_IBASE
10714 dla ra, artMterpAsmInstructionStart
10715 dla t9, MterpCheckBefore
10716 move a0, rSELF
10717 daddu a1, rFP, OFF_FP_SHADOWFRAME
10718 daddu ra, ra, (177 * 128) # Addr of primary handler.
10719 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10720
10721/* ------------------------------ */
10722 .balign 128
10723.L_ALT_op_mul_int_2addr: /* 0xb2 */
10724/* File: mips64/alt_stub.S */
10725/*
10726 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10727 * any interesting requests and then jump to the real instruction
10728 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10729 */
10730 .extern MterpCheckBefore
10731 EXPORT_PC
10732 REFRESH_IBASE
10733 dla ra, artMterpAsmInstructionStart
10734 dla t9, MterpCheckBefore
10735 move a0, rSELF
10736 daddu a1, rFP, OFF_FP_SHADOWFRAME
10737 daddu ra, ra, (178 * 128) # Addr of primary handler.
10738 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10739
10740/* ------------------------------ */
10741 .balign 128
10742.L_ALT_op_div_int_2addr: /* 0xb3 */
10743/* File: mips64/alt_stub.S */
10744/*
10745 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10746 * any interesting requests and then jump to the real instruction
10747 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10748 */
10749 .extern MterpCheckBefore
10750 EXPORT_PC
10751 REFRESH_IBASE
10752 dla ra, artMterpAsmInstructionStart
10753 dla t9, MterpCheckBefore
10754 move a0, rSELF
10755 daddu a1, rFP, OFF_FP_SHADOWFRAME
10756 daddu ra, ra, (179 * 128) # Addr of primary handler.
10757 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10758
10759/* ------------------------------ */
10760 .balign 128
10761.L_ALT_op_rem_int_2addr: /* 0xb4 */
10762/* File: mips64/alt_stub.S */
10763/*
10764 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10765 * any interesting requests and then jump to the real instruction
10766 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10767 */
10768 .extern MterpCheckBefore
10769 EXPORT_PC
10770 REFRESH_IBASE
10771 dla ra, artMterpAsmInstructionStart
10772 dla t9, MterpCheckBefore
10773 move a0, rSELF
10774 daddu a1, rFP, OFF_FP_SHADOWFRAME
10775 daddu ra, ra, (180 * 128) # Addr of primary handler.
10776 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10777
10778/* ------------------------------ */
10779 .balign 128
10780.L_ALT_op_and_int_2addr: /* 0xb5 */
10781/* File: mips64/alt_stub.S */
10782/*
10783 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10784 * any interesting requests and then jump to the real instruction
10785 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10786 */
10787 .extern MterpCheckBefore
10788 EXPORT_PC
10789 REFRESH_IBASE
10790 dla ra, artMterpAsmInstructionStart
10791 dla t9, MterpCheckBefore
10792 move a0, rSELF
10793 daddu a1, rFP, OFF_FP_SHADOWFRAME
10794 daddu ra, ra, (181 * 128) # Addr of primary handler.
10795 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10796
10797/* ------------------------------ */
10798 .balign 128
10799.L_ALT_op_or_int_2addr: /* 0xb6 */
10800/* File: mips64/alt_stub.S */
10801/*
10802 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10803 * any interesting requests and then jump to the real instruction
10804 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10805 */
10806 .extern MterpCheckBefore
10807 EXPORT_PC
10808 REFRESH_IBASE
10809 dla ra, artMterpAsmInstructionStart
10810 dla t9, MterpCheckBefore
10811 move a0, rSELF
10812 daddu a1, rFP, OFF_FP_SHADOWFRAME
10813 daddu ra, ra, (182 * 128) # Addr of primary handler.
10814 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10815
10816/* ------------------------------ */
10817 .balign 128
10818.L_ALT_op_xor_int_2addr: /* 0xb7 */
10819/* File: mips64/alt_stub.S */
10820/*
10821 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10822 * any interesting requests and then jump to the real instruction
10823 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10824 */
10825 .extern MterpCheckBefore
10826 EXPORT_PC
10827 REFRESH_IBASE
10828 dla ra, artMterpAsmInstructionStart
10829 dla t9, MterpCheckBefore
10830 move a0, rSELF
10831 daddu a1, rFP, OFF_FP_SHADOWFRAME
10832 daddu ra, ra, (183 * 128) # Addr of primary handler.
10833 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10834
10835/* ------------------------------ */
10836 .balign 128
10837.L_ALT_op_shl_int_2addr: /* 0xb8 */
10838/* File: mips64/alt_stub.S */
10839/*
10840 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10841 * any interesting requests and then jump to the real instruction
10842 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10843 */
10844 .extern MterpCheckBefore
10845 EXPORT_PC
10846 REFRESH_IBASE
10847 dla ra, artMterpAsmInstructionStart
10848 dla t9, MterpCheckBefore
10849 move a0, rSELF
10850 daddu a1, rFP, OFF_FP_SHADOWFRAME
10851 daddu ra, ra, (184 * 128) # Addr of primary handler.
10852 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10853
10854/* ------------------------------ */
10855 .balign 128
10856.L_ALT_op_shr_int_2addr: /* 0xb9 */
10857/* File: mips64/alt_stub.S */
10858/*
10859 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10860 * any interesting requests and then jump to the real instruction
10861 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10862 */
10863 .extern MterpCheckBefore
10864 EXPORT_PC
10865 REFRESH_IBASE
10866 dla ra, artMterpAsmInstructionStart
10867 dla t9, MterpCheckBefore
10868 move a0, rSELF
10869 daddu a1, rFP, OFF_FP_SHADOWFRAME
10870 daddu ra, ra, (185 * 128) # Addr of primary handler.
10871 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10872
10873/* ------------------------------ */
10874 .balign 128
10875.L_ALT_op_ushr_int_2addr: /* 0xba */
10876/* File: mips64/alt_stub.S */
10877/*
10878 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10879 * any interesting requests and then jump to the real instruction
10880 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10881 */
10882 .extern MterpCheckBefore
10883 EXPORT_PC
10884 REFRESH_IBASE
10885 dla ra, artMterpAsmInstructionStart
10886 dla t9, MterpCheckBefore
10887 move a0, rSELF
10888 daddu a1, rFP, OFF_FP_SHADOWFRAME
10889 daddu ra, ra, (186 * 128) # Addr of primary handler.
10890 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10891
10892/* ------------------------------ */
10893 .balign 128
10894.L_ALT_op_add_long_2addr: /* 0xbb */
10895/* File: mips64/alt_stub.S */
10896/*
10897 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10898 * any interesting requests and then jump to the real instruction
10899 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10900 */
10901 .extern MterpCheckBefore
10902 EXPORT_PC
10903 REFRESH_IBASE
10904 dla ra, artMterpAsmInstructionStart
10905 dla t9, MterpCheckBefore
10906 move a0, rSELF
10907 daddu a1, rFP, OFF_FP_SHADOWFRAME
10908 daddu ra, ra, (187 * 128) # Addr of primary handler.
10909 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10910
10911/* ------------------------------ */
10912 .balign 128
10913.L_ALT_op_sub_long_2addr: /* 0xbc */
10914/* File: mips64/alt_stub.S */
10915/*
10916 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10917 * any interesting requests and then jump to the real instruction
10918 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10919 */
10920 .extern MterpCheckBefore
10921 EXPORT_PC
10922 REFRESH_IBASE
10923 dla ra, artMterpAsmInstructionStart
10924 dla t9, MterpCheckBefore
10925 move a0, rSELF
10926 daddu a1, rFP, OFF_FP_SHADOWFRAME
10927 daddu ra, ra, (188 * 128) # Addr of primary handler.
10928 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10929
10930/* ------------------------------ */
10931 .balign 128
10932.L_ALT_op_mul_long_2addr: /* 0xbd */
10933/* File: mips64/alt_stub.S */
10934/*
10935 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10936 * any interesting requests and then jump to the real instruction
10937 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10938 */
10939 .extern MterpCheckBefore
10940 EXPORT_PC
10941 REFRESH_IBASE
10942 dla ra, artMterpAsmInstructionStart
10943 dla t9, MterpCheckBefore
10944 move a0, rSELF
10945 daddu a1, rFP, OFF_FP_SHADOWFRAME
10946 daddu ra, ra, (189 * 128) # Addr of primary handler.
10947 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10948
10949/* ------------------------------ */
10950 .balign 128
10951.L_ALT_op_div_long_2addr: /* 0xbe */
10952/* File: mips64/alt_stub.S */
10953/*
10954 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10955 * any interesting requests and then jump to the real instruction
10956 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10957 */
10958 .extern MterpCheckBefore
10959 EXPORT_PC
10960 REFRESH_IBASE
10961 dla ra, artMterpAsmInstructionStart
10962 dla t9, MterpCheckBefore
10963 move a0, rSELF
10964 daddu a1, rFP, OFF_FP_SHADOWFRAME
10965 daddu ra, ra, (190 * 128) # Addr of primary handler.
10966 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10967
10968/* ------------------------------ */
10969 .balign 128
10970.L_ALT_op_rem_long_2addr: /* 0xbf */
10971/* File: mips64/alt_stub.S */
10972/*
10973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10974 * any interesting requests and then jump to the real instruction
10975 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10976 */
10977 .extern MterpCheckBefore
10978 EXPORT_PC
10979 REFRESH_IBASE
10980 dla ra, artMterpAsmInstructionStart
10981 dla t9, MterpCheckBefore
10982 move a0, rSELF
10983 daddu a1, rFP, OFF_FP_SHADOWFRAME
10984 daddu ra, ra, (191 * 128) # Addr of primary handler.
10985 jalr zero, t9 # (self, shadow_frame) Note: tail call.
10986
10987/* ------------------------------ */
10988 .balign 128
10989.L_ALT_op_and_long_2addr: /* 0xc0 */
10990/* File: mips64/alt_stub.S */
10991/*
10992 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
10993 * any interesting requests and then jump to the real instruction
10994 * handler. Note that the call to MterpCheckBefore is done as a tail call.
10995 */
10996 .extern MterpCheckBefore
10997 EXPORT_PC
10998 REFRESH_IBASE
10999 dla ra, artMterpAsmInstructionStart
11000 dla t9, MterpCheckBefore
11001 move a0, rSELF
11002 daddu a1, rFP, OFF_FP_SHADOWFRAME
11003 daddu ra, ra, (192 * 128) # Addr of primary handler.
11004 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11005
11006/* ------------------------------ */
11007 .balign 128
11008.L_ALT_op_or_long_2addr: /* 0xc1 */
11009/* File: mips64/alt_stub.S */
11010/*
11011 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11012 * any interesting requests and then jump to the real instruction
11013 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11014 */
11015 .extern MterpCheckBefore
11016 EXPORT_PC
11017 REFRESH_IBASE
11018 dla ra, artMterpAsmInstructionStart
11019 dla t9, MterpCheckBefore
11020 move a0, rSELF
11021 daddu a1, rFP, OFF_FP_SHADOWFRAME
11022 daddu ra, ra, (193 * 128) # Addr of primary handler.
11023 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11024
11025/* ------------------------------ */
11026 .balign 128
11027.L_ALT_op_xor_long_2addr: /* 0xc2 */
11028/* File: mips64/alt_stub.S */
11029/*
11030 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11031 * any interesting requests and then jump to the real instruction
11032 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11033 */
11034 .extern MterpCheckBefore
11035 EXPORT_PC
11036 REFRESH_IBASE
11037 dla ra, artMterpAsmInstructionStart
11038 dla t9, MterpCheckBefore
11039 move a0, rSELF
11040 daddu a1, rFP, OFF_FP_SHADOWFRAME
11041 daddu ra, ra, (194 * 128) # Addr of primary handler.
11042 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11043
11044/* ------------------------------ */
11045 .balign 128
11046.L_ALT_op_shl_long_2addr: /* 0xc3 */
11047/* File: mips64/alt_stub.S */
11048/*
11049 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11050 * any interesting requests and then jump to the real instruction
11051 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11052 */
11053 .extern MterpCheckBefore
11054 EXPORT_PC
11055 REFRESH_IBASE
11056 dla ra, artMterpAsmInstructionStart
11057 dla t9, MterpCheckBefore
11058 move a0, rSELF
11059 daddu a1, rFP, OFF_FP_SHADOWFRAME
11060 daddu ra, ra, (195 * 128) # Addr of primary handler.
11061 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11062
11063/* ------------------------------ */
11064 .balign 128
11065.L_ALT_op_shr_long_2addr: /* 0xc4 */
11066/* File: mips64/alt_stub.S */
11067/*
11068 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11069 * any interesting requests and then jump to the real instruction
11070 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11071 */
11072 .extern MterpCheckBefore
11073 EXPORT_PC
11074 REFRESH_IBASE
11075 dla ra, artMterpAsmInstructionStart
11076 dla t9, MterpCheckBefore
11077 move a0, rSELF
11078 daddu a1, rFP, OFF_FP_SHADOWFRAME
11079 daddu ra, ra, (196 * 128) # Addr of primary handler.
11080 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11081
11082/* ------------------------------ */
11083 .balign 128
11084.L_ALT_op_ushr_long_2addr: /* 0xc5 */
11085/* File: mips64/alt_stub.S */
11086/*
11087 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11088 * any interesting requests and then jump to the real instruction
11089 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11090 */
11091 .extern MterpCheckBefore
11092 EXPORT_PC
11093 REFRESH_IBASE
11094 dla ra, artMterpAsmInstructionStart
11095 dla t9, MterpCheckBefore
11096 move a0, rSELF
11097 daddu a1, rFP, OFF_FP_SHADOWFRAME
11098 daddu ra, ra, (197 * 128) # Addr of primary handler.
11099 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11100
11101/* ------------------------------ */
11102 .balign 128
11103.L_ALT_op_add_float_2addr: /* 0xc6 */
11104/* File: mips64/alt_stub.S */
11105/*
11106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11107 * any interesting requests and then jump to the real instruction
11108 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11109 */
11110 .extern MterpCheckBefore
11111 EXPORT_PC
11112 REFRESH_IBASE
11113 dla ra, artMterpAsmInstructionStart
11114 dla t9, MterpCheckBefore
11115 move a0, rSELF
11116 daddu a1, rFP, OFF_FP_SHADOWFRAME
11117 daddu ra, ra, (198 * 128) # Addr of primary handler.
11118 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11119
11120/* ------------------------------ */
11121 .balign 128
11122.L_ALT_op_sub_float_2addr: /* 0xc7 */
11123/* File: mips64/alt_stub.S */
11124/*
11125 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11126 * any interesting requests and then jump to the real instruction
11127 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11128 */
11129 .extern MterpCheckBefore
11130 EXPORT_PC
11131 REFRESH_IBASE
11132 dla ra, artMterpAsmInstructionStart
11133 dla t9, MterpCheckBefore
11134 move a0, rSELF
11135 daddu a1, rFP, OFF_FP_SHADOWFRAME
11136 daddu ra, ra, (199 * 128) # Addr of primary handler.
11137 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11138
11139/* ------------------------------ */
11140 .balign 128
11141.L_ALT_op_mul_float_2addr: /* 0xc8 */
11142/* File: mips64/alt_stub.S */
11143/*
11144 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11145 * any interesting requests and then jump to the real instruction
11146 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11147 */
11148 .extern MterpCheckBefore
11149 EXPORT_PC
11150 REFRESH_IBASE
11151 dla ra, artMterpAsmInstructionStart
11152 dla t9, MterpCheckBefore
11153 move a0, rSELF
11154 daddu a1, rFP, OFF_FP_SHADOWFRAME
11155 daddu ra, ra, (200 * 128) # Addr of primary handler.
11156 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11157
11158/* ------------------------------ */
11159 .balign 128
11160.L_ALT_op_div_float_2addr: /* 0xc9 */
11161/* File: mips64/alt_stub.S */
11162/*
11163 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11164 * any interesting requests and then jump to the real instruction
11165 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11166 */
11167 .extern MterpCheckBefore
11168 EXPORT_PC
11169 REFRESH_IBASE
11170 dla ra, artMterpAsmInstructionStart
11171 dla t9, MterpCheckBefore
11172 move a0, rSELF
11173 daddu a1, rFP, OFF_FP_SHADOWFRAME
11174 daddu ra, ra, (201 * 128) # Addr of primary handler.
11175 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11176
11177/* ------------------------------ */
11178 .balign 128
11179.L_ALT_op_rem_float_2addr: /* 0xca */
11180/* File: mips64/alt_stub.S */
11181/*
11182 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11183 * any interesting requests and then jump to the real instruction
11184 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11185 */
11186 .extern MterpCheckBefore
11187 EXPORT_PC
11188 REFRESH_IBASE
11189 dla ra, artMterpAsmInstructionStart
11190 dla t9, MterpCheckBefore
11191 move a0, rSELF
11192 daddu a1, rFP, OFF_FP_SHADOWFRAME
11193 daddu ra, ra, (202 * 128) # Addr of primary handler.
11194 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11195
11196/* ------------------------------ */
11197 .balign 128
11198.L_ALT_op_add_double_2addr: /* 0xcb */
11199/* File: mips64/alt_stub.S */
11200/*
11201 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11202 * any interesting requests and then jump to the real instruction
11203 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11204 */
11205 .extern MterpCheckBefore
11206 EXPORT_PC
11207 REFRESH_IBASE
11208 dla ra, artMterpAsmInstructionStart
11209 dla t9, MterpCheckBefore
11210 move a0, rSELF
11211 daddu a1, rFP, OFF_FP_SHADOWFRAME
11212 daddu ra, ra, (203 * 128) # Addr of primary handler.
11213 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11214
11215/* ------------------------------ */
11216 .balign 128
11217.L_ALT_op_sub_double_2addr: /* 0xcc */
11218/* File: mips64/alt_stub.S */
11219/*
11220 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11221 * any interesting requests and then jump to the real instruction
11222 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11223 */
11224 .extern MterpCheckBefore
11225 EXPORT_PC
11226 REFRESH_IBASE
11227 dla ra, artMterpAsmInstructionStart
11228 dla t9, MterpCheckBefore
11229 move a0, rSELF
11230 daddu a1, rFP, OFF_FP_SHADOWFRAME
11231 daddu ra, ra, (204 * 128) # Addr of primary handler.
11232 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11233
11234/* ------------------------------ */
11235 .balign 128
11236.L_ALT_op_mul_double_2addr: /* 0xcd */
11237/* File: mips64/alt_stub.S */
11238/*
11239 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11240 * any interesting requests and then jump to the real instruction
11241 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11242 */
11243 .extern MterpCheckBefore
11244 EXPORT_PC
11245 REFRESH_IBASE
11246 dla ra, artMterpAsmInstructionStart
11247 dla t9, MterpCheckBefore
11248 move a0, rSELF
11249 daddu a1, rFP, OFF_FP_SHADOWFRAME
11250 daddu ra, ra, (205 * 128) # Addr of primary handler.
11251 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11252
11253/* ------------------------------ */
11254 .balign 128
11255.L_ALT_op_div_double_2addr: /* 0xce */
11256/* File: mips64/alt_stub.S */
11257/*
11258 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11259 * any interesting requests and then jump to the real instruction
11260 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11261 */
11262 .extern MterpCheckBefore
11263 EXPORT_PC
11264 REFRESH_IBASE
11265 dla ra, artMterpAsmInstructionStart
11266 dla t9, MterpCheckBefore
11267 move a0, rSELF
11268 daddu a1, rFP, OFF_FP_SHADOWFRAME
11269 daddu ra, ra, (206 * 128) # Addr of primary handler.
11270 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11271
11272/* ------------------------------ */
11273 .balign 128
11274.L_ALT_op_rem_double_2addr: /* 0xcf */
11275/* File: mips64/alt_stub.S */
11276/*
11277 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11278 * any interesting requests and then jump to the real instruction
11279 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11280 */
11281 .extern MterpCheckBefore
11282 EXPORT_PC
11283 REFRESH_IBASE
11284 dla ra, artMterpAsmInstructionStart
11285 dla t9, MterpCheckBefore
11286 move a0, rSELF
11287 daddu a1, rFP, OFF_FP_SHADOWFRAME
11288 daddu ra, ra, (207 * 128) # Addr of primary handler.
11289 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11290
11291/* ------------------------------ */
11292 .balign 128
11293.L_ALT_op_add_int_lit16: /* 0xd0 */
11294/* File: mips64/alt_stub.S */
11295/*
11296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11297 * any interesting requests and then jump to the real instruction
11298 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11299 */
11300 .extern MterpCheckBefore
11301 EXPORT_PC
11302 REFRESH_IBASE
11303 dla ra, artMterpAsmInstructionStart
11304 dla t9, MterpCheckBefore
11305 move a0, rSELF
11306 daddu a1, rFP, OFF_FP_SHADOWFRAME
11307 daddu ra, ra, (208 * 128) # Addr of primary handler.
11308 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11309
11310/* ------------------------------ */
11311 .balign 128
11312.L_ALT_op_rsub_int: /* 0xd1 */
11313/* File: mips64/alt_stub.S */
11314/*
11315 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11316 * any interesting requests and then jump to the real instruction
11317 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11318 */
11319 .extern MterpCheckBefore
11320 EXPORT_PC
11321 REFRESH_IBASE
11322 dla ra, artMterpAsmInstructionStart
11323 dla t9, MterpCheckBefore
11324 move a0, rSELF
11325 daddu a1, rFP, OFF_FP_SHADOWFRAME
11326 daddu ra, ra, (209 * 128) # Addr of primary handler.
11327 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11328
11329/* ------------------------------ */
11330 .balign 128
11331.L_ALT_op_mul_int_lit16: /* 0xd2 */
11332/* File: mips64/alt_stub.S */
11333/*
11334 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11335 * any interesting requests and then jump to the real instruction
11336 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11337 */
11338 .extern MterpCheckBefore
11339 EXPORT_PC
11340 REFRESH_IBASE
11341 dla ra, artMterpAsmInstructionStart
11342 dla t9, MterpCheckBefore
11343 move a0, rSELF
11344 daddu a1, rFP, OFF_FP_SHADOWFRAME
11345 daddu ra, ra, (210 * 128) # Addr of primary handler.
11346 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11347
11348/* ------------------------------ */
11349 .balign 128
11350.L_ALT_op_div_int_lit16: /* 0xd3 */
11351/* File: mips64/alt_stub.S */
11352/*
11353 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11354 * any interesting requests and then jump to the real instruction
11355 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11356 */
11357 .extern MterpCheckBefore
11358 EXPORT_PC
11359 REFRESH_IBASE
11360 dla ra, artMterpAsmInstructionStart
11361 dla t9, MterpCheckBefore
11362 move a0, rSELF
11363 daddu a1, rFP, OFF_FP_SHADOWFRAME
11364 daddu ra, ra, (211 * 128) # Addr of primary handler.
11365 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11366
11367/* ------------------------------ */
11368 .balign 128
11369.L_ALT_op_rem_int_lit16: /* 0xd4 */
11370/* File: mips64/alt_stub.S */
11371/*
11372 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11373 * any interesting requests and then jump to the real instruction
11374 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11375 */
11376 .extern MterpCheckBefore
11377 EXPORT_PC
11378 REFRESH_IBASE
11379 dla ra, artMterpAsmInstructionStart
11380 dla t9, MterpCheckBefore
11381 move a0, rSELF
11382 daddu a1, rFP, OFF_FP_SHADOWFRAME
11383 daddu ra, ra, (212 * 128) # Addr of primary handler.
11384 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11385
11386/* ------------------------------ */
11387 .balign 128
11388.L_ALT_op_and_int_lit16: /* 0xd5 */
11389/* File: mips64/alt_stub.S */
11390/*
11391 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11392 * any interesting requests and then jump to the real instruction
11393 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11394 */
11395 .extern MterpCheckBefore
11396 EXPORT_PC
11397 REFRESH_IBASE
11398 dla ra, artMterpAsmInstructionStart
11399 dla t9, MterpCheckBefore
11400 move a0, rSELF
11401 daddu a1, rFP, OFF_FP_SHADOWFRAME
11402 daddu ra, ra, (213 * 128) # Addr of primary handler.
11403 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11404
11405/* ------------------------------ */
11406 .balign 128
11407.L_ALT_op_or_int_lit16: /* 0xd6 */
11408/* File: mips64/alt_stub.S */
11409/*
11410 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11411 * any interesting requests and then jump to the real instruction
11412 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11413 */
11414 .extern MterpCheckBefore
11415 EXPORT_PC
11416 REFRESH_IBASE
11417 dla ra, artMterpAsmInstructionStart
11418 dla t9, MterpCheckBefore
11419 move a0, rSELF
11420 daddu a1, rFP, OFF_FP_SHADOWFRAME
11421 daddu ra, ra, (214 * 128) # Addr of primary handler.
11422 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11423
11424/* ------------------------------ */
11425 .balign 128
11426.L_ALT_op_xor_int_lit16: /* 0xd7 */
11427/* File: mips64/alt_stub.S */
11428/*
11429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11430 * any interesting requests and then jump to the real instruction
11431 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11432 */
11433 .extern MterpCheckBefore
11434 EXPORT_PC
11435 REFRESH_IBASE
11436 dla ra, artMterpAsmInstructionStart
11437 dla t9, MterpCheckBefore
11438 move a0, rSELF
11439 daddu a1, rFP, OFF_FP_SHADOWFRAME
11440 daddu ra, ra, (215 * 128) # Addr of primary handler.
11441 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11442
11443/* ------------------------------ */
11444 .balign 128
11445.L_ALT_op_add_int_lit8: /* 0xd8 */
11446/* File: mips64/alt_stub.S */
11447/*
11448 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11449 * any interesting requests and then jump to the real instruction
11450 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11451 */
11452 .extern MterpCheckBefore
11453 EXPORT_PC
11454 REFRESH_IBASE
11455 dla ra, artMterpAsmInstructionStart
11456 dla t9, MterpCheckBefore
11457 move a0, rSELF
11458 daddu a1, rFP, OFF_FP_SHADOWFRAME
11459 daddu ra, ra, (216 * 128) # Addr of primary handler.
11460 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11461
11462/* ------------------------------ */
11463 .balign 128
11464.L_ALT_op_rsub_int_lit8: /* 0xd9 */
11465/* File: mips64/alt_stub.S */
11466/*
11467 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11468 * any interesting requests and then jump to the real instruction
11469 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11470 */
11471 .extern MterpCheckBefore
11472 EXPORT_PC
11473 REFRESH_IBASE
11474 dla ra, artMterpAsmInstructionStart
11475 dla t9, MterpCheckBefore
11476 move a0, rSELF
11477 daddu a1, rFP, OFF_FP_SHADOWFRAME
11478 daddu ra, ra, (217 * 128) # Addr of primary handler.
11479 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11480
11481/* ------------------------------ */
11482 .balign 128
11483.L_ALT_op_mul_int_lit8: /* 0xda */
11484/* File: mips64/alt_stub.S */
11485/*
11486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11487 * any interesting requests and then jump to the real instruction
11488 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11489 */
11490 .extern MterpCheckBefore
11491 EXPORT_PC
11492 REFRESH_IBASE
11493 dla ra, artMterpAsmInstructionStart
11494 dla t9, MterpCheckBefore
11495 move a0, rSELF
11496 daddu a1, rFP, OFF_FP_SHADOWFRAME
11497 daddu ra, ra, (218 * 128) # Addr of primary handler.
11498 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11499
11500/* ------------------------------ */
11501 .balign 128
11502.L_ALT_op_div_int_lit8: /* 0xdb */
11503/* File: mips64/alt_stub.S */
11504/*
11505 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11506 * any interesting requests and then jump to the real instruction
11507 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11508 */
11509 .extern MterpCheckBefore
11510 EXPORT_PC
11511 REFRESH_IBASE
11512 dla ra, artMterpAsmInstructionStart
11513 dla t9, MterpCheckBefore
11514 move a0, rSELF
11515 daddu a1, rFP, OFF_FP_SHADOWFRAME
11516 daddu ra, ra, (219 * 128) # Addr of primary handler.
11517 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11518
11519/* ------------------------------ */
11520 .balign 128
11521.L_ALT_op_rem_int_lit8: /* 0xdc */
11522/* File: mips64/alt_stub.S */
11523/*
11524 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11525 * any interesting requests and then jump to the real instruction
11526 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11527 */
11528 .extern MterpCheckBefore
11529 EXPORT_PC
11530 REFRESH_IBASE
11531 dla ra, artMterpAsmInstructionStart
11532 dla t9, MterpCheckBefore
11533 move a0, rSELF
11534 daddu a1, rFP, OFF_FP_SHADOWFRAME
11535 daddu ra, ra, (220 * 128) # Addr of primary handler.
11536 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11537
11538/* ------------------------------ */
11539 .balign 128
11540.L_ALT_op_and_int_lit8: /* 0xdd */
11541/* File: mips64/alt_stub.S */
11542/*
11543 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11544 * any interesting requests and then jump to the real instruction
11545 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11546 */
11547 .extern MterpCheckBefore
11548 EXPORT_PC
11549 REFRESH_IBASE
11550 dla ra, artMterpAsmInstructionStart
11551 dla t9, MterpCheckBefore
11552 move a0, rSELF
11553 daddu a1, rFP, OFF_FP_SHADOWFRAME
11554 daddu ra, ra, (221 * 128) # Addr of primary handler.
11555 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11556
11557/* ------------------------------ */
11558 .balign 128
11559.L_ALT_op_or_int_lit8: /* 0xde */
11560/* File: mips64/alt_stub.S */
11561/*
11562 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11563 * any interesting requests and then jump to the real instruction
11564 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11565 */
11566 .extern MterpCheckBefore
11567 EXPORT_PC
11568 REFRESH_IBASE
11569 dla ra, artMterpAsmInstructionStart
11570 dla t9, MterpCheckBefore
11571 move a0, rSELF
11572 daddu a1, rFP, OFF_FP_SHADOWFRAME
11573 daddu ra, ra, (222 * 128) # Addr of primary handler.
11574 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11575
11576/* ------------------------------ */
11577 .balign 128
11578.L_ALT_op_xor_int_lit8: /* 0xdf */
11579/* File: mips64/alt_stub.S */
11580/*
11581 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11582 * any interesting requests and then jump to the real instruction
11583 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11584 */
11585 .extern MterpCheckBefore
11586 EXPORT_PC
11587 REFRESH_IBASE
11588 dla ra, artMterpAsmInstructionStart
11589 dla t9, MterpCheckBefore
11590 move a0, rSELF
11591 daddu a1, rFP, OFF_FP_SHADOWFRAME
11592 daddu ra, ra, (223 * 128) # Addr of primary handler.
11593 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11594
11595/* ------------------------------ */
11596 .balign 128
11597.L_ALT_op_shl_int_lit8: /* 0xe0 */
11598/* File: mips64/alt_stub.S */
11599/*
11600 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11601 * any interesting requests and then jump to the real instruction
11602 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11603 */
11604 .extern MterpCheckBefore
11605 EXPORT_PC
11606 REFRESH_IBASE
11607 dla ra, artMterpAsmInstructionStart
11608 dla t9, MterpCheckBefore
11609 move a0, rSELF
11610 daddu a1, rFP, OFF_FP_SHADOWFRAME
11611 daddu ra, ra, (224 * 128) # Addr of primary handler.
11612 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11613
11614/* ------------------------------ */
11615 .balign 128
11616.L_ALT_op_shr_int_lit8: /* 0xe1 */
11617/* File: mips64/alt_stub.S */
11618/*
11619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11620 * any interesting requests and then jump to the real instruction
11621 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11622 */
11623 .extern MterpCheckBefore
11624 EXPORT_PC
11625 REFRESH_IBASE
11626 dla ra, artMterpAsmInstructionStart
11627 dla t9, MterpCheckBefore
11628 move a0, rSELF
11629 daddu a1, rFP, OFF_FP_SHADOWFRAME
11630 daddu ra, ra, (225 * 128) # Addr of primary handler.
11631 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11632
11633/* ------------------------------ */
11634 .balign 128
11635.L_ALT_op_ushr_int_lit8: /* 0xe2 */
11636/* File: mips64/alt_stub.S */
11637/*
11638 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11639 * any interesting requests and then jump to the real instruction
11640 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11641 */
11642 .extern MterpCheckBefore
11643 EXPORT_PC
11644 REFRESH_IBASE
11645 dla ra, artMterpAsmInstructionStart
11646 dla t9, MterpCheckBefore
11647 move a0, rSELF
11648 daddu a1, rFP, OFF_FP_SHADOWFRAME
11649 daddu ra, ra, (226 * 128) # Addr of primary handler.
11650 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11651
11652/* ------------------------------ */
11653 .balign 128
11654.L_ALT_op_iget_quick: /* 0xe3 */
11655/* File: mips64/alt_stub.S */
11656/*
11657 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11658 * any interesting requests and then jump to the real instruction
11659 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11660 */
11661 .extern MterpCheckBefore
11662 EXPORT_PC
11663 REFRESH_IBASE
11664 dla ra, artMterpAsmInstructionStart
11665 dla t9, MterpCheckBefore
11666 move a0, rSELF
11667 daddu a1, rFP, OFF_FP_SHADOWFRAME
11668 daddu ra, ra, (227 * 128) # Addr of primary handler.
11669 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11670
11671/* ------------------------------ */
11672 .balign 128
11673.L_ALT_op_iget_wide_quick: /* 0xe4 */
11674/* File: mips64/alt_stub.S */
11675/*
11676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11677 * any interesting requests and then jump to the real instruction
11678 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11679 */
11680 .extern MterpCheckBefore
11681 EXPORT_PC
11682 REFRESH_IBASE
11683 dla ra, artMterpAsmInstructionStart
11684 dla t9, MterpCheckBefore
11685 move a0, rSELF
11686 daddu a1, rFP, OFF_FP_SHADOWFRAME
11687 daddu ra, ra, (228 * 128) # Addr of primary handler.
11688 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11689
11690/* ------------------------------ */
11691 .balign 128
11692.L_ALT_op_iget_object_quick: /* 0xe5 */
11693/* File: mips64/alt_stub.S */
11694/*
11695 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11696 * any interesting requests and then jump to the real instruction
11697 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11698 */
11699 .extern MterpCheckBefore
11700 EXPORT_PC
11701 REFRESH_IBASE
11702 dla ra, artMterpAsmInstructionStart
11703 dla t9, MterpCheckBefore
11704 move a0, rSELF
11705 daddu a1, rFP, OFF_FP_SHADOWFRAME
11706 daddu ra, ra, (229 * 128) # Addr of primary handler.
11707 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11708
11709/* ------------------------------ */
11710 .balign 128
11711.L_ALT_op_iput_quick: /* 0xe6 */
11712/* File: mips64/alt_stub.S */
11713/*
11714 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11715 * any interesting requests and then jump to the real instruction
11716 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11717 */
11718 .extern MterpCheckBefore
11719 EXPORT_PC
11720 REFRESH_IBASE
11721 dla ra, artMterpAsmInstructionStart
11722 dla t9, MterpCheckBefore
11723 move a0, rSELF
11724 daddu a1, rFP, OFF_FP_SHADOWFRAME
11725 daddu ra, ra, (230 * 128) # Addr of primary handler.
11726 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11727
11728/* ------------------------------ */
11729 .balign 128
11730.L_ALT_op_iput_wide_quick: /* 0xe7 */
11731/* File: mips64/alt_stub.S */
11732/*
11733 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11734 * any interesting requests and then jump to the real instruction
11735 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11736 */
11737 .extern MterpCheckBefore
11738 EXPORT_PC
11739 REFRESH_IBASE
11740 dla ra, artMterpAsmInstructionStart
11741 dla t9, MterpCheckBefore
11742 move a0, rSELF
11743 daddu a1, rFP, OFF_FP_SHADOWFRAME
11744 daddu ra, ra, (231 * 128) # Addr of primary handler.
11745 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11746
11747/* ------------------------------ */
11748 .balign 128
11749.L_ALT_op_iput_object_quick: /* 0xe8 */
11750/* File: mips64/alt_stub.S */
11751/*
11752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11753 * any interesting requests and then jump to the real instruction
11754 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11755 */
11756 .extern MterpCheckBefore
11757 EXPORT_PC
11758 REFRESH_IBASE
11759 dla ra, artMterpAsmInstructionStart
11760 dla t9, MterpCheckBefore
11761 move a0, rSELF
11762 daddu a1, rFP, OFF_FP_SHADOWFRAME
11763 daddu ra, ra, (232 * 128) # Addr of primary handler.
11764 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11765
11766/* ------------------------------ */
11767 .balign 128
11768.L_ALT_op_invoke_virtual_quick: /* 0xe9 */
11769/* File: mips64/alt_stub.S */
11770/*
11771 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11772 * any interesting requests and then jump to the real instruction
11773 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11774 */
11775 .extern MterpCheckBefore
11776 EXPORT_PC
11777 REFRESH_IBASE
11778 dla ra, artMterpAsmInstructionStart
11779 dla t9, MterpCheckBefore
11780 move a0, rSELF
11781 daddu a1, rFP, OFF_FP_SHADOWFRAME
11782 daddu ra, ra, (233 * 128) # Addr of primary handler.
11783 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11784
11785/* ------------------------------ */
11786 .balign 128
11787.L_ALT_op_invoke_virtual_range_quick: /* 0xea */
11788/* File: mips64/alt_stub.S */
11789/*
11790 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11791 * any interesting requests and then jump to the real instruction
11792 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11793 */
11794 .extern MterpCheckBefore
11795 EXPORT_PC
11796 REFRESH_IBASE
11797 dla ra, artMterpAsmInstructionStart
11798 dla t9, MterpCheckBefore
11799 move a0, rSELF
11800 daddu a1, rFP, OFF_FP_SHADOWFRAME
11801 daddu ra, ra, (234 * 128) # Addr of primary handler.
11802 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11803
11804/* ------------------------------ */
11805 .balign 128
11806.L_ALT_op_iput_boolean_quick: /* 0xeb */
11807/* File: mips64/alt_stub.S */
11808/*
11809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11810 * any interesting requests and then jump to the real instruction
11811 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11812 */
11813 .extern MterpCheckBefore
11814 EXPORT_PC
11815 REFRESH_IBASE
11816 dla ra, artMterpAsmInstructionStart
11817 dla t9, MterpCheckBefore
11818 move a0, rSELF
11819 daddu a1, rFP, OFF_FP_SHADOWFRAME
11820 daddu ra, ra, (235 * 128) # Addr of primary handler.
11821 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11822
11823/* ------------------------------ */
11824 .balign 128
11825.L_ALT_op_iput_byte_quick: /* 0xec */
11826/* File: mips64/alt_stub.S */
11827/*
11828 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11829 * any interesting requests and then jump to the real instruction
11830 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11831 */
11832 .extern MterpCheckBefore
11833 EXPORT_PC
11834 REFRESH_IBASE
11835 dla ra, artMterpAsmInstructionStart
11836 dla t9, MterpCheckBefore
11837 move a0, rSELF
11838 daddu a1, rFP, OFF_FP_SHADOWFRAME
11839 daddu ra, ra, (236 * 128) # Addr of primary handler.
11840 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11841
11842/* ------------------------------ */
11843 .balign 128
11844.L_ALT_op_iput_char_quick: /* 0xed */
11845/* File: mips64/alt_stub.S */
11846/*
11847 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11848 * any interesting requests and then jump to the real instruction
11849 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11850 */
11851 .extern MterpCheckBefore
11852 EXPORT_PC
11853 REFRESH_IBASE
11854 dla ra, artMterpAsmInstructionStart
11855 dla t9, MterpCheckBefore
11856 move a0, rSELF
11857 daddu a1, rFP, OFF_FP_SHADOWFRAME
11858 daddu ra, ra, (237 * 128) # Addr of primary handler.
11859 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11860
11861/* ------------------------------ */
11862 .balign 128
11863.L_ALT_op_iput_short_quick: /* 0xee */
11864/* File: mips64/alt_stub.S */
11865/*
11866 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11867 * any interesting requests and then jump to the real instruction
11868 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11869 */
11870 .extern MterpCheckBefore
11871 EXPORT_PC
11872 REFRESH_IBASE
11873 dla ra, artMterpAsmInstructionStart
11874 dla t9, MterpCheckBefore
11875 move a0, rSELF
11876 daddu a1, rFP, OFF_FP_SHADOWFRAME
11877 daddu ra, ra, (238 * 128) # Addr of primary handler.
11878 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11879
11880/* ------------------------------ */
11881 .balign 128
11882.L_ALT_op_iget_boolean_quick: /* 0xef */
11883/* File: mips64/alt_stub.S */
11884/*
11885 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11886 * any interesting requests and then jump to the real instruction
11887 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11888 */
11889 .extern MterpCheckBefore
11890 EXPORT_PC
11891 REFRESH_IBASE
11892 dla ra, artMterpAsmInstructionStart
11893 dla t9, MterpCheckBefore
11894 move a0, rSELF
11895 daddu a1, rFP, OFF_FP_SHADOWFRAME
11896 daddu ra, ra, (239 * 128) # Addr of primary handler.
11897 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11898
11899/* ------------------------------ */
11900 .balign 128
11901.L_ALT_op_iget_byte_quick: /* 0xf0 */
11902/* File: mips64/alt_stub.S */
11903/*
11904 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11905 * any interesting requests and then jump to the real instruction
11906 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11907 */
11908 .extern MterpCheckBefore
11909 EXPORT_PC
11910 REFRESH_IBASE
11911 dla ra, artMterpAsmInstructionStart
11912 dla t9, MterpCheckBefore
11913 move a0, rSELF
11914 daddu a1, rFP, OFF_FP_SHADOWFRAME
11915 daddu ra, ra, (240 * 128) # Addr of primary handler.
11916 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11917
11918/* ------------------------------ */
11919 .balign 128
11920.L_ALT_op_iget_char_quick: /* 0xf1 */
11921/* File: mips64/alt_stub.S */
11922/*
11923 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11924 * any interesting requests and then jump to the real instruction
11925 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11926 */
11927 .extern MterpCheckBefore
11928 EXPORT_PC
11929 REFRESH_IBASE
11930 dla ra, artMterpAsmInstructionStart
11931 dla t9, MterpCheckBefore
11932 move a0, rSELF
11933 daddu a1, rFP, OFF_FP_SHADOWFRAME
11934 daddu ra, ra, (241 * 128) # Addr of primary handler.
11935 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11936
11937/* ------------------------------ */
11938 .balign 128
11939.L_ALT_op_iget_short_quick: /* 0xf2 */
11940/* File: mips64/alt_stub.S */
11941/*
11942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11943 * any interesting requests and then jump to the real instruction
11944 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11945 */
11946 .extern MterpCheckBefore
11947 EXPORT_PC
11948 REFRESH_IBASE
11949 dla ra, artMterpAsmInstructionStart
11950 dla t9, MterpCheckBefore
11951 move a0, rSELF
11952 daddu a1, rFP, OFF_FP_SHADOWFRAME
11953 daddu ra, ra, (242 * 128) # Addr of primary handler.
11954 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11955
11956/* ------------------------------ */
11957 .balign 128
11958.L_ALT_op_invoke_lambda: /* 0xf3 */
11959/* File: mips64/alt_stub.S */
11960/*
11961 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11962 * any interesting requests and then jump to the real instruction
11963 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11964 */
11965 .extern MterpCheckBefore
11966 EXPORT_PC
11967 REFRESH_IBASE
11968 dla ra, artMterpAsmInstructionStart
11969 dla t9, MterpCheckBefore
11970 move a0, rSELF
11971 daddu a1, rFP, OFF_FP_SHADOWFRAME
11972 daddu ra, ra, (243 * 128) # Addr of primary handler.
11973 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11974
11975/* ------------------------------ */
11976 .balign 128
11977.L_ALT_op_unused_f4: /* 0xf4 */
11978/* File: mips64/alt_stub.S */
11979/*
11980 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
11981 * any interesting requests and then jump to the real instruction
11982 * handler. Note that the call to MterpCheckBefore is done as a tail call.
11983 */
11984 .extern MterpCheckBefore
11985 EXPORT_PC
11986 REFRESH_IBASE
11987 dla ra, artMterpAsmInstructionStart
11988 dla t9, MterpCheckBefore
11989 move a0, rSELF
11990 daddu a1, rFP, OFF_FP_SHADOWFRAME
11991 daddu ra, ra, (244 * 128) # Addr of primary handler.
11992 jalr zero, t9 # (self, shadow_frame) Note: tail call.
11993
11994/* ------------------------------ */
11995 .balign 128
11996.L_ALT_op_capture_variable: /* 0xf5 */
11997/* File: mips64/alt_stub.S */
11998/*
11999 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12000 * any interesting requests and then jump to the real instruction
12001 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12002 */
12003 .extern MterpCheckBefore
12004 EXPORT_PC
12005 REFRESH_IBASE
12006 dla ra, artMterpAsmInstructionStart
12007 dla t9, MterpCheckBefore
12008 move a0, rSELF
12009 daddu a1, rFP, OFF_FP_SHADOWFRAME
12010 daddu ra, ra, (245 * 128) # Addr of primary handler.
12011 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12012
12013/* ------------------------------ */
12014 .balign 128
12015.L_ALT_op_create_lambda: /* 0xf6 */
12016/* File: mips64/alt_stub.S */
12017/*
12018 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12019 * any interesting requests and then jump to the real instruction
12020 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12021 */
12022 .extern MterpCheckBefore
12023 EXPORT_PC
12024 REFRESH_IBASE
12025 dla ra, artMterpAsmInstructionStart
12026 dla t9, MterpCheckBefore
12027 move a0, rSELF
12028 daddu a1, rFP, OFF_FP_SHADOWFRAME
12029 daddu ra, ra, (246 * 128) # Addr of primary handler.
12030 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12031
12032/* ------------------------------ */
12033 .balign 128
12034.L_ALT_op_liberate_variable: /* 0xf7 */
12035/* File: mips64/alt_stub.S */
12036/*
12037 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12038 * any interesting requests and then jump to the real instruction
12039 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12040 */
12041 .extern MterpCheckBefore
12042 EXPORT_PC
12043 REFRESH_IBASE
12044 dla ra, artMterpAsmInstructionStart
12045 dla t9, MterpCheckBefore
12046 move a0, rSELF
12047 daddu a1, rFP, OFF_FP_SHADOWFRAME
12048 daddu ra, ra, (247 * 128) # Addr of primary handler.
12049 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12050
12051/* ------------------------------ */
12052 .balign 128
12053.L_ALT_op_box_lambda: /* 0xf8 */
12054/* File: mips64/alt_stub.S */
12055/*
12056 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12057 * any interesting requests and then jump to the real instruction
12058 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12059 */
12060 .extern MterpCheckBefore
12061 EXPORT_PC
12062 REFRESH_IBASE
12063 dla ra, artMterpAsmInstructionStart
12064 dla t9, MterpCheckBefore
12065 move a0, rSELF
12066 daddu a1, rFP, OFF_FP_SHADOWFRAME
12067 daddu ra, ra, (248 * 128) # Addr of primary handler.
12068 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12069
12070/* ------------------------------ */
12071 .balign 128
12072.L_ALT_op_unbox_lambda: /* 0xf9 */
12073/* File: mips64/alt_stub.S */
12074/*
12075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12076 * any interesting requests and then jump to the real instruction
12077 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12078 */
12079 .extern MterpCheckBefore
12080 EXPORT_PC
12081 REFRESH_IBASE
12082 dla ra, artMterpAsmInstructionStart
12083 dla t9, MterpCheckBefore
12084 move a0, rSELF
12085 daddu a1, rFP, OFF_FP_SHADOWFRAME
12086 daddu ra, ra, (249 * 128) # Addr of primary handler.
12087 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12088
12089/* ------------------------------ */
12090 .balign 128
12091.L_ALT_op_unused_fa: /* 0xfa */
12092/* File: mips64/alt_stub.S */
12093/*
12094 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12095 * any interesting requests and then jump to the real instruction
12096 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12097 */
12098 .extern MterpCheckBefore
12099 EXPORT_PC
12100 REFRESH_IBASE
12101 dla ra, artMterpAsmInstructionStart
12102 dla t9, MterpCheckBefore
12103 move a0, rSELF
12104 daddu a1, rFP, OFF_FP_SHADOWFRAME
12105 daddu ra, ra, (250 * 128) # Addr of primary handler.
12106 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12107
12108/* ------------------------------ */
12109 .balign 128
12110.L_ALT_op_unused_fb: /* 0xfb */
12111/* File: mips64/alt_stub.S */
12112/*
12113 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12114 * any interesting requests and then jump to the real instruction
12115 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12116 */
12117 .extern MterpCheckBefore
12118 EXPORT_PC
12119 REFRESH_IBASE
12120 dla ra, artMterpAsmInstructionStart
12121 dla t9, MterpCheckBefore
12122 move a0, rSELF
12123 daddu a1, rFP, OFF_FP_SHADOWFRAME
12124 daddu ra, ra, (251 * 128) # Addr of primary handler.
12125 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12126
12127/* ------------------------------ */
12128 .balign 128
12129.L_ALT_op_unused_fc: /* 0xfc */
12130/* File: mips64/alt_stub.S */
12131/*
12132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12133 * any interesting requests and then jump to the real instruction
12134 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12135 */
12136 .extern MterpCheckBefore
12137 EXPORT_PC
12138 REFRESH_IBASE
12139 dla ra, artMterpAsmInstructionStart
12140 dla t9, MterpCheckBefore
12141 move a0, rSELF
12142 daddu a1, rFP, OFF_FP_SHADOWFRAME
12143 daddu ra, ra, (252 * 128) # Addr of primary handler.
12144 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12145
12146/* ------------------------------ */
12147 .balign 128
12148.L_ALT_op_unused_fd: /* 0xfd */
12149/* File: mips64/alt_stub.S */
12150/*
12151 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12152 * any interesting requests and then jump to the real instruction
12153 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12154 */
12155 .extern MterpCheckBefore
12156 EXPORT_PC
12157 REFRESH_IBASE
12158 dla ra, artMterpAsmInstructionStart
12159 dla t9, MterpCheckBefore
12160 move a0, rSELF
12161 daddu a1, rFP, OFF_FP_SHADOWFRAME
12162 daddu ra, ra, (253 * 128) # Addr of primary handler.
12163 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12164
12165/* ------------------------------ */
12166 .balign 128
12167.L_ALT_op_unused_fe: /* 0xfe */
12168/* File: mips64/alt_stub.S */
12169/*
12170 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12171 * any interesting requests and then jump to the real instruction
12172 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12173 */
12174 .extern MterpCheckBefore
12175 EXPORT_PC
12176 REFRESH_IBASE
12177 dla ra, artMterpAsmInstructionStart
12178 dla t9, MterpCheckBefore
12179 move a0, rSELF
12180 daddu a1, rFP, OFF_FP_SHADOWFRAME
12181 daddu ra, ra, (254 * 128) # Addr of primary handler.
12182 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12183
12184/* ------------------------------ */
12185 .balign 128
12186.L_ALT_op_unused_ff: /* 0xff */
12187/* File: mips64/alt_stub.S */
12188/*
12189 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle
12190 * any interesting requests and then jump to the real instruction
12191 * handler. Note that the call to MterpCheckBefore is done as a tail call.
12192 */
12193 .extern MterpCheckBefore
12194 EXPORT_PC
12195 REFRESH_IBASE
12196 dla ra, artMterpAsmInstructionStart
12197 dla t9, MterpCheckBefore
12198 move a0, rSELF
12199 daddu a1, rFP, OFF_FP_SHADOWFRAME
12200 daddu ra, ra, (255 * 128) # Addr of primary handler.
12201 jalr zero, t9 # (self, shadow_frame) Note: tail call.
12202
12203 .balign 128
12204 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart
12205 .global artMterpAsmAltInstructionEnd
12206artMterpAsmAltInstructionEnd:
12207/* File: mips64/footer.S */
12208/*
12209 * We've detected a condition that will result in an exception, but the exception
12210 * has not yet been thrown. Just bail out to the reference interpreter to deal with it.
12211 * TUNING: for consistency, we may want to just go ahead and handle these here.
12212 */
12213
12214 .extern MterpLogDivideByZeroException
12215common_errDivideByZero:
12216 EXPORT_PC
12217#if MTERP_LOGGING
12218 move a0, rSELF
12219 daddu a1, rFP, OFF_FP_SHADOWFRAME
12220 jal MterpLogDivideByZeroException
12221#endif
12222 b MterpCommonFallback
12223
12224 .extern MterpLogArrayIndexException
12225common_errArrayIndex:
12226 EXPORT_PC
12227#if MTERP_LOGGING
12228 move a0, rSELF
12229 daddu a1, rFP, OFF_FP_SHADOWFRAME
12230 jal MterpLogArrayIndexException
12231#endif
12232 b MterpCommonFallback
12233
12234 .extern MterpLogNullObjectException
12235common_errNullObject:
12236 EXPORT_PC
12237#if MTERP_LOGGING
12238 move a0, rSELF
12239 daddu a1, rFP, OFF_FP_SHADOWFRAME
12240 jal MterpLogNullObjectException
12241#endif
12242 b MterpCommonFallback
12243
12244/*
12245 * If we're here, something is out of the ordinary. If there is a pending
12246 * exception, handle it. Otherwise, roll back and retry with the reference
12247 * interpreter.
12248 */
12249MterpPossibleException:
12250 ld a0, THREAD_EXCEPTION_OFFSET(rSELF)
12251 beqzc a0, MterpFallback # If not, fall back to reference interpreter.
12252 /* intentional fallthrough - handle pending exception. */
12253/*
12254 * On return from a runtime helper routine, we've found a pending exception.
12255 * Can we handle it here - or need to bail out to caller?
12256 *
12257 */
12258 .extern MterpHandleException
12259MterpException:
12260 move a0, rSELF
12261 daddu a1, rFP, OFF_FP_SHADOWFRAME
12262 jal MterpHandleException # (self, shadow_frame)
12263 beqzc v0, MterpExceptionReturn # no local catch, back to caller.
12264 ld a0, OFF_FP_CODE_ITEM(rFP)
12265 lwu a1, OFF_FP_DEX_PC(rFP)
12266 REFRESH_IBASE
12267 daddu rPC, a0, CODEITEM_INSNS_OFFSET
12268 dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr
12269 sd rPC, OFF_FP_DEX_PC_PTR(rFP)
12270 /* resume execution at catch block */
12271 FETCH_INST
12272 GET_INST_OPCODE v0
12273 GOTO_OPCODE v0
12274 /* NOTE: no fallthrough */
12275
12276/*
12277 * Check for suspend check request. Assumes rINST already loaded, rPC advanced and
12278 * still needs to get the opcode and branch to it, and flags are in ra.
12279 */
12280 .extern MterpSuspendCheck
12281MterpCheckSuspendAndContinue:
12282 REFRESH_IBASE
12283 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
12284 bnez ra, check1
12285 GET_INST_OPCODE v0 # extract opcode from rINST
12286 GOTO_OPCODE v0 # jump to next instruction
12287check1:
12288 EXPORT_PC
12289 move a0, rSELF
12290 jal MterpSuspendCheck # (self)
12291 GET_INST_OPCODE v0 # extract opcode from rINST
12292 GOTO_OPCODE v0 # jump to next instruction
12293
12294/*
12295 * Bail out to reference interpreter.
12296 */
12297 .extern MterpLogFallback
12298MterpFallback:
12299 EXPORT_PC
12300#if MTERP_LOGGING
12301 move a0, rSELF
12302 daddu a1, rFP, OFF_FP_SHADOWFRAME
12303 jal MterpLogFallback
12304#endif
12305MterpCommonFallback:
12306 li v0, 0 # signal retry with reference interpreter.
12307 b MterpDone
12308
12309/*
12310 * We pushed some registers on the stack in ExecuteMterpImpl, then saved
12311 * SP and RA. Here we restore SP, restore the registers, and then restore
12312 * RA to PC.
12313 *
12314 * On entry:
12315 * uint32_t* rFP (should still be live, pointer to base of vregs)
12316 */
12317MterpExceptionReturn:
12318 li v0, 1 # signal return to caller.
12319 b MterpDone
12320/*
12321 * Returned value is expected in a0 and if it's not 64-bit, the 32 most
12322 * significant bits of a0 must be 0.
12323 */
12324MterpReturn:
12325 ld a2, OFF_FP_RESULT_REGISTER(rFP)
12326 lw ra, THREAD_FLAGS_OFFSET(rSELF)
12327 sd a0, 0(a2)
12328 move a0, rSELF
12329 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
12330 beqzc ra, check2
12331 jal MterpSuspendCheck # (self)
12332check2:
12333 li v0, 1 # signal return to caller.
12334MterpDone:
12335 ld s5, STACK_OFFSET_S5(sp)
12336 .cfi_restore 21
12337 ld s4, STACK_OFFSET_S4(sp)
12338 .cfi_restore 20
12339 ld s3, STACK_OFFSET_S3(sp)
12340 .cfi_restore 19
12341 ld s2, STACK_OFFSET_S2(sp)
12342 .cfi_restore 18
12343 ld s1, STACK_OFFSET_S1(sp)
12344 .cfi_restore 17
12345 ld s0, STACK_OFFSET_S0(sp)
12346 .cfi_restore 16
12347
12348 ld ra, STACK_OFFSET_RA(sp)
12349 .cfi_restore 31
12350
12351 ld t8, STACK_OFFSET_GP(sp)
12352 .cpreturn
12353 .cfi_restore 28
12354
12355 .set noreorder
12356 jr ra
12357 daddu sp, sp, STACK_SIZE
12358 .cfi_adjust_cfa_offset -STACK_SIZE
12359
12360 .cfi_endproc
12361 .size ExecuteMterpImpl, .-ExecuteMterpImpl
12362