1. cfa59b4 Basic SIMD reduction support. by Aart Bik · 8 years ago
  2. a57b4ee Revert "Basic SIMD reduction support." by Aart Bik · 8 years ago
  3. 9879d0e Basic SIMD reduction support. by Aart Bik · 8 years ago
  4. b79f4ac Added GVN related attributes to vector nodes. by Aart Bik · 8 years ago
  5. 9858bf7 Revert "Added GVN related attributes to vector nodes." by Nicolas Geoffray · 8 years ago
  6. a79f0b5 Added GVN related attributes to vector nodes. by Aart Bik · 8 years ago
  7. a1633a7 Merge "Min/max SIMDization support." by Aart Bik · 8 years ago
  8. c8e93c7 Min/max SIMDization support. by Aart Bik · 8 years ago
  9. e1811ed ARM64: Share address computation across SIMD LDRs/STRs. by Artem Serov · 8 years ago
  10. d58bc32 Allow same-length integral type mixing in SIMD. by Aart Bik · 8 years ago
  11. db14fcf Pack booleans in the already existing bit field. by Aart Bik · 8 years ago
  12. 8de5916 Factor vector unary/binary shared code out into superclass. by Aart Bik · 8 years ago
  13. f34dd20 ARM64: Support MultiplyAccumulate for SIMD. by Artem Serov · 8 years ago
  14. f3e61ee Implement halving add idiom (with checker tests). by Aart Bik · 8 years ago
  15. 6daebeb Implemented ABS vectorization. by Aart Bik · 8 years ago
  16. f8f5a16 ART vectorizer. by Aart Bik · 8 years ago