| commit | c86950cb3f50ead0c9a9d0366b870d6c6e1b91c8 | [log] [tgz] |
|---|---|---|
| author | Duane Sand <duane.sand@imgtec.com> | Mon Jul 14 15:30:14 2014 -0700 |
| committer | Elliott Hughes <enh@google.com> | Wed Jul 23 21:04:20 2014 -0700 |
| tree | b21dc20111743fbbacc80bc8a06ca794dfef2333 | |
| parent | bc74ecfaf5de47056fd8a48db65c0e5aef892f0c [diff] |
[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models Save and restore floating point registers via 64-bit load/stores when possible. Use assembler's builtin macro ops to generate pairs of 32-bit load/stores on Mips I cpus. Some cpus or FR modes have only 16 even-numbered dp fp regs. This is exposed by _MIPS_FPSET, defined by existing compilers. (cherry picked from commit dd37251c473e1483faba0fd5aaf30e7a55582e8a) Change-Id: Ibd43653701a363a77af85121d3cbd229d132a06a