Clean up some ARMv4/ARMv5 cruft.
Change-Id: I29e836fea4b53901e29f96c6888869c35f6726be
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S
index 0dc86d5..f25b3e3 100644
--- a/libc/arch-arm/bionic/memcpy.S
+++ b/libc/arch-arm/bionic/memcpy.S
@@ -352,9 +352,9 @@
// preload the destination because we'll align it to a cache line
// with small writes. Also start the source "pump".
- PLD (r0, #0)
- PLD (r1, #0)
- PLD (r1, #32)
+ pld [r0, #0]
+ pld [r1, #0]
+ pld [r1, #32]
/* it simplifies things to take care of len<4 early */
cmp r2, #4
@@ -442,7 +442,7 @@
add r12, r12, #64
1: ldmia r1!, { r4-r11 }
- PLD (r12, #64)
+ pld [r12, #64]
subs r2, r2, #32
// NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
@@ -563,7 +563,7 @@
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
- PLD (r1, #64)
+ pld [r1, #64]
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #16
@@ -590,7 +590,7 @@
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
- PLD (r1, #64)
+ pld [r1, #64]
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #24
@@ -617,7 +617,7 @@
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
- PLD (r1, #64)
+ pld [r1, #64]
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #8