Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-arm/asm/arch/dma.h b/libc/kernel/arch-arm/asm/arch/dma.h
index cdfe92b..5405469 100644
--- a/libc/kernel/arch-arm/asm/arch/dma.h
+++ b/libc/kernel/arch-arm/asm/arch/dma.h
@@ -64,7 +64,7 @@
#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
-#define OMAP_LOGICAL_DMA_CH_COUNT 32
+#define OMAP_LOGICAL_DMA_CH_COUNT 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
@@ -171,83 +171,83 @@
#define OMAP_DMA_CRYPTO_DES_OUT 56
#define OMAP24XX_DMA_NO_DEVICE 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_XTI_DMA 1
-#define OMAP24XX_DMA_EXT_DMAREQ0 2
-#define OMAP24XX_DMA_EXT_DMAREQ1 3
-#define OMAP24XX_DMA_GPMC 4
+#define OMAP24XX_DMA_XTI_DMA 1
+#define OMAP24XX_DMA_EXT_DMAREQ0 2
+#define OMAP24XX_DMA_EXT_DMAREQ1 3
+#define OMAP24XX_DMA_GPMC 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_GFX 5
-#define OMAP24XX_DMA_DSS 6
-#define OMAP24XX_DMA_VLYNQ_TX 7
-#define OMAP24XX_DMA_CWT 8
+#define OMAP24XX_DMA_GFX 5
+#define OMAP24XX_DMA_DSS 6
+#define OMAP24XX_DMA_VLYNQ_TX 7
+#define OMAP24XX_DMA_CWT 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_AES_TX 9
-#define OMAP24XX_DMA_AES_RX 10
-#define OMAP24XX_DMA_DES_TX 11
-#define OMAP24XX_DMA_DES_RX 12
+#define OMAP24XX_DMA_AES_TX 9
+#define OMAP24XX_DMA_AES_RX 10
+#define OMAP24XX_DMA_DES_TX 11
+#define OMAP24XX_DMA_DES_RX 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_SHA1MD5_RX 13
-#define OMAP24XX_DMA_EXT_DMAREQ2 14
-#define OMAP24XX_DMA_EXT_DMAREQ3 15
-#define OMAP24XX_DMA_EXT_DMAREQ4 16
+#define OMAP24XX_DMA_SHA1MD5_RX 13
+#define OMAP24XX_DMA_EXT_DMAREQ2 14
+#define OMAP24XX_DMA_EXT_DMAREQ3 15
+#define OMAP24XX_DMA_EXT_DMAREQ4 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_EAC_AC_RD 17
-#define OMAP24XX_DMA_EAC_AC_WR 18
-#define OMAP24XX_DMA_EAC_MD_UL_RD 19
-#define OMAP24XX_DMA_EAC_MD_UL_WR 20
+#define OMAP24XX_DMA_EAC_AC_RD 17
+#define OMAP24XX_DMA_EAC_AC_WR 18
+#define OMAP24XX_DMA_EAC_MD_UL_RD 19
+#define OMAP24XX_DMA_EAC_MD_UL_WR 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_EAC_MD_DL_RD 21
-#define OMAP24XX_DMA_EAC_MD_DL_WR 22
-#define OMAP24XX_DMA_EAC_BT_UL_RD 23
-#define OMAP24XX_DMA_EAC_BT_UL_WR 24
+#define OMAP24XX_DMA_EAC_MD_DL_RD 21
+#define OMAP24XX_DMA_EAC_MD_DL_WR 22
+#define OMAP24XX_DMA_EAC_BT_UL_RD 23
+#define OMAP24XX_DMA_EAC_BT_UL_WR 24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_EAC_BT_DL_RD 25
-#define OMAP24XX_DMA_EAC_BT_DL_WR 26
-#define OMAP24XX_DMA_I2C1_TX 27
-#define OMAP24XX_DMA_I2C1_RX 28
+#define OMAP24XX_DMA_EAC_BT_DL_RD 25
+#define OMAP24XX_DMA_EAC_BT_DL_WR 26
+#define OMAP24XX_DMA_I2C1_TX 27
+#define OMAP24XX_DMA_I2C1_RX 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_I2C2_TX 29
-#define OMAP24XX_DMA_I2C2_RX 30
-#define OMAP24XX_DMA_MCBSP1_TX 31
-#define OMAP24XX_DMA_MCBSP1_RX 32
+#define OMAP24XX_DMA_I2C2_TX 29
+#define OMAP24XX_DMA_I2C2_RX 30
+#define OMAP24XX_DMA_MCBSP1_TX 31
+#define OMAP24XX_DMA_MCBSP1_RX 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_MCBSP2_TX 33
-#define OMAP24XX_DMA_MCBSP2_RX 34
-#define OMAP24XX_DMA_SPI1_TX0 35
-#define OMAP24XX_DMA_SPI1_RX0 36
+#define OMAP24XX_DMA_MCBSP2_TX 33
+#define OMAP24XX_DMA_MCBSP2_RX 34
+#define OMAP24XX_DMA_SPI1_TX0 35
+#define OMAP24XX_DMA_SPI1_RX0 36
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_SPI1_TX1 37
-#define OMAP24XX_DMA_SPI1_RX1 38
-#define OMAP24XX_DMA_SPI1_TX2 39
-#define OMAP24XX_DMA_SPI1_RX2 40
+#define OMAP24XX_DMA_SPI1_TX1 37
+#define OMAP24XX_DMA_SPI1_RX1 38
+#define OMAP24XX_DMA_SPI1_TX2 39
+#define OMAP24XX_DMA_SPI1_RX2 40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_SPI1_TX3 41
-#define OMAP24XX_DMA_SPI1_RX3 42
-#define OMAP24XX_DMA_SPI2_TX0 43
-#define OMAP24XX_DMA_SPI2_RX0 44
+#define OMAP24XX_DMA_SPI1_TX3 41
+#define OMAP24XX_DMA_SPI1_RX3 42
+#define OMAP24XX_DMA_SPI2_TX0 43
+#define OMAP24XX_DMA_SPI2_RX0 44
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_SPI2_TX1 45
-#define OMAP24XX_DMA_SPI2_RX1 46
-#define OMAP24XX_DMA_UART1_TX 49
-#define OMAP24XX_DMA_UART1_RX 50
+#define OMAP24XX_DMA_SPI2_TX1 45
+#define OMAP24XX_DMA_SPI2_RX1 46
+#define OMAP24XX_DMA_UART1_TX 49
+#define OMAP24XX_DMA_UART1_RX 50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_UART2_TX 51
-#define OMAP24XX_DMA_UART2_RX 52
-#define OMAP24XX_DMA_UART3_TX 53
-#define OMAP24XX_DMA_UART3_RX 54
+#define OMAP24XX_DMA_UART2_TX 51
+#define OMAP24XX_DMA_UART2_RX 52
+#define OMAP24XX_DMA_UART3_TX 53
+#define OMAP24XX_DMA_UART3_RX 54
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_USB_W2FC_TX0 55
-#define OMAP24XX_DMA_USB_W2FC_RX0 56
-#define OMAP24XX_DMA_USB_W2FC_TX1 57
-#define OMAP24XX_DMA_USB_W2FC_RX1 58
+#define OMAP24XX_DMA_USB_W2FC_TX0 55
+#define OMAP24XX_DMA_USB_W2FC_RX0 56
+#define OMAP24XX_DMA_USB_W2FC_TX1 57
+#define OMAP24XX_DMA_USB_W2FC_RX1 58
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_USB_W2FC_TX2 59
-#define OMAP24XX_DMA_USB_W2FC_RX2 60
-#define OMAP24XX_DMA_MMC1_TX 61
-#define OMAP24XX_DMA_MMC1_RX 62
+#define OMAP24XX_DMA_USB_W2FC_TX2 59
+#define OMAP24XX_DMA_USB_W2FC_RX2 60
+#define OMAP24XX_DMA_MMC1_TX 61
+#define OMAP24XX_DMA_MMC1_RX 62
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP24XX_DMA_MS 63
-#define OMAP24XX_DMA_EXT_DMAREQ5 64
+#define OMAP24XX_DMA_MS 63
+#define OMAP24XX_DMA_EXT_DMAREQ5 64
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/arch-arm/asm/arch/fpga.h b/libc/kernel/arch-arm/asm/arch/fpga.h
index 64055a4..8439a80 100644
--- a/libc/kernel/arch-arm/asm/arch/fpga.h
+++ b/libc/kernel/arch-arm/asm/arch/fpga.h
@@ -22,19 +22,19 @@
#define fpga_read(reg) __raw_readb(reg)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fpga_write(val, reg) __raw_writeb(val, reg)
-#define H2P2_DBG_FPGA_BASE 0xE8000000
-#define H2P2_DBG_FPGA_SIZE SZ_4K
-#define H2P2_DBG_FPGA_START 0x04000000
+#define H2P2_DBG_FPGA_BASE 0xE8000000
+#define H2P2_DBG_FPGA_SIZE SZ_4K
+#define H2P2_DBG_FPGA_START 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
-#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
-#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
+#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
+#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
+#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
-#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
-#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
-#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
+#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
+#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
+#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
+#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct h2p2_dbg_fpga {
u16 smc91x[8];
@@ -57,16 +57,16 @@
#define H2P2_DBG_FPGA_LED_RED (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
-#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
+#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
-#define OMAP1510_FPGA_BASE 0xE8000000
+#define OMAP1510_FPGA_BASE 0xE8000000
#define OMAP1510_FPGA_SIZE SZ_4K
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_START 0x08000000
+#define OMAP1510_FPGA_START 0x08000000
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
@@ -122,16 +122,16 @@
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
-#define OMAP1510_FPGA_HID_SCLK (1<<0)
-#define OMAP1510_FPGA_HID_MOSI (1<<1)
-#define OMAP1510_FPGA_HID_nSS (1<<2)
+#define OMAP1510_FPGA_HID_SCLK (1<<0)
+#define OMAP1510_FPGA_HID_MOSI (1<<1)
+#define OMAP1510_FPGA_HID_nSS (1<<2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_HID_nHSUS (1<<3)
-#define OMAP1510_FPGA_HID_MISO (1<<4)
-#define OMAP1510_FPGA_HID_ATN (1<<5)
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)
+#define OMAP1510_FPGA_HID_MISO (1<<4)
+#define OMAP1510_FPGA_HID_ATN (1<<5)
#define OMAP1510_FPGA_HID_rsrvd (1<<6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define OMAP1510_FPGA_HID_RESETn (1<<7)
+#define OMAP1510_FPGA_HID_RESETn (1<<7)
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
diff --git a/libc/kernel/arch-arm/asm/arch/hardware.h b/libc/kernel/arch-arm/asm/arch/hardware.h
index d13fb6a..a779d96 100644
--- a/libc/kernel/arch-arm/asm/arch/hardware.h
+++ b/libc/kernel/arch-arm/asm/arch/hardware.h
@@ -66,8 +66,8 @@
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DIS_USB_PVCI_CLK (1 << 5)
-#define USB_MCLK_EN (1 << 4)
+#define DIS_USB_PVCI_CLK (1 << 5)
+#define USB_MCLK_EN (1 << 4)
#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
#define SOFT_UDC_REQ (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/arch-arm/asm/arch/mcbsp.h b/libc/kernel/arch-arm/asm/arch/mcbsp.h
index 2090ef2..5f4e4d4 100644
--- a/libc/kernel/arch-arm/asm/arch/mcbsp.h
+++ b/libc/kernel/arch-arm/asm/arch/mcbsp.h
@@ -39,12 +39,12 @@
#define RRDY 0x0002
#define RFULL 0x0004
#define RSYNC_ERR 0x0008
-#define RINTM(value) ((value)<<4)
+#define RINTM(value) ((value)<<4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ABIS 0x0040
#define DXENA 0x0080
-#define CLKSTP(value) ((value)<<11)
-#define RJUST(value) ((value)<<13)
+#define CLKSTP(value) ((value)<<11)
+#define RJUST(value) ((value)<<13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DLB 0x8000
#define XRST 0x0001
@@ -52,7 +52,7 @@
#define XEMPTY 0x0004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XSYNC_ERR 0x0008
-#define XINTM(value) ((value)<<4)
+#define XINTM(value) ((value)<<4)
#define GRST 0x0040
#define FRST 0x0080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -77,29 +77,29 @@
#define XIOEN 0x2000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IDLE_EN 0x4000
-#define RWDLEN1(value) ((value)<<5)
-#define RFRLEN1(value) ((value)<<8)
-#define XWDLEN1(value) ((value)<<5)
+#define RWDLEN1(value) ((value)<<5)
+#define RFRLEN1(value) ((value)<<8)
+#define XWDLEN1(value) ((value)<<5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define XFRLEN1(value) ((value)<<8)
-#define RDATDLY(value) (value)
+#define XFRLEN1(value) ((value)<<8)
+#define RDATDLY(value) (value)
#define RFIG 0x0004
-#define RCOMPAND(value) ((value)<<3)
+#define RCOMPAND(value) ((value)<<3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define RWDLEN2(value) ((value)<<5)
-#define RFRLEN2(value) ((value)<<8)
+#define RWDLEN2(value) ((value)<<5)
+#define RFRLEN2(value) ((value)<<8)
#define RPHASE 0x8000
-#define XDATDLY(value) (value)
+#define XDATDLY(value) (value)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XFIG 0x0004
-#define XCOMPAND(value) ((value)<<3)
-#define XWDLEN2(value) ((value)<<5)
-#define XFRLEN2(value) ((value)<<8)
+#define XCOMPAND(value) ((value)<<3)
+#define XWDLEN2(value) ((value)<<5)
+#define XFRLEN2(value) ((value)<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XPHASE 0x8000
-#define CLKGDV(value) (value)
-#define FWID(value) ((value)<<8)
-#define FPER(value) (value)
+#define CLKGDV(value) (value)
+#define FWID(value) ((value)<<8)
+#define FPER(value) (value)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FSGM 0x1000
#define CLKSM 0x2000
@@ -107,14 +107,14 @@
#define GSYNC 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RMCM 0x0001
-#define RCBLK(value) ((value)<<2)
-#define RPABLK(value) ((value)<<5)
-#define RPBBLK(value) ((value)<<7)
+#define RCBLK(value) ((value)<<2)
+#define RPABLK(value) ((value)<<5)
+#define RPBBLK(value) ((value)<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define XMCM(value) (value)
-#define XCBLK(value) ((value)<<2)
-#define XPABLK(value) ((value)<<5)
-#define XPBBLK(value) ((value)<<7)
+#define XMCM(value) (value)
+#define XCBLK(value) ((value)<<2)
+#define XPABLK(value) ((value)<<5)
+#define XPBBLK(value) ((value)<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct omap_mcbsp_reg_cfg {
u16 spcr2;
diff --git a/libc/kernel/arch-arm/asm/arch/mux.h b/libc/kernel/arch-arm/asm/arch/mux.h
index 502b2c7..ef0848c 100644
--- a/libc/kernel/arch-arm/asm/arch/mux.h
+++ b/libc/kernel/arch-arm/asm/arch/mux.h
@@ -18,8 +18,8 @@
****************************************************************************/
#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H
-#define PU_PD_SEL_NA 0
-#define PULL_DWN_CTRL_NA 0
+#define PU_PD_SEL_NA 0
+#define PULL_DWN_CTRL_NA 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, .mask_offset = mode_offset, .mask = mode,
#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, .pull_bit = bit, .pull_val = status,