Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-mips/asm/cpu.h b/libc/kernel/arch-mips/asm/cpu.h
index 7b4b2d3..cbd4147 100644
--- a/libc/kernel/arch-mips/asm/cpu.h
+++ b/libc/kernel/arch-mips/asm/cpu.h
@@ -34,9 +34,9 @@
#define PRID_IMP_R2000 0x0100
#define PRID_IMP_AU1_REV1 0x0100
#define PRID_IMP_AU1_REV2 0x0200
-#define PRID_IMP_R3000 0x0200
+#define PRID_IMP_R3000 0x0200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PRID_IMP_R6000 0x0300
+#define PRID_IMP_R6000 0x0300
#define PRID_IMP_R4000 0x0400
#define PRID_IMP_R6000A 0x0600
#define PRID_IMP_R10000 0x0900
@@ -53,7 +53,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX39 0x2200
#define PRID_IMP_R4640 0x2200
-#define PRID_IMP_R4650 0x2200
+#define PRID_IMP_R4650 0x2200
#define PRID_IMP_R5000 0x2300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX49 0x2d00
@@ -61,7 +61,7 @@
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PRID_IMP_NEVADA 0x2800
+#define PRID_IMP_NEVADA 0x2800
#define PRID_IMP_RM9000 0x3400
#define PRID_IMP_LOONGSON1 0x4200
#define PRID_IMP_R5432 0x5400
@@ -108,11 +108,11 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
-#define PRID_REV_VR4181 0x0050
+#define PRID_REV_VR4181 0x0050
#define PRID_REV_VR4121 0x0060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_VR4122 0x0070
-#define PRID_REV_VR4181A 0x0070
+#define PRID_REV_VR4181A 0x0070
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -157,39 +157,39 @@
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
-#define MIPS_CPU_TLB 0x00000001
-#define MIPS_CPU_4KEX 0x00000002
-#define MIPS_CPU_3K_CACHE 0x00000004
+#define MIPS_CPU_TLB 0x00000001
+#define MIPS_CPU_4KEX 0x00000002
+#define MIPS_CPU_3K_CACHE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_CPU_4K_CACHE 0x00000008
-#define MIPS_CPU_TX39_CACHE 0x00000010
-#define MIPS_CPU_FPU 0x00000020
-#define MIPS_CPU_32FPR 0x00000040
+#define MIPS_CPU_4K_CACHE 0x00000008
+#define MIPS_CPU_TX39_CACHE 0x00000010
+#define MIPS_CPU_FPU 0x00000020
+#define MIPS_CPU_32FPR 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_CPU_COUNTER 0x00000080
-#define MIPS_CPU_WATCH 0x00000100
-#define MIPS_CPU_DIVEC 0x00000200
-#define MIPS_CPU_VCE 0x00000400
+#define MIPS_CPU_COUNTER 0x00000080
+#define MIPS_CPU_WATCH 0x00000100
+#define MIPS_CPU_DIVEC 0x00000200
+#define MIPS_CPU_VCE 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_CPU_CACHE_CDEX_P 0x00000800
-#define MIPS_CPU_CACHE_CDEX_S 0x00001000
-#define MIPS_CPU_MCHECK 0x00002000
-#define MIPS_CPU_EJTAG 0x00004000
+#define MIPS_CPU_CACHE_CDEX_P 0x00000800
+#define MIPS_CPU_CACHE_CDEX_S 0x00001000
+#define MIPS_CPU_MCHECK 0x00002000
+#define MIPS_CPU_EJTAG 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_CPU_NOFPUEX 0x00008000
-#define MIPS_CPU_LLSC 0x00010000
-#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000
-#define MIPS_CPU_PREFETCH 0x00040000
+#define MIPS_CPU_NOFPUEX 0x00008000
+#define MIPS_CPU_LLSC 0x00010000
+#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000
+#define MIPS_CPU_PREFETCH 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_CPU_VINT 0x00080000
-#define MIPS_CPU_VEIC 0x00100000
-#define MIPS_CPU_ULRI 0x00200000
-#define MIPS_ASE_MIPS16 0x00000001
+#define MIPS_CPU_VINT 0x00080000
+#define MIPS_CPU_VEIC 0x00100000
+#define MIPS_CPU_ULRI 0x00200000
+#define MIPS_ASE_MIPS16 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_ASE_MDMX 0x00000002
-#define MIPS_ASE_MIPS3D 0x00000004
-#define MIPS_ASE_SMARTMIPS 0x00000008
-#define MIPS_ASE_DSP 0x00000010
+#define MIPS_ASE_MDMX 0x00000002
+#define MIPS_ASE_MIPS3D 0x00000004
+#define MIPS_ASE_SMARTMIPS 0x00000008
+#define MIPS_ASE_DSP 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MIPS_ASE_MIPSMT 0x00000020
+#define MIPS_ASE_MIPSMT 0x00000020
#endif