Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-mips/asm/sn/addrs.h b/libc/kernel/arch-mips/asm/sn/addrs.h
index d243613..543c7d5 100644
--- a/libc/kernel/arch-mips/asm/sn/addrs.h
+++ b/libc/kernel/arch-mips/asm/sn/addrs.h
@@ -68,12 +68,12 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NODE_SWIN_ADDR(nasid, addr) (((addr) >= NODE_SWIN_BASE(nasid, 0)) && ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE) ))
#define UALIAS_BASE HSPEC_BASE
-#define UALIAS_SIZE 0x10000000
+#define UALIAS_SIZE 0x10000000
#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HUB_REGISTER_WIDGET 1
#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
-#define IALIAS_SIZE 0x800000
+#define IALIAS_SIZE 0x800000
#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
@@ -116,7 +116,7 @@
#define KLDIR_ADDR(nasid) TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
#define KLDIR_SIZE 0x0400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KLI_LAUNCH 0
+#define KLI_LAUNCH 0
#define KLI_KLCONFIG 1
#define KLI_NMI 2
#define KLI_GDA 3
diff --git a/libc/kernel/arch-mips/asm/sn/io.h b/libc/kernel/arch-mips/asm/sn/io.h
index 2b8a101..a3c3e17 100644
--- a/libc/kernel/arch-mips/asm/sn/io.h
+++ b/libc/kernel/arch-mips/asm/sn/io.h
@@ -18,23 +18,23 @@
****************************************************************************/
#ifndef _ASM_SN_IO_H
#define _ASM_SN_IO_H
-#define IIO_ITTE_BASE 0x400160
+#define IIO_ITTE_BASE 0x400160
#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ITTE_OFFSET_BITS 5
+#define IIO_ITTE_OFFSET_BITS 5
#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1)
#define IIO_ITTE_OFFSET_SHIFT 0
-#define IIO_ITTE_WIDGET_BITS 4
+#define IIO_ITTE_WIDGET_BITS 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
#define IIO_ITTE_WIDGET_SHIFT 8
-#define IIO_ITTE_IOSP 1
+#define IIO_ITTE_IOSP 1
#define IIO_ITTE_IOSP_MASK 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_IOSP_SHIFT 12
#define HUB_PIO_MAP_TO_MEM 0
#define HUB_PIO_MAP_TO_IO 1
-#define IIO_ITTE_INVALID_WIDGET 3
+#define IIO_ITTE_INVALID_WIDGET 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), (((((addr) >> BWIN_SIZE_BITS) & IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | (io_or_mem << IIO_ITTE_IOSP_SHIFT) | (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
#define IIO_ITTE_DISABLE(nasid, bigwin) IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
diff --git a/libc/kernel/arch-mips/asm/sn/ioc3.h b/libc/kernel/arch-mips/asm/sn/ioc3.h
index 9771304..46ba4dd 100644
--- a/libc/kernel/arch-mips/asm/sn/ioc3.h
+++ b/libc/kernel/arch-mips/asm/sn/ioc3.h
@@ -193,21 +193,21 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
-#define ERXBUF_CRCERR 0x00000001
-#define ERXBUF_FRAMERR 0x00000002
+#define ERXBUF_CRCERR 0x00000001
+#define ERXBUF_FRAMERR 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_CODERR 0x00000004
-#define ERXBUF_INVPREAMB 0x00000008
-#define ERXBUF_LOLEN 0x00007000
-#define ERXBUF_HILEN 0x03ff0000
+#define ERXBUF_CODERR 0x00000004
+#define ERXBUF_INVPREAMB 0x00000008
+#define ERXBUF_LOLEN 0x00007000
+#define ERXBUF_HILEN 0x03ff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_MULTICAST 0x04000000
-#define ERXBUF_BROADCAST 0x08000000
-#define ERXBUF_LONGEVENT 0x10000000
-#define ERXBUF_BADPKT 0x20000000
+#define ERXBUF_MULTICAST 0x04000000
+#define ERXBUF_BROADCAST 0x08000000
+#define ERXBUF_LONGEVENT 0x10000000
+#define ERXBUF_BADPKT 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_GOODPKT 0x40000000
-#define ERXBUF_CARRIER 0x80000000
+#define ERXBUF_GOODPKT 0x40000000
+#define ERXBUF_CARRIER 0x80000000
#define ETXD_DATALEN 104
struct ioc3_etxd {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -218,15 +218,15 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 data[ETXD_DATALEN];
};
-#define ETXD_BYTECNT_MASK 0x000007ff
-#define ETXD_INTWHENDONE 0x00001000
+#define ETXD_BYTECNT_MASK 0x000007ff
+#define ETXD_INTWHENDONE 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_D0V 0x00010000
-#define ETXD_B1V 0x00020000
-#define ETXD_B2V 0x00040000
-#define ETXD_DOCHECKSUM 0x00080000
+#define ETXD_D0V 0x00010000
+#define ETXD_B1V 0x00020000
+#define ETXD_B2V 0x00040000
+#define ETXD_DOCHECKSUM 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_CHKOFF_MASK 0x07f00000
+#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
#define ETXD_D0CNT_MASK 0x0000007f
#define ETXD_B1CNT_MASK 0x0007ff00
@@ -241,22 +241,22 @@
#define IOC3_BYTEBUS_DEV3 0xe0000L
#define IOC3_SIO_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
-#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
-#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
-#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
+#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
+#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
+#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
+#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
-#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
-#define IOC3_SSRAM IOC3_RAM_OFF
-#define IOC3_SSRAM_LEN 0x40000
+#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
+#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
+#define IOC3_SSRAM IOC3_RAM_OFF
+#define IOC3_SSRAM_LEN 0x40000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IOC3_SSRAM_DM 0x0000ffff
-#define IOC3_SSRAM_PM 0x00010000
-#define PCI_SCR_PAR_RESP_EN 0x00000040
-#define PCI_SCR_SERR_EN 0x00000100
+#define IOC3_SSRAM_DM 0x0000ffff
+#define IOC3_SSRAM_PM 0x00010000
+#define PCI_SCR_PAR_RESP_EN 0x00000040
+#define PCI_SCR_SERR_EN 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PCI_SCR_DROP_MODE_EN 0x00008000
+#define PCI_SCR_DROP_MODE_EN 0x00008000
#define PCI_SCR_RX_SERR (0x1 << 16)
#define PCI_SCR_DROP_MODE (0x1 << 17)
#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
@@ -267,158 +267,158 @@
#define PCI_SCR_SIG_SERR (0x1 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI_SCR_PAR_ERR (0x1 << 31)
-#define KM_CSR_K_WRT_PEND 0x00000001
-#define KM_CSR_M_WRT_PEND 0x00000002
-#define KM_CSR_K_LCB 0x00000004
+#define KM_CSR_K_WRT_PEND 0x00000001
+#define KM_CSR_M_WRT_PEND 0x00000002
+#define KM_CSR_K_LCB 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_LCB 0x00000008
-#define KM_CSR_K_DATA 0x00000010
-#define KM_CSR_K_CLK 0x00000020
-#define KM_CSR_K_PULL_DATA 0x00000040
+#define KM_CSR_M_LCB 0x00000008
+#define KM_CSR_K_DATA 0x00000010
+#define KM_CSR_K_CLK 0x00000020
+#define KM_CSR_K_PULL_DATA 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_K_PULL_CLK 0x00000080
-#define KM_CSR_M_DATA 0x00000100
-#define KM_CSR_M_CLK 0x00000200
-#define KM_CSR_M_PULL_DATA 0x00000400
+#define KM_CSR_K_PULL_CLK 0x00000080
+#define KM_CSR_M_DATA 0x00000100
+#define KM_CSR_M_CLK 0x00000200
+#define KM_CSR_M_PULL_DATA 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_PULL_CLK 0x00000800
-#define KM_CSR_EMM_MODE 0x00001000
-#define KM_CSR_SIM_MODE 0x00002000
-#define KM_CSR_K_SM_IDLE 0x00004000
+#define KM_CSR_M_PULL_CLK 0x00000800
+#define KM_CSR_EMM_MODE 0x00001000
+#define KM_CSR_SIM_MODE 0x00002000
+#define KM_CSR_K_SM_IDLE 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_SM_IDLE 0x00008000
-#define KM_CSR_K_TO 0x00010000
-#define KM_CSR_M_TO 0x00020000
-#define KM_CSR_K_TO_EN 0x00040000
+#define KM_CSR_M_SM_IDLE 0x00008000
+#define KM_CSR_K_TO 0x00010000
+#define KM_CSR_M_TO 0x00020000
+#define KM_CSR_K_TO_EN 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_TO_EN 0x00080000
-#define KM_CSR_K_CLAMP_ONE 0x00100000
-#define KM_CSR_M_CLAMP_ONE 0x00200000
-#define KM_CSR_K_CLAMP_THREE 0x00400000
+#define KM_CSR_M_TO_EN 0x00080000
+#define KM_CSR_K_CLAMP_ONE 0x00100000
+#define KM_CSR_M_CLAMP_ONE 0x00200000
+#define KM_CSR_K_CLAMP_THREE 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_CSR_M_CLAMP_THREE 0x00800000
-#define KM_RD_DATA_2 0x000000ff
+#define KM_CSR_M_CLAMP_THREE 0x00800000
+#define KM_RD_DATA_2 0x000000ff
#define KM_RD_DATA_2_SHIFT 0
-#define KM_RD_DATA_1 0x0000ff00
+#define KM_RD_DATA_1 0x0000ff00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_RD_DATA_1_SHIFT 8
-#define KM_RD_DATA_0 0x00ff0000
+#define KM_RD_DATA_0 0x00ff0000
#define KM_RD_DATA_0_SHIFT 16
-#define KM_RD_FRAME_ERR_2 0x01000000
+#define KM_RD_FRAME_ERR_2 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_RD_FRAME_ERR_1 0x02000000
-#define KM_RD_FRAME_ERR_0 0x04000000
-#define KM_RD_KBD_MSE 0x08000000
-#define KM_RD_OFLO 0x10000000
+#define KM_RD_FRAME_ERR_1 0x02000000
+#define KM_RD_FRAME_ERR_0 0x04000000
+#define KM_RD_KBD_MSE 0x08000000
+#define KM_RD_OFLO 0x10000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_RD_VALID_2 0x20000000
-#define KM_RD_VALID_1 0x40000000
-#define KM_RD_VALID_0 0x80000000
+#define KM_RD_VALID_2 0x20000000
+#define KM_RD_VALID_1 0x40000000
+#define KM_RD_VALID_0 0x80000000
#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KM_WD_WRT_DATA 0x000000ff
+#define KM_WD_WRT_DATA 0x000000ff
#define KM_WD_WRT_DATA_SHIFT 0
-#define RXSB_OVERRUN 0x01
-#define RXSB_PAR_ERR 0x02
+#define RXSB_OVERRUN 0x01
+#define RXSB_PAR_ERR 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define RXSB_FRAME_ERR 0x04
-#define RXSB_BREAK 0x08
-#define RXSB_CTS 0x10
-#define RXSB_DCD 0x20
+#define RXSB_FRAME_ERR 0x04
+#define RXSB_BREAK 0x08
+#define RXSB_CTS 0x10
+#define RXSB_DCD 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define RXSB_MODEM_VALID 0x40
-#define RXSB_DATA_VALID 0x80
-#define TXCB_INT_WHEN_DONE 0x20
-#define TXCB_INVALID 0x00
+#define RXSB_MODEM_VALID 0x40
+#define RXSB_DATA_VALID 0x80
+#define TXCB_INT_WHEN_DONE 0x20
+#define TXCB_INVALID 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define TXCB_VALID 0x40
-#define TXCB_MCR 0x80
-#define TXCB_DELAY 0xc0
-#define SBBR_L_SIZE 0x00000001
+#define TXCB_VALID 0x40
+#define TXCB_MCR 0x80
+#define TXCB_DELAY 0xc0
+#define SBBR_L_SIZE 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SBBR_L_BASE 0xfffff000
-#define SSCR_RX_THRESHOLD 0x000001ff
-#define SSCR_TX_TIMER_BUSY 0x00010000
-#define SSCR_HFC_EN 0x00020000
+#define SBBR_L_BASE 0xfffff000
+#define SSCR_RX_THRESHOLD 0x000001ff
+#define SSCR_TX_TIMER_BUSY 0x00010000
+#define SSCR_HFC_EN 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RX_RING_DCD 0x00040000
-#define SSCR_RX_RING_CTS 0x00080000
-#define SSCR_HIGH_SPD 0x00100000
-#define SSCR_DIAG 0x00200000
+#define SSCR_RX_RING_DCD 0x00040000
+#define SSCR_RX_RING_CTS 0x00080000
+#define SSCR_HIGH_SPD 0x00100000
+#define SSCR_DIAG 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RX_DRAIN 0x08000000
-#define SSCR_DMA_EN 0x10000000
-#define SSCR_DMA_PAUSE 0x20000000
-#define SSCR_PAUSE_STATE 0x40000000
+#define SSCR_RX_DRAIN 0x08000000
+#define SSCR_DMA_EN 0x10000000
+#define SSCR_DMA_PAUSE 0x20000000
+#define SSCR_PAUSE_STATE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SSCR_RESET 0x80000000
-#define PROD_CONS_PTR_4K 0x00000ff8
-#define PROD_CONS_PTR_1K 0x000003f8
+#define SSCR_RESET 0x80000000
+#define PROD_CONS_PTR_4K 0x00000ff8
+#define PROD_CONS_PTR_1K 0x000003f8
#define PROD_CONS_PTR_OFF 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SRCIR_ARM 0x80000000
-#define SRPIR_BYTE_CNT 0x07000000
+#define SRCIR_ARM 0x80000000
+#define SRPIR_BYTE_CNT 0x07000000
#define SRPIR_BYTE_CNT_SHIFT 24
-#define STCIR_BYTE_CNT 0x0f000000
+#define STCIR_BYTE_CNT 0x0f000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STCIR_BYTE_CNT_SHIFT 24
-#define SHADOW_DR 0x00000001
-#define SHADOW_OE 0x00000002
-#define SHADOW_PE 0x00000004
+#define SHADOW_DR 0x00000001
+#define SHADOW_OE 0x00000002
+#define SHADOW_PE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_FE 0x00000008
-#define SHADOW_BI 0x00000010
-#define SHADOW_THRE 0x00000020
-#define SHADOW_TEMT 0x00000040
+#define SHADOW_FE 0x00000008
+#define SHADOW_BI 0x00000010
+#define SHADOW_THRE 0x00000020
+#define SHADOW_TEMT 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_RFCE 0x00000080
-#define SHADOW_DCTS 0x00010000
-#define SHADOW_DDCD 0x00080000
-#define SHADOW_CTS 0x00100000
+#define SHADOW_RFCE 0x00000080
+#define SHADOW_DCTS 0x00010000
+#define SHADOW_DDCD 0x00080000
+#define SHADOW_CTS 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_DCD 0x00800000
-#define SHADOW_DTR 0x01000000
-#define SHADOW_RTS 0x02000000
-#define SHADOW_OUT1 0x04000000
+#define SHADOW_DCD 0x00800000
+#define SHADOW_DTR 0x01000000
+#define SHADOW_RTS 0x02000000
+#define SHADOW_OUT1 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SHADOW_OUT2 0x08000000
-#define SHADOW_LOOP 0x10000000
-#define SRTR_CNT 0x00000fff
-#define SRTR_CNT_VAL 0x0fff0000
+#define SHADOW_OUT2 0x08000000
+#define SHADOW_LOOP 0x10000000
+#define SRTR_CNT 0x00000fff
+#define SRTR_CNT_VAL 0x0fff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SRTR_CNT_VAL_SHIFT 16
-#define SRTR_HZ 16000
-#define SIO_IR_SA_TX_MT 0x00000001
-#define SIO_IR_SA_RX_FULL 0x00000002
+#define SRTR_HZ 16000
+#define SIO_IR_SA_TX_MT 0x00000001
+#define SIO_IR_SA_RX_FULL 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SA_RX_HIGH 0x00000004
-#define SIO_IR_SA_RX_TIMER 0x00000008
-#define SIO_IR_SA_DELTA_DCD 0x00000010
-#define SIO_IR_SA_DELTA_CTS 0x00000020
+#define SIO_IR_SA_RX_HIGH 0x00000004
+#define SIO_IR_SA_RX_TIMER 0x00000008
+#define SIO_IR_SA_DELTA_DCD 0x00000010
+#define SIO_IR_SA_DELTA_CTS 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SA_INT 0x00000040
-#define SIO_IR_SA_TX_EXPLICIT 0x00000080
-#define SIO_IR_SA_MEMERR 0x00000100
-#define SIO_IR_SB_TX_MT 0x00000200
+#define SIO_IR_SA_INT 0x00000040
+#define SIO_IR_SA_TX_EXPLICIT 0x00000080
+#define SIO_IR_SA_MEMERR 0x00000100
+#define SIO_IR_SB_TX_MT 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SB_RX_FULL 0x00000400
-#define SIO_IR_SB_RX_HIGH 0x00000800
-#define SIO_IR_SB_RX_TIMER 0x00001000
-#define SIO_IR_SB_DELTA_DCD 0x00002000
+#define SIO_IR_SB_RX_FULL 0x00000400
+#define SIO_IR_SB_RX_HIGH 0x00000800
+#define SIO_IR_SB_RX_TIMER 0x00001000
+#define SIO_IR_SB_DELTA_DCD 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_SB_DELTA_CTS 0x00004000
-#define SIO_IR_SB_INT 0x00008000
-#define SIO_IR_SB_TX_EXPLICIT 0x00010000
-#define SIO_IR_SB_MEMERR 0x00020000
+#define SIO_IR_SB_DELTA_CTS 0x00004000
+#define SIO_IR_SB_INT 0x00008000
+#define SIO_IR_SB_TX_EXPLICIT 0x00010000
+#define SIO_IR_SB_MEMERR 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_PP_INT 0x00040000
-#define SIO_IR_PP_INTA 0x00080000
-#define SIO_IR_PP_INTB 0x00100000
-#define SIO_IR_PP_MEMERR 0x00200000
+#define SIO_IR_PP_INT 0x00040000
+#define SIO_IR_PP_INTA 0x00080000
+#define SIO_IR_PP_INTB 0x00100000
+#define SIO_IR_PP_MEMERR 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_IR_KBD_INT 0x00400000
-#define SIO_IR_RT_INT 0x08000000
-#define SIO_IR_GEN_INT1 0x10000000
+#define SIO_IR_KBD_INT 0x00400000
+#define SIO_IR_RT_INT 0x08000000
+#define SIO_IR_GEN_INT1 0x10000000
#define SIO_IR_GEN_INT_SHIFT 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR)
@@ -427,61 +427,61 @@
#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & PCI_INW(&((mem)->sio_ies_ro)))
-#define SIO_CR_SIO_RESET 0x00000001
-#define SIO_CR_SER_A_BASE 0x000000fe
+#define SIO_CR_SIO_RESET 0x00000001
+#define SIO_CR_SER_A_BASE 0x000000fe
#define SIO_CR_SER_A_BASE_SHIFT 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_CR_SER_B_BASE 0x00007f00
+#define SIO_CR_SER_B_BASE 0x00007f00
#define SIO_CR_SER_B_BASE_SHIFT 8
-#define SIO_SR_CMD_PULSE 0x00078000
+#define SIO_SR_CMD_PULSE 0x00078000
#define SIO_CR_CMD_PULSE_SHIFT 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define SIO_CR_ARB_DIAG 0x00380000
+#define SIO_CR_ARB_DIAG 0x00380000
#define SIO_CR_ARB_DIAG_TXA 0x00000000
#define SIO_CR_ARB_DIAG_RXA 0x00080000
#define SIO_CR_ARB_DIAG_TXB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_CR_ARB_DIAG_RXB 0x00180000
#define SIO_CR_ARB_DIAG_PP 0x00200000
-#define SIO_CR_ARB_DIAG_IDLE 0x00400000
-#define INT_OUT_COUNT 0x0000ffff
+#define SIO_CR_ARB_DIAG_IDLE 0x00400000
+#define INT_OUT_COUNT 0x0000ffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MODE 0x00070000
-#define INT_OUT_MODE_0 0x00000000
-#define INT_OUT_MODE_1 0x00040000
-#define INT_OUT_MODE_1PULSE 0x00050000
+#define INT_OUT_MODE 0x00070000
+#define INT_OUT_MODE_0 0x00000000
+#define INT_OUT_MODE_1 0x00040000
+#define INT_OUT_MODE_1PULSE 0x00050000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MODE_PULSES 0x00060000
-#define INT_OUT_MODE_SQW 0x00070000
-#define INT_OUT_DIAG 0x40000000
-#define INT_OUT_INT_OUT 0x80000000
+#define INT_OUT_MODE_PULSES 0x00060000
+#define INT_OUT_MODE_SQW 0x00070000
+#define INT_OUT_DIAG 0x40000000
+#define INT_OUT_INT_OUT 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_NS_PER_TICK (30 * 260)
-#define INT_OUT_TICKS_PER_PULSE 3
+#define INT_OUT_NS_PER_TICK (30 * 260)
+#define INT_OUT_TICKS_PER_PULSE 3
#define INT_OUT_US_TO_COUNT(x) (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * 100 / INT_OUT_NS_PER_TICK - 1)
#define INT_OUT_COUNT_TO_US(x) (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define INT_OUT_MIN_TICKS 3
-#define INT_OUT_MAX_TICKS INT_OUT_COUNT
-#define GPCR_DIR 0x000000ff
-#define GPCR_DIR_PIN(x) (1<<(x))
+#define INT_OUT_MIN_TICKS 3
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT
+#define GPCR_DIR 0x000000ff
+#define GPCR_DIR_PIN(x) (1<<(x))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_EDGE 0x000f0000
-#define GPCR_EDGE_PIN(x) (1<<((x)+15))
-#define GPCR_INT_OUT_EN 0x00100000
-#define GPCR_MLAN_EN 0x00200000
+#define GPCR_EDGE 0x000f0000
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))
+#define GPCR_INT_OUT_EN 0x00100000
+#define GPCR_MLAN_EN 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_DIR_SERA_XCVR 0x00000080
-#define GPCR_DIR_SERB_XCVR 0x00000040
-#define GPCR_DIR_PHY_RST 0x00000020
-#define GPCR_PHY_RESET 0x20
+#define GPCR_DIR_SERA_XCVR 0x00000080
+#define GPCR_DIR_SERB_XCVR 0x00000040
+#define GPCR_DIR_PHY_RST 0x00000020
+#define GPCR_PHY_RESET 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPCR_UARTB_MODESEL 0x40
-#define GPCR_UARTA_MODESEL 0x80
-#define GPPR_PHY_RESET_PIN 5
-#define GPPR_UARTB_MODESEL_PIN 6
+#define GPCR_UARTB_MODESEL 0x40
+#define GPCR_UARTA_MODESEL 0x80
+#define GPPR_PHY_RESET_PIN 5
+#define GPPR_UARTB_MODESEL_PIN 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define GPPR_UARTA_MODESEL_PIN 7
+#define GPPR_UARTA_MODESEL_PIN 7
#define EMCR_DUPLEX 0x00000001
#define EMCR_PROMISC 0x00000002
#define EMCR_PADEN 0x00000004
@@ -523,10 +523,10 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EISR_TXMEMERR 0x02000000
#define EISR_TXPARERR 0x04000000
-#define ERCSR_THRESH_MASK 0x000001ff
-#define ERCSR_RX_TMR 0x40000000
+#define ERCSR_THRESH_MASK 0x000001ff
+#define ERCSR_RX_TMR 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERCSR_DIAG_OFLO 0x80000000
+#define ERCSR_DIAG_OFLO 0x80000000
#define ERBR_ALIGNMENT 4096
#define ERBR_L_RXRINGBASE_MASK 0xfffff000
#define ERBAR_BARRIER_BIT 0x0100
@@ -581,29 +581,29 @@
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_CRCERR 0x00000001
-#define ERXBUF_FRAMERR 0x00000002
-#define ERXBUF_CODERR 0x00000004
-#define ERXBUF_INVPREAMB 0x00000008
+#define ERXBUF_CRCERR 0x00000001
+#define ERXBUF_FRAMERR 0x00000002
+#define ERXBUF_CODERR 0x00000004
+#define ERXBUF_INVPREAMB 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_LOLEN 0x00007000
-#define ERXBUF_HILEN 0x03ff0000
-#define ERXBUF_MULTICAST 0x04000000
-#define ERXBUF_BROADCAST 0x08000000
+#define ERXBUF_LOLEN 0x00007000
+#define ERXBUF_HILEN 0x03ff0000
+#define ERXBUF_MULTICAST 0x04000000
+#define ERXBUF_BROADCAST 0x08000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ERXBUF_LONGEVENT 0x10000000
-#define ERXBUF_BADPKT 0x20000000
-#define ERXBUF_GOODPKT 0x40000000
-#define ERXBUF_CARRIER 0x80000000
+#define ERXBUF_LONGEVENT 0x10000000
+#define ERXBUF_BADPKT 0x20000000
+#define ERXBUF_GOODPKT 0x40000000
+#define ERXBUF_CARRIER 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_BYTECNT_MASK 0x000007ff
-#define ETXD_INTWHENDONE 0x00001000
-#define ETXD_D0V 0x00010000
-#define ETXD_B1V 0x00020000
+#define ETXD_BYTECNT_MASK 0x000007ff
+#define ETXD_INTWHENDONE 0x00001000
+#define ETXD_D0V 0x00010000
+#define ETXD_B1V 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define ETXD_B2V 0x00040000
-#define ETXD_DOCHECKSUM 0x00080000
-#define ETXD_CHKOFF_MASK 0x07f00000
+#define ETXD_B2V 0x00040000
+#define ETXD_DOCHECKSUM 0x00080000
+#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_D0CNT_MASK 0x0000007f
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/addrs.h b/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
index 5c056ed..8e29419 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
@@ -119,15 +119,15 @@
#define IO6DPROM_SIZE 0x200000
#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
-#define IP27PROM_INT_LAUNCH 10
+#define IP27PROM_INT_LAUNCH 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IP27PROM_INT_NETUART 12
+#define IP27PROM_INT_NETUART 12
#endif
#define IP27PROM_ELSC_SHFT 10
#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
-#define IO6PROM_STACK_SHFT 14
+#define IO6PROM_STACK_SHFT 14
#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -142,11 +142,11 @@
#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
-#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
-#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
-#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
+#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
+#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
+#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KL_I2C_REG MD_UREG0_0
+#define KL_I2C_REG MD_UREG0_0
#ifndef __ASSEMBLY__
#ifdef HUB_ERR_STS_WAR
#define CACHE_ERR_EFRAME 0x480
@@ -156,7 +156,7 @@
#endif
#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CACHE_ERR_SP_PTR (0x1000 - 32)
+#define CACHE_ERR_SP_PTR (0x1000 - 32)
#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/hubio.h b/libc/kernel/arch-mips/asm/sn/sn0/hubio.h
index f593233..eadbea9 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/hubio.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/hubio.h
@@ -18,41 +18,41 @@
****************************************************************************/
#ifndef _ASM_SGI_SN_SN0_HUBIO_H
#define _ASM_SGI_SN_SN0_HUBIO_H
-#define IIO_WIDGET IIO_WID
-#define IIO_WIDGET_STAT IIO_WSTAT
+#define IIO_WIDGET IIO_WID
+#define IIO_WIDGET_STAT IIO_WSTAT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_WIDGET_CTRL IIO_WCR
-#define IIO_WIDGET_TOUT IIO_WRTO
-#define IIO_WIDGET_FLUSH IIO_WTFR
-#define IIO_PROTECT IIO_ILAPR
+#define IIO_WIDGET_CTRL IIO_WCR
+#define IIO_WIDGET_TOUT IIO_WRTO
+#define IIO_WIDGET_FLUSH IIO_WTFR
+#define IIO_PROTECT IIO_ILAPR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_PROTECT_OVRRD IIO_ILAPO
-#define IIO_OUTWIDGET_ACCESS IIO_IOWA
-#define IIO_INWIDGET_ACCESS IIO_IIWA
-#define IIO_INDEV_ERR_MASK IIO_IIDEM
+#define IIO_PROTECT_OVRRD IIO_ILAPO
+#define IIO_OUTWIDGET_ACCESS IIO_IOWA
+#define IIO_INWIDGET_ACCESS IIO_IIWA
+#define IIO_INDEV_ERR_MASK IIO_IIDEM
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_LLP_CSR IIO_ILCSR
-#define IIO_LLP_LOG IIO_ILLR
-#define IIO_XTALKCC_TOUT IIO_IXCC
-#define IIO_XTALKTT_TOUT IIO_IXTT
+#define IIO_LLP_CSR IIO_ILCSR
+#define IIO_LLP_LOG IIO_ILLR
+#define IIO_XTALKCC_TOUT IIO_IXCC
+#define IIO_XTALKTT_TOUT IIO_IXTT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IO_ERR_CLR IIO_IECLR
-#define IIO_BTE_CRB_CNT IIO_IBCN
+#define IIO_IO_ERR_CLR IIO_IECLR
+#define IIO_BTE_CRB_CNT IIO_IBCN
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_LLP_CSR_LLP_STAT_SHFT 12
-#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull
-#define IIO_BTE_STAT_0 IIO_IBLS_0
-#define IIO_BTE_SRC_0 IIO_IBSA_0
+#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull
+#define IIO_BTE_STAT_0 IIO_IBLS_0
+#define IIO_BTE_SRC_0 IIO_IBSA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_BTE_DEST_0 IIO_IBDA_0
-#define IIO_BTE_CTRL_0 IIO_IBCT_0
-#define IIO_BTE_NOTIFY_0 IIO_IBNA_0
-#define IIO_BTE_INT_0 IIO_IBIA_0
+#define IIO_BTE_DEST_0 IIO_IBDA_0
+#define IIO_BTE_CTRL_0 IIO_IBCT_0
+#define IIO_BTE_NOTIFY_0 IIO_IBNA_0
+#define IIO_BTE_INT_0 IIO_IBIA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_BTE_OFF_0 0
-#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0
+#define IIO_BTE_OFF_0 0
+#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0
#define BTEOFF_STAT 0
#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -68,27 +68,27 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_PERF_CNT 0x430008
#define IO_PERF_SETS 32
-#define IIO_WID 0x400000
-#define IIO_WSTAT 0x400008
+#define IIO_WID 0x400000
+#define IIO_WSTAT 0x400008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_WCR 0x400020
-#define IIO_WSTAT_ECRAZY (1ULL << 32)
-#define IIO_WSTAT_TXRETRY (1ULL << 9)
+#define IIO_WCR 0x400020
+#define IIO_WSTAT_ECRAZY (1ULL << 32)
+#define IIO_WSTAT_TXRETRY (1ULL << 9)
#define IIO_WSTAT_TXRETRY_MASK (0x7F)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & IIO_WSTAT_TXRETRY_MASK)
-#define IIO_ILAPR 0x400100
-#define IIO_ILAPO 0x400108
+#define IIO_ILAPR 0x400100
+#define IIO_ILAPO 0x400108
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IOWA 0x400110
-#define IIO_IIWA 0x400118
-#define IIO_IIDEM 0x400120
-#define IIO_ILCSR 0x400128
+#define IIO_IOWA 0x400110
+#define IIO_IIWA 0x400118
+#define IIO_IIDEM 0x400120
+#define IIO_ILCSR 0x400128
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ILLR 0x400130
-#define IIO_IIDSR 0x400138
-#define IIO_IIBUSERR 0x1400208
+#define IIO_ILLR 0x400130
+#define IIO_IIDSR 0x400138
+#define IIO_IIBUSERR 0x1400208
#define IIO_IIDSR_SENT_SHIFT 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IIDSR_SENT_MASK 0x10000000
@@ -99,21 +99,21 @@
#define IIO_IIDSR_NODE_MASK 0x0000ff00
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x0000003f
-#define IIO_IGFX_0 0x400140
+#define IIO_IGFX_0 0x400140
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IGFX_1 0x400148
-#define IIO_IGFX_W_NUM_BITS 4
+#define IIO_IGFX_1 0x400148
+#define IIO_IGFX_W_NUM_BITS 4
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
#define IIO_IGFX_W_NUM_SHIFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IGFX_N_NUM_BITS 9
+#define IIO_IGFX_N_NUM_BITS 9
#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
#define IIO_IGFX_N_NUM_SHIFT 4
-#define IIO_IGFX_P_NUM_BITS 1
+#define IIO_IGFX_P_NUM_BITS 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
#define IIO_IGFX_P_NUM_SHIFT 16
-#define IIO_IGFX_VLD_BITS 1
+#define IIO_IGFX_VLD_BITS 1
#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_VLD_SHIFT 20
@@ -136,7 +136,7 @@
#define IIO_SCRATCH_BIT0_9 0x0000000000001000
#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_NUM_ITTES 7
+#define IIO_NUM_ITTES 7
#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
#define ILCSR_WARM_RESET 0x100
@@ -272,46 +272,46 @@
#define IIO_LLP_SN_MAX 0xffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_NUM_IPRBS (9)
-#define IIO_IOPRB_0 0x400198
-#define IIO_IOPRB_8 0x4001a0
-#define IIO_IOPRB_9 0x4001a8
+#define IIO_IOPRB_0 0x400198
+#define IIO_IOPRB_8 0x4001a0
+#define IIO_IOPRB_9 0x4001a8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IOPRB_A 0x4001b0
-#define IIO_IOPRB_B 0x4001b8
-#define IIO_IOPRB_C 0x4001c0
-#define IIO_IOPRB_D 0x4001c8
+#define IIO_IOPRB_A 0x4001b0
+#define IIO_IOPRB_B 0x4001b8
+#define IIO_IOPRB_C 0x4001c0
+#define IIO_IOPRB_D 0x4001c8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IOPRB_E 0x4001d0
-#define IIO_IOPRB_F 0x4001d8
-#define IIO_IXCC 0x4001e0
+#define IIO_IOPRB_E 0x4001d0
+#define IIO_IOPRB_F 0x4001d8
+#define IIO_IXCC 0x4001e0
#define IIO_IXTCC IIO_IXCC
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IMEM 0x4001e8
-#define IIO_IXTT 0x4001f0
-#define IIO_IECLR 0x4001f8
-#define IIO_IBCN 0x400200
+#define IIO_IMEM 0x4001e8
+#define IIO_IXTT 0x4001f0
+#define IIO_IECLR 0x4001f8
+#define IIO_IBCN 0x400200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IMEM_W0ESD 0x1
-#define IIO_IMEM_B0ESD (1 << 4)
-#define IIO_IMEM_B1ESD (1 << 8)
-#define IIO_IPCA 0x400300
+#define IIO_IMEM_W0ESD 0x1
+#define IIO_IMEM_B0ESD (1 << 4)
+#define IIO_IMEM_B1ESD (1 << 8)
+#define IIO_IPCA 0x400300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_NUM_PRTES 8
-#define IIO_PRTE_0 0x400308
+#define IIO_NUM_PRTES 8
+#define IIO_PRTE_0 0x400308
#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
-#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8))
+#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IPDR 0x400388
-#define IIO_ICDR 0x400390
-#define IIO_IFDR 0x400398
-#define IIO_IIAP 0x4003a0
+#define IIO_IPDR 0x400388
+#define IIO_ICDR 0x400390
+#define IIO_IFDR 0x400398
+#define IIO_IIAP 0x4003a0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IMMR IIO_IIAP
-#define IIO_ICMR 0x4003a8
-#define IIO_ICCR 0x4003b0
-#define IIO_ICTO 0x4003b8
+#define IIO_ICMR 0x4003a8
+#define IIO_ICCR 0x4003b0
+#define IIO_ICTO 0x4003b8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICTP 0x4003c0
+#define IIO_ICTP 0x4003c0
#define IIO_ICMR_PC_VLD_SHFT 36
#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
#define IIO_ICMR_CRB_VLD_SHFT 20
@@ -334,16 +334,16 @@
#define IIO_ICCR_PENDING (0x10000)
#define IIO_ICCR_CMD_MASK (0xFF)
#define IIO_ICCR_CMD_SHFT (7)
-#define IIO_ICCR_CMD_NOP (0x0)
+#define IIO_ICCR_CMD_NOP (0x0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICCR_CMD_WAKE (0x100)
-#define IIO_ICCR_CMD_TIMEOUT (0x200)
-#define IIO_ICCR_CMD_EJECT (0x400)
+#define IIO_ICCR_CMD_WAKE (0x100)
+#define IIO_ICCR_CMD_TIMEOUT (0x200)
+#define IIO_ICCR_CMD_EJECT (0x400)
#define IIO_ICCR_CMD_FLUSH (0x800)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_NUM_CRBS 15
-#define IIO_NUM_NORMAL_CRBS 12
-#define IIO_NUM_PC_CRBS 4
+#define IIO_NUM_CRBS 15
+#define IIO_NUM_NORMAL_CRBS 12
+#define IIO_NUM_PC_CRBS 4
#define IIO_ICRB_OFFSET 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_0 0x400400
@@ -401,17 +401,17 @@
#define ICRBN_A_ERR_MASK 0x3ff
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_ADDR_SHFT 2
-#define IIO_ICRB_ECODE_DERR 0
-#define IIO_ICRB_ECODE_PERR 1
-#define IIO_ICRB_ECODE_WERR 2
+#define IIO_ICRB_ADDR_SHFT 2
+#define IIO_ICRB_ECODE_DERR 0
+#define IIO_ICRB_ECODE_PERR 1
+#define IIO_ICRB_ECODE_WERR 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_ECODE_AERR 3
-#define IIO_ICRB_ECODE_PWERR 4
-#define IIO_ICRB_ECODE_PRERR 5
-#define IIO_ICRB_ECODE_TOUT 6
+#define IIO_ICRB_ECODE_AERR 3
+#define IIO_ICRB_ECODE_PWERR 4
+#define IIO_ICRB_ECODE_PRERR 5
+#define IIO_ICRB_ECODE_TOUT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_ECODE_XTERR 7
+#define IIO_ICRB_ECODE_XTERR 7
#ifndef __ASSEMBLY__
typedef union icrbb_u {
u64 reg_value;
@@ -496,44 +496,44 @@
#define b_initiator icrbb_field_s.initiator
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_XTSIZE_DW 0
-#define IIO_ICRB_XTSIZE_32 1
-#define IIO_ICRB_XTSIZE_128 2
-#define IIO_ICRB_PROC0 0
+#define IIO_ICRB_XTSIZE_DW 0
+#define IIO_ICRB_XTSIZE_32 1
+#define IIO_ICRB_XTSIZE_128 2
+#define IIO_ICRB_PROC0 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_PROC1 1
-#define IIO_ICRB_GB_REQ 2
-#define IIO_ICRB_IO_REQ 3
-#define IIO_ICRB_IMSGT_XTALK 0
+#define IIO_ICRB_PROC1 1
+#define IIO_ICRB_GB_REQ 2
+#define IIO_ICRB_IO_REQ 3
+#define IIO_ICRB_IMSGT_XTALK 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_IMSGT_BTE 1
-#define IIO_ICRB_IMSGT_SN0NET 2
-#define IIO_ICRB_IMSGT_CRB 3
-#define IIO_ICRB_INIT_XTALK 0
+#define IIO_ICRB_IMSGT_BTE 1
+#define IIO_ICRB_IMSGT_SN0NET 2
+#define IIO_ICRB_IMSGT_CRB 3
+#define IIO_ICRB_INIT_XTALK 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_INIT_BTE0 0x1
-#define IIO_ICRB_INIT_SN0NET 0x2
-#define IIO_ICRB_INIT_CRB 0x3
-#define IIO_ICRB_INIT_BTE1 0x5
+#define IIO_ICRB_INIT_BTE0 0x1
+#define IIO_ICRB_INIT_SN0NET 0x2
+#define IIO_ICRB_INIT_CRB 0x3
+#define IIO_ICRB_INIT_BTE1 0x5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_REQ_DWRD 0
-#define IIO_ICRB_REQ_QCLRD 1
-#define IIO_ICRB_REQ_BLKRD 2
-#define IIO_ICRB_REQ_RSHU 6
+#define IIO_ICRB_REQ_DWRD 0
+#define IIO_ICRB_REQ_QCLRD 1
+#define IIO_ICRB_REQ_BLKRD 2
+#define IIO_ICRB_REQ_RSHU 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_REQ_REXU 7
-#define IIO_ICRB_REQ_RDEX 8
-#define IIO_ICRB_REQ_WINC 9
-#define IIO_ICRB_REQ_BWINV 10
+#define IIO_ICRB_REQ_REXU 7
+#define IIO_ICRB_REQ_RDEX 8
+#define IIO_ICRB_REQ_WINC 9
+#define IIO_ICRB_REQ_BWINV 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_REQ_PIORD 11
-#define IIO_ICRB_REQ_PIOWR 12
-#define IIO_ICRB_REQ_PRDM 13
-#define IIO_ICRB_REQ_PWRM 14
+#define IIO_ICRB_REQ_PIORD 11
+#define IIO_ICRB_REQ_PIOWR 12
+#define IIO_ICRB_REQ_PRDM 13
+#define IIO_ICRB_REQ_PWRM 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_ICRB_REQ_PTPWR 15
-#define IIO_ICRB_REQ_WB 16
-#define IIO_ICRB_REQ_DEX 17
+#define IIO_ICRB_REQ_PTPWR 15
+#define IIO_ICRB_REQ_WB 16
+#define IIO_ICRB_REQ_DEX 17
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef union icrbc_s {
@@ -558,8 +558,8 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define c_pripsc icrbc_field_s.pripsc
#define c_bteop icrbc_field_s.bteop
-#define c_bteaddr icrbc_field_s.push_be
-#define c_benable icrbc_field_s.push_be
+#define c_bteaddr icrbc_field_s.push_be
+#define c_benable icrbc_field_s.push_be
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define c_suppl icrbc_field_s.suppl
#define c_barrop icrbc_field_s.barrop
@@ -598,41 +598,41 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} hubii_ifdr_t;
#endif
-#define IIO_IBLS_0 0x410000
-#define IIO_IBSA_0 0x410008
+#define IIO_IBLS_0 0x410000
+#define IIO_IBSA_0 0x410008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IBDA_0 0x410010
-#define IIO_IBCT_0 0x410018
-#define IIO_IBNA_0 0x410020
+#define IIO_IBDA_0 0x410010
+#define IIO_IBCT_0 0x410018
+#define IIO_IBNA_0 0x410020
#define IIO_IBNR_0 IIO_IBNA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IBIA_0 0x410028
-#define IIO_IBLS_1 0x420000
-#define IIO_IBSA_1 0x420008
-#define IIO_IBDA_1 0x420010
+#define IIO_IBIA_0 0x410028
+#define IIO_IBLS_1 0x420000
+#define IIO_IBSA_1 0x420008
+#define IIO_IBDA_1 0x420010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IBCT_1 0x420018
-#define IIO_IBNA_1 0x420020
+#define IIO_IBCT_1 0x420018
+#define IIO_IBNA_1 0x420020
#define IIO_IBNR_1 IIO_IBNA_1
-#define IIO_IBIA_1 0x420028
+#define IIO_IBIA_1 0x420028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_IPCR 0x430000
-#define IIO_IPPR 0x430008
-#define IECLR_BTE1 (1 << 18)
-#define IECLR_BTE0 (1 << 17)
+#define IIO_IPCR 0x430000
+#define IIO_IPPR 0x430008
+#define IECLR_BTE1 (1 << 18)
+#define IECLR_BTE0 (1 << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IECLR_CRAZY (1 << 16)
-#define IECLR_PRB_F (1 << 15)
-#define IECLR_PRB_E (1 << 14)
-#define IECLR_PRB_D (1 << 13)
+#define IECLR_CRAZY (1 << 16)
+#define IECLR_PRB_F (1 << 15)
+#define IECLR_PRB_E (1 << 14)
+#define IECLR_PRB_D (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IECLR_PRB_C (1 << 12)
-#define IECLR_PRB_B (1 << 11)
-#define IECLR_PRB_A (1 << 10)
-#define IECLR_PRB_9 (1 << 9)
+#define IECLR_PRB_C (1 << 12)
+#define IECLR_PRB_B (1 << 11)
+#define IECLR_PRB_A (1 << 10)
+#define IECLR_PRB_9 (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IECLR_PRB_8 (1 << 8)
-#define IECLR_PRB_0 (1 << 0)
+#define IECLR_PRB_8 (1 << 8)
+#define IECLR_PRB_0 (1 << 0)
#ifndef __ASSEMBLY__
typedef union iprte_a {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -692,9 +692,9 @@
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IPRB_MODE_NORMAL (0)
-#define IPRB_MODE_COLLECT_A (1)
-#define IPRB_MODE_SERVICE_A (2)
-#define IPRB_MODE_SERVICE_B (3)
+#define IPRB_MODE_COLLECT_A (1)
+#define IPRB_MODE_SERVICE_A (2)
+#define IPRB_MODE_SERVICE_B (3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
typedef union icrbp_a {
@@ -781,7 +781,7 @@
#define MAX_HUBS_PER_XBOW 2
#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32)
+#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32)
#define HUBII_XBOW_CREDIT 3
#define HUBII_XBOW_REV2_CREDIT 4
#endif
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/hubmd.h b/libc/kernel/arch-mips/asm/sn/sn0/hubmd.h
index 9f0893f..9825009 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/hubmd.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/hubmd.h
@@ -18,106 +18,106 @@
****************************************************************************/
#ifndef _ASM_SN_SN0_HUBMD_H
#define _ASM_SN_SN0_HUBMD_H
-#define CACHE_SLINE_SIZE 128
+#define CACHE_SLINE_SIZE 128
#define MAX_REGIONS 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PAGE_SIZE 4096
-#define MD_PAGE_NUM_SHFT 12
+#define MD_PAGE_SIZE 4096
+#define MD_PAGE_NUM_SHFT 12
#define MD_BASE 0x200000
#define MD_BASE_PERF 0x210000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_BASE_JUNK 0x220000
-#define MD_IO_PROTECT 0x200000
-#define MD_IO_PROT_OVRRD 0x200008
-#define MD_HSPEC_PROTECT 0x200010
+#define MD_IO_PROTECT 0x200000
+#define MD_IO_PROT_OVRRD 0x200008
+#define MD_HSPEC_PROTECT 0x200010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_MEMORY_CONFIG 0x200018
-#define MD_REFRESH_CONTROL 0x200020
-#define MD_FANDOP_CAC_STAT 0x200028
-#define MD_MIG_DIFF_THRESH 0x200030
+#define MD_MEMORY_CONFIG 0x200018
+#define MD_REFRESH_CONTROL 0x200020
+#define MD_FANDOP_CAC_STAT 0x200028
+#define MD_MIG_DIFF_THRESH 0x200030
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_MIG_VALUE_THRESH 0x200038
-#define MD_MIG_CANDIDATE 0x200040
-#define MD_MIG_CANDIDATE_CLR 0x200048
-#define MD_DIR_ERROR 0x200050
+#define MD_MIG_VALUE_THRESH 0x200038
+#define MD_MIG_CANDIDATE 0x200040
+#define MD_MIG_CANDIDATE_CLR 0x200048
+#define MD_DIR_ERROR 0x200050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_DIR_ERROR_CLR 0x200058
-#define MD_PROTOCOL_ERROR 0x200060
-#define MD_PROTOCOL_ERROR_CLR 0x200068
-#define MD_MEM_ERROR 0x200070
+#define MD_DIR_ERROR_CLR 0x200058
+#define MD_PROTOCOL_ERROR 0x200060
+#define MD_PROTOCOL_ERROR_CLR 0x200068
+#define MD_MEM_ERROR 0x200070
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_MEM_ERROR_CLR 0x200078
-#define MD_MISC_ERROR 0x200080
-#define MD_MISC_ERROR_CLR 0x200088
-#define MD_MEM_DIMM_INIT 0x200090
+#define MD_MEM_ERROR_CLR 0x200078
+#define MD_MISC_ERROR 0x200080
+#define MD_MISC_ERROR_CLR 0x200088
+#define MD_MEM_DIMM_INIT 0x200090
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_DIR_DIMM_INIT 0x200098
-#define MD_MOQ_SIZE 0x2000a0
-#define MD_MLAN_CTL 0x2000a8
-#define MD_PERF_SEL 0x210000
+#define MD_DIR_DIMM_INIT 0x200098
+#define MD_MOQ_SIZE 0x2000a0
+#define MD_MLAN_CTL 0x2000a8
+#define MD_PERF_SEL 0x210000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PERF_CNT0 0x210010
-#define MD_PERF_CNT1 0x210018
-#define MD_PERF_CNT2 0x210020
-#define MD_PERF_CNT3 0x210028
+#define MD_PERF_CNT0 0x210010
+#define MD_PERF_CNT1 0x210018
+#define MD_PERF_CNT2 0x210020
+#define MD_PERF_CNT3 0x210028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PERF_CNT4 0x210030
-#define MD_PERF_CNT5 0x210038
-#define MD_UREG0_0 0x220000
-#define MD_UREG0_1 0x220008
+#define MD_PERF_CNT4 0x210030
+#define MD_PERF_CNT5 0x210038
+#define MD_UREG0_0 0x220000
+#define MD_UREG0_1 0x220008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG0_2 0x220010
-#define MD_UREG0_3 0x220018
-#define MD_UREG0_4 0x220020
-#define MD_UREG0_5 0x220028
+#define MD_UREG0_2 0x220010
+#define MD_UREG0_3 0x220018
+#define MD_UREG0_4 0x220020
+#define MD_UREG0_5 0x220028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG0_6 0x220030
-#define MD_UREG0_7 0x220038
-#define MD_SLOTID_USTAT 0x220048
-#define MD_LED0 0x220050
+#define MD_UREG0_6 0x220030
+#define MD_UREG0_7 0x220038
+#define MD_SLOTID_USTAT 0x220048
+#define MD_LED0 0x220050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_LED1 0x220058
-#define MD_UREG1_0 0x220080
-#define MD_UREG1_1 0x220088
-#define MD_UREG1_2 0x220090
+#define MD_LED1 0x220058
+#define MD_UREG1_0 0x220080
+#define MD_UREG1_1 0x220088
+#define MD_UREG1_2 0x220090
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG1_3 0x220098
-#define MD_UREG1_4 0x2200a0
-#define MD_UREG1_5 0x2200a8
-#define MD_UREG1_6 0x2200b0
+#define MD_UREG1_3 0x220098
+#define MD_UREG1_4 0x2200a0
+#define MD_UREG1_5 0x2200a8
+#define MD_UREG1_6 0x2200b0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG1_7 0x2200b8
-#define MD_UREG1_8 0x2200c0
-#define MD_UREG1_9 0x2200c8
-#define MD_UREG1_10 0x2200d0
+#define MD_UREG1_7 0x2200b8
+#define MD_UREG1_8 0x2200c0
+#define MD_UREG1_9 0x2200c8
+#define MD_UREG1_10 0x2200d0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG1_11 0x2200d8
-#define MD_UREG1_12 0x2200e0
-#define MD_UREG1_13 0x2200e8
-#define MD_UREG1_14 0x2200f0
+#define MD_UREG1_11 0x2200d8
+#define MD_UREG1_12 0x2200e0
+#define MD_UREG1_13 0x2200e8
+#define MD_UREG1_14 0x2200f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_UREG1_15 0x2200f8
-#define MD_MEM_BANKS 8
-#define MD_SIZE_EMPTY 0
+#define MD_UREG1_15 0x2200f8
+#define MD_MEM_BANKS 8
+#define MD_SIZE_EMPTY 0
#define MD_SIZE_8MB 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_16MB 2
-#define MD_SIZE_32MB 3
-#define MD_SIZE_64MB 4
-#define MD_SIZE_128MB 5
+#define MD_SIZE_32MB 3
+#define MD_SIZE_64MB 4
+#define MD_SIZE_128MB 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_256MB 6
-#define MD_SIZE_512MB 7
+#define MD_SIZE_512MB 7
#define MD_SIZE_1GB 8
#define MD_SIZE_2GB 9
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_4GB 10
#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
-#define MMC_FPROM_CYC_SHFT 49
+#define MMC_FPROM_CYC_SHFT 49
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49)
-#define MMC_FPROM_WR_SHFT 44
+#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49)
+#define MMC_FPROM_WR_SHFT 44
#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
#define MMC_UCTLR_CYC_SHFT 39
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -191,27 +191,27 @@
#define MLAN_RD_DATA (UINT64_CAST 0x01)
#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSU_CORECLK_TST_SHFT 7
+#define MSU_CORECLK_TST_SHFT 7
#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
-#define MSU_CORECLK_SHFT 6
+#define MSU_CORECLK_SHFT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
#define MSU_CORECLK (UINT64_CAST 1 << 6)
-#define MSU_NETSYNC_SHFT 5
+#define MSU_NETSYNC_SHFT 5
#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_NETSYNC (UINT64_CAST 1 << 5)
-#define MSU_FPROMRDY_SHFT 4
+#define MSU_FPROMRDY_SHFT 4
#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSU_I2CINTR_SHFT 3
+#define MSU_I2CINTR_SHFT 3
#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
#define MSU_I2CINTR (UINT64_CAST 1 << 3)
#define MSU_SLOTID_MASK 0xff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSU_SN0_SLOTID_SHFT 0
+#define MSU_SN0_SLOTID_SHFT 0
#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
#define MSU_SN00_SLOTID_SHFT 7
#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
@@ -239,55 +239,55 @@
#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
#define MD_MIG_CANDIDATE_NODEID_SHFT 20
#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
-#define MD_MIG_CANDIDATE_ADDR_SHFT 14
+#define MD_MIG_CANDIDATE_ADDR_SHFT 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_BANK_SHFT 29
+#define MD_BANK_SHFT 29
#define MD_BANK_MASK (UINT64_CAST 7 << 29)
-#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT)
+#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT)
#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_DIR_SHARED (UINT64_CAST 0x0)
-#define MD_DIR_POISONED (UINT64_CAST 0x1)
-#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2)
-#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3)
+#define MD_DIR_SHARED (UINT64_CAST 0x0)
+#define MD_DIR_POISONED (UINT64_CAST 0x1)
+#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2)
+#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4)
-#define MD_DIR_WAIT (UINT64_CAST 0x5)
-#define MD_DIR_UNOWNED (UINT64_CAST 0x7)
+#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4)
+#define MD_DIR_WAIT (UINT64_CAST 0x5)
+#define MD_DIR_UNOWNED (UINT64_CAST 0x7)
#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PDIR_MASK 0xffffffffffff
-#define MD_PDIR_ECC_SHFT 0
+#define MD_PDIR_MASK 0xffffffffffff
+#define MD_PDIR_ECC_SHFT 0
#define MD_PDIR_ECC_MASK 0x7f
-#define MD_PDIR_PRIO_SHFT 8
+#define MD_PDIR_PRIO_SHFT 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_PRIO_MASK (0xf << 8)
-#define MD_PDIR_AX_SHFT 7
+#define MD_PDIR_AX_SHFT 7
#define MD_PDIR_AX_MASK (1 << 7)
#define MD_PDIR_AX (1 << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PDIR_FINE_SHFT 12
+#define MD_PDIR_FINE_SHFT 12
#define MD_PDIR_FINE_MASK (1 << 12)
#define MD_PDIR_FINE (1 << 12)
-#define MD_PDIR_OCT_SHFT 13
+#define MD_PDIR_OCT_SHFT 13
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_OCT_MASK (7 << 13)
-#define MD_PDIR_STATE_SHFT 13
+#define MD_PDIR_STATE_SHFT 13
#define MD_PDIR_STATE_MASK (7 << 13)
-#define MD_PDIR_ONECNT_SHFT 16
+#define MD_PDIR_ONECNT_SHFT 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_ONECNT_MASK (0x3f << 16)
-#define MD_PDIR_PTR_SHFT 22
+#define MD_PDIR_PTR_SHFT 22
#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
-#define MD_PDIR_VECMSB_SHFT 22
+#define MD_PDIR_VECMSB_SHFT 22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
#define MD_PDIR_VECMSB_BITSHFT 27
#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
-#define MD_PDIR_CWOFF_SHFT 7
+#define MD_PDIR_CWOFF_SHFT 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_CWOFF_MASK (7 << 7)
-#define MD_PDIR_VECLSB_SHFT 10
+#define MD_PDIR_VECLSB_SHFT 10
#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
#define MD_PDIR_VECLSB_BITSHFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -296,29 +296,29 @@
#define MD_PDIR_INIT_HI 0
#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | MD_PROT_RW << MD_PPROT_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_SDIR_MASK 0xffff
-#define MD_SDIR_ECC_SHFT 0
+#define MD_SDIR_MASK 0xffff
+#define MD_SDIR_ECC_SHFT 0
#define MD_SDIR_ECC_MASK 0x1f
-#define MD_SDIR_PRIO_SHFT 6
+#define MD_SDIR_PRIO_SHFT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_PRIO_MASK (1 << 6)
-#define MD_SDIR_AX_SHFT 5
+#define MD_SDIR_AX_SHFT 5
#define MD_SDIR_AX_MASK (1 << 5)
#define MD_SDIR_AX (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_SDIR_STATE_SHFT 7
+#define MD_SDIR_STATE_SHFT 7
#define MD_SDIR_STATE_MASK (7 << 7)
-#define MD_SDIR_PTR_SHFT 10
+#define MD_SDIR_PTR_SHFT 10
#define MD_SDIR_PTR_MASK (0x3f << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_SDIR_CWOFF_SHFT 5
+#define MD_SDIR_CWOFF_SHFT 5
#define MD_SDIR_CWOFF_MASK (7 << 5)
-#define MD_SDIR_VECMSB_SHFT 11
+#define MD_SDIR_VECMSB_SHFT 11
#define MD_SDIR_VECMSB_BITMASK 0x1f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_VECMSB_BITSHFT 7
#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
-#define MD_SDIR_VECLSB_SHFT 5
+#define MD_SDIR_VECLSB_SHFT 5
#define MD_SDIR_VECLSB_BITMASK 0x7ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_VECLSB_BITSHFT 0
@@ -332,23 +332,23 @@
#define MD_PROT_NO (UINT64_CAST 0x0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PROT_BAD (UINT64_CAST 0x5)
-#define MD_PPROT_SHFT 0
+#define MD_PPROT_SHFT 0
#define MD_PPROT_MASK 7
-#define MD_PPROT_MIGMD_SHFT 3
+#define MD_PPROT_MIGMD_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PPROT_MIGMD_MASK (3 << 3)
-#define MD_PPROT_REFCNT_SHFT 5
+#define MD_PPROT_REFCNT_SHFT 5
#define MD_PPROT_REFCNT_WIDTH 0x7ffff
#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_PPROT_IO_SHFT 45
+#define MD_PPROT_IO_SHFT 45
#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
-#define MD_SPROT_SHFT 0
+#define MD_SPROT_SHFT 0
#define MD_SPROT_MASK 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MD_SPROT_MIGMD_SHFT 3
+#define MD_SPROT_MIGMD_SHFT 3
#define MD_SPROT_MIGMD_MASK (3 << 3)
-#define MD_SPROT_REFCNT_SHFT 5
+#define MD_SPROT_REFCNT_SHFT 5
#define MD_SPROT_REFCNT_WIDTH 0x7ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/hubni.h b/libc/kernel/arch-mips/asm/sn/sn0/hubni.h
index cb3658d..8d330f1 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/hubni.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/hubni.h
@@ -24,47 +24,47 @@
#endif
#define NI_BASE 0x600000
#define NI_BASE_TABLES 0x630000
-#define NI_STATUS_REV_ID 0x600000
+#define NI_STATUS_REV_ID 0x600000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_PORT_RESET 0x600008
-#define NI_PROTECTION 0x600010
-#define NI_GLOBAL_PARMS 0x600018
-#define NI_SCRATCH_REG0 0x600100
+#define NI_PORT_RESET 0x600008
+#define NI_PROTECTION 0x600010
+#define NI_GLOBAL_PARMS 0x600018
+#define NI_SCRATCH_REG0 0x600100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_SCRATCH_REG1 0x600108
-#define NI_DIAG_PARMS 0x600110
-#define NI_VECTOR_PARMS 0x600200
-#define NI_VECTOR 0x600208
+#define NI_SCRATCH_REG1 0x600108
+#define NI_DIAG_PARMS 0x600110
+#define NI_VECTOR_PARMS 0x600200
+#define NI_VECTOR 0x600208
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_VECTOR_DATA 0x600210
-#define NI_VECTOR_STATUS 0x600300
-#define NI_RETURN_VECTOR 0x600308
-#define NI_VECTOR_READ_DATA 0x600310
+#define NI_VECTOR_DATA 0x600210
+#define NI_VECTOR_STATUS 0x600300
+#define NI_RETURN_VECTOR 0x600308
+#define NI_VECTOR_READ_DATA 0x600310
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_VECTOR_CLEAR 0x600380
-#define NI_IO_PROTECT 0x600400
-#define NI_IO_PROT_OVRRD 0x600408
-#define NI_AGE_CPU0_MEMORY 0x600500
+#define NI_VECTOR_CLEAR 0x600380
+#define NI_IO_PROTECT 0x600400
+#define NI_IO_PROT_OVRRD 0x600408
+#define NI_AGE_CPU0_MEMORY 0x600500
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_AGE_CPU0_PIO 0x600508
-#define NI_AGE_CPU1_MEMORY 0x600510
-#define NI_AGE_CPU1_PIO 0x600518
-#define NI_AGE_GBR_MEMORY 0x600520
+#define NI_AGE_CPU0_PIO 0x600508
+#define NI_AGE_CPU1_MEMORY 0x600510
+#define NI_AGE_CPU1_PIO 0x600518
+#define NI_AGE_GBR_MEMORY 0x600520
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_AGE_GBR_PIO 0x600528
-#define NI_AGE_IO_MEMORY 0x600530
-#define NI_AGE_IO_PIO 0x600538
+#define NI_AGE_GBR_PIO 0x600528
+#define NI_AGE_IO_MEMORY 0x600530
+#define NI_AGE_IO_PIO 0x600538
#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_AGE_REG_MAX NI_AGE_IO_PIO
-#define NI_PORT_PARMS 0x608000
-#define NI_PORT_ERROR 0x608008
-#define NI_PORT_ERROR_CLEAR 0x608088
+#define NI_PORT_PARMS 0x608000
+#define NI_PORT_ERROR 0x608008
+#define NI_PORT_ERROR_CLEAR 0x608088
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NI_META_TABLE0 0x638000
+#define NI_META_TABLE0 0x638000
#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
#define NI_META_ENTRIES 32
-#define NI_LOCAL_TABLE0 0x638100
+#define NI_LOCAL_TABLE0 0x638100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
#define NI_LOCAL_ENTRIES 16
@@ -73,55 +73,55 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_LINKUP_SHFT 29
#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
-#define NSRI_DOWNREASON_SHFT 28
-#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28)
+#define NSRI_DOWNREASON_SHFT 28
+#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_MORENODES_SHFT 18
-#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18)
+#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18)
#define MORE_MEMORY 0
#define MORE_NODES 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_REGIONSIZE_SHFT 17
-#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17)
+#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17)
#define REGIONSIZE_FINE 1
#define REGIONSIZE_COARSE 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_NODEID_SHFT 8
-#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)
+#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)
#define NSRI_REV_SHFT 4
-#define NSRI_REV_MASK (UINT64_CAST 0xf << 4)
+#define NSRI_REV_MASK (UINT64_CAST 0xf << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_CHIPID_SHFT 0
-#define NSRI_CHIPID_MASK (UINT64_CAST 0xf)
+#define NSRI_CHIPID_MASK (UINT64_CAST 0xf)
#define NASID_TO_FINEREG_SHFT 0
#define NASID_TO_COARSEREG_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NPR_PORTRESET (UINT64_CAST 1 << 7)
-#define NPR_LINKRESET (UINT64_CAST 1 << 1)
-#define NPR_LOCALRESET (UINT64_CAST 1)
+#define NPR_PORTRESET (UINT64_CAST 1 << 7)
+#define NPR_LINKRESET (UINT64_CAST 1 << 1)
+#define NPR_LOCALRESET (UINT64_CAST 1)
#define NPROT_RESETOK (UINT64_CAST 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NGP_MAXRETRY_SHFT 48
+#define NGP_MAXRETRY_SHFT 48
#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
-#define NGP_TAILTOWRAP_SHFT 32
+#define NGP_TAILTOWRAP_SHFT 32
#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NGP_CREDITTOVAL_SHFT 16
+#define NGP_CREDITTOVAL_SHFT 16
#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
-#define NGP_TAILTOVAL_SHFT 4
+#define NGP_TAILTOVAL_SHFT 4
#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NDP_PORTTORESET (UINT64_CAST 1 << 18)
-#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12)
-#define NDP_PORTDISABLE (UINT64_CAST 1 << 6)
-#define NDP_SENDERROR (UINT64_CAST 1)
+#define NDP_PORTTORESET (UINT64_CAST 1 << 18)
+#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12)
+#define NDP_PORTDISABLE (UINT64_CAST 1 << 6)
+#define NDP_SENDERROR (UINT64_CAST 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NVP_PIOID_SHFT 40
#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVP_WRITEID_SHFT 32
#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8)
+#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8)
#define NVP_TYPE_SHFT 0
#define NVP_TYPE_MASK (UINT64_CAST 0x3)
#define NVS_VALID (UINT64_CAST 1 << 63)
@@ -134,21 +134,21 @@
#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVS_WRITEID_SHFT 32
#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
-#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8)
+#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NVS_TYPE_SHFT 0
#define NVS_TYPE_MASK (UINT64_CAST 0x7)
-#define NVS_ERROR_MASK (UINT64_CAST 0x4)
-#define PIOTYPE_READ 0
+#define NVS_ERROR_MASK (UINT64_CAST 0x4)
+#define PIOTYPE_READ 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PIOTYPE_WRITE 1
-#define PIOTYPE_UNDEFINED 2
-#define PIOTYPE_EXCHANGE 3
-#define PIOTYPE_ADDR_ERR 4
+#define PIOTYPE_WRITE 1
+#define PIOTYPE_UNDEFINED 2
+#define PIOTYPE_EXCHANGE 3
+#define PIOTYPE_ADDR_ERR 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PIOTYPE_CMD_ERR 5
-#define PIOTYPE_PROT_ERR 6
-#define PIOTYPE_UNKNOWN 7
+#define PIOTYPE_CMD_ERR 5
+#define PIOTYPE_PROT_ERR 6
+#define PIOTYPE_UNKNOWN 7
#define NAGE_VCH_SHFT 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/hubpi.h b/libc/kernel/arch-mips/asm/sn/sn0/hubpi.h
index 922c480..7efab8b 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/hubpi.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/hubpi.h
@@ -21,15 +21,15 @@
#include <linux/types.h>
#define PI_BASE 0x000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_CPU_PROTECT 0x000000
-#define PI_PROT_OVERRD 0x000008
-#define PI_IO_PROTECT 0x000010
-#define PI_REGION_PRESENT 0x000018
+#define PI_CPU_PROTECT 0x000000
+#define PI_PROT_OVERRD 0x000008
+#define PI_IO_PROTECT 0x000010
+#define PI_REGION_PRESENT 0x000018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_CPU_NUM 0x000020
-#define PI_CALIAS_SIZE 0x000028
-#define PI_MAX_CRB_TIMEOUT 0x000030
-#define PI_CRB_SFACTOR 0x000038
+#define PI_CPU_NUM 0x000020
+#define PI_CALIAS_SIZE 0x000028
+#define PI_MAX_CRB_TIMEOUT 0x000030
+#define PI_CRB_SFACTOR 0x000038
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CALIAS_SIZE_0 0
#define PI_CALIAS_SIZE_4K 1
@@ -51,143 +51,143 @@
#define PI_CALIAS_SIZE_32M 14
#define PI_CALIAS_SIZE_64M 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_CPU_PRESENT_A 0x000040
-#define PI_CPU_PRESENT_B 0x000048
-#define PI_CPU_ENABLE_A 0x000050
-#define PI_CPU_ENABLE_B 0x000058
+#define PI_CPU_PRESENT_A 0x000040
+#define PI_CPU_PRESENT_B 0x000048
+#define PI_CPU_ENABLE_A 0x000050
+#define PI_CPU_ENABLE_B 0x000058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_REPLY_LEVEL 0x000060
-#define PI_HARDRESET_BIT 0x020068
-#define PI_NMI_A 0x000070
-#define PI_NMI_B 0x000078
+#define PI_REPLY_LEVEL 0x000060
+#define PI_HARDRESET_BIT 0x020068
+#define PI_NMI_A 0x000070
+#define PI_NMI_B 0x000078
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
-#define PI_SOFTRESET 0x000080
-#define PI_INT_PEND_MOD 0x000090
-#define PI_INT_PEND0 0x000098
+#define PI_SOFTRESET 0x000080
+#define PI_INT_PEND_MOD 0x000090
+#define PI_INT_PEND0 0x000098
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_INT_PEND1 0x0000a0
-#define PI_INT_MASK0_A 0x0000a8
-#define PI_INT_MASK1_A 0x0000b0
-#define PI_INT_MASK0_B 0x0000b8
+#define PI_INT_PEND1 0x0000a0
+#define PI_INT_MASK0_A 0x0000a8
+#define PI_INT_MASK1_A 0x0000b0
+#define PI_INT_MASK0_B 0x0000b8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_INT_MASK1_B 0x0000c0
-#define PI_INT_MASK_OFFSET 0x10
-#define PI_CC_PEND_SET_A 0x0000c8
-#define PI_CC_PEND_SET_B 0x0000d0
+#define PI_INT_MASK1_B 0x0000c0
+#define PI_INT_MASK_OFFSET 0x10
+#define PI_CC_PEND_SET_A 0x0000c8
+#define PI_CC_PEND_SET_B 0x0000d0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_CC_PEND_CLR_A 0x0000d8
-#define PI_CC_PEND_CLR_B 0x0000e0
-#define PI_CC_MASK 0x0000e8
-#define PI_INT_SET_OFFSET 0x08
+#define PI_CC_PEND_CLR_A 0x0000d8
+#define PI_CC_PEND_CLR_B 0x0000e0
+#define PI_CC_MASK 0x0000e8
+#define PI_INT_SET_OFFSET 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_RT_COUNT 0x030100
-#define PI_RT_COMPARE_A 0x000108
-#define PI_RT_COMPARE_B 0x000110
-#define PI_PROFILE_COMPARE 0x000118
+#define PI_RT_COUNT 0x030100
+#define PI_RT_COMPARE_A 0x000108
+#define PI_RT_COMPARE_B 0x000110
+#define PI_PROFILE_COMPARE 0x000118
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_RT_PEND_A 0x000120
-#define PI_RT_PEND_B 0x000128
-#define PI_PROF_PEND_A 0x000130
-#define PI_PROF_PEND_B 0x000138
+#define PI_RT_PEND_A 0x000120
+#define PI_RT_PEND_B 0x000128
+#define PI_PROF_PEND_A 0x000130
+#define PI_PROF_PEND_B 0x000138
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_RT_EN_A 0x000140
-#define PI_RT_EN_B 0x000148
-#define PI_PROF_EN_A 0x000150
-#define PI_PROF_EN_B 0x000158
+#define PI_RT_EN_A 0x000140
+#define PI_RT_EN_B 0x000148
+#define PI_PROF_EN_A 0x000150
+#define PI_PROF_EN_B 0x000158
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_RT_LOCAL_CTRL 0x000160
-#define PI_RT_FILTER_CTRL 0x000168
-#define PI_COUNT_OFFSET 0x08
-#define PI_BIST_WRITE_DATA 0x000200
+#define PI_RT_LOCAL_CTRL 0x000160
+#define PI_RT_FILTER_CTRL 0x000168
+#define PI_COUNT_OFFSET 0x08
+#define PI_BIST_WRITE_DATA 0x000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_BIST_READ_DATA 0x000208
-#define PI_BIST_COUNT_TARG 0x000210
-#define PI_BIST_READY 0x000218
-#define PI_BIST_SHIFT_LOAD 0x000220
+#define PI_BIST_READ_DATA 0x000208
+#define PI_BIST_COUNT_TARG 0x000210
+#define PI_BIST_READY 0x000218
+#define PI_BIST_SHIFT_LOAD 0x000220
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_BIST_SHIFT_UNLOAD 0x000228
-#define PI_BIST_ENTER_RUN 0x000230
-#define PI_GFX_PAGE_A 0x000300
-#define PI_GFX_CREDIT_CNTR_A 0x000308
+#define PI_BIST_SHIFT_UNLOAD 0x000228
+#define PI_BIST_ENTER_RUN 0x000230
+#define PI_GFX_PAGE_A 0x000300
+#define PI_GFX_CREDIT_CNTR_A 0x000308
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_GFX_BIAS_A 0x000310
-#define PI_GFX_INT_CNTR_A 0x000318
-#define PI_GFX_INT_CMP_A 0x000320
-#define PI_GFX_PAGE_B 0x000328
+#define PI_GFX_BIAS_A 0x000310
+#define PI_GFX_INT_CNTR_A 0x000318
+#define PI_GFX_INT_CMP_A 0x000320
+#define PI_GFX_PAGE_B 0x000328
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_GFX_CREDIT_CNTR_B 0x000330
-#define PI_GFX_BIAS_B 0x000338
-#define PI_GFX_INT_CNTR_B 0x000340
-#define PI_GFX_INT_CMP_B 0x000348
+#define PI_GFX_CREDIT_CNTR_B 0x000330
+#define PI_GFX_BIAS_B 0x000338
+#define PI_GFX_INT_CNTR_B 0x000340
+#define PI_GFX_INT_CMP_B 0x000348
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
-#define PI_ERR_INT_PEND 0x000400
-#define PI_ERR_INT_MASK_A 0x000408
+#define PI_ERR_INT_PEND 0x000400
+#define PI_ERR_INT_MASK_A 0x000408
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_ERR_INT_MASK_B 0x000410
-#define PI_ERR_STACK_ADDR_A 0x000418
-#define PI_ERR_STACK_ADDR_B 0x000420
-#define PI_ERR_STACK_SIZE 0x000428
+#define PI_ERR_INT_MASK_B 0x000410
+#define PI_ERR_STACK_ADDR_A 0x000418
+#define PI_ERR_STACK_ADDR_B 0x000420
+#define PI_ERR_STACK_SIZE 0x000428
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_ERR_STATUS0_A 0x000430
-#define PI_ERR_STATUS0_A_RCLR 0x000438
-#define PI_ERR_STATUS1_A 0x000440
-#define PI_ERR_STATUS1_A_RCLR 0x000448
+#define PI_ERR_STATUS0_A 0x000430
+#define PI_ERR_STATUS0_A_RCLR 0x000438
+#define PI_ERR_STATUS1_A 0x000440
+#define PI_ERR_STATUS1_A_RCLR 0x000448
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_ERR_STATUS0_B 0x000450
-#define PI_ERR_STATUS0_B_RCLR 0x000458
-#define PI_ERR_STATUS1_B 0x000460
-#define PI_ERR_STATUS1_B_RCLR 0x000468
+#define PI_ERR_STATUS0_B 0x000450
+#define PI_ERR_STATUS0_B_RCLR 0x000458
+#define PI_ERR_STATUS1_B 0x000460
+#define PI_ERR_STATUS1_B_RCLR 0x000468
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_SPOOL_CMP_A 0x000470
-#define PI_SPOOL_CMP_B 0x000478
-#define PI_CRB_TIMEOUT_A 0x000480
-#define PI_CRB_TIMEOUT_B 0x000488
+#define PI_SPOOL_CMP_A 0x000470
+#define PI_SPOOL_CMP_B 0x000478
+#define PI_CRB_TIMEOUT_A 0x000480
+#define PI_CRB_TIMEOUT_B 0x000488
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_SYSAD_ERRCHK_EN 0x000490
-#define PI_BAD_CHECK_BIT_A 0x000498
-#define PI_BAD_CHECK_BIT_B 0x0004a0
-#define PI_NACK_CNT_A 0x0004a8
+#define PI_SYSAD_ERRCHK_EN 0x000490
+#define PI_BAD_CHECK_BIT_A 0x000498
+#define PI_BAD_CHECK_BIT_B 0x0004a0
+#define PI_NACK_CNT_A 0x0004a8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_NACK_CNT_B 0x0004b0
-#define PI_NACK_CMP 0x0004b8
+#define PI_NACK_CNT_B 0x0004b0
+#define PI_NACK_CMP 0x0004b8
#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
-#define PI_ERR_SPOOL_CMP_B 0x00000001
+#define PI_ERR_SPOOL_CMP_B 0x00000001
#define PI_ERR_SPOOL_CMP_A 0x00000002
-#define PI_ERR_SPUR_MSG_B 0x00000004
+#define PI_ERR_SPUR_MSG_B 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SPUR_MSG_A 0x00000008
-#define PI_ERR_WRB_TERR_B 0x00000010
+#define PI_ERR_WRB_TERR_B 0x00000010
#define PI_ERR_WRB_TERR_A 0x00000020
-#define PI_ERR_WRB_WERR_B 0x00000040
+#define PI_ERR_WRB_WERR_B 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_WRB_WERR_A 0x00000080
-#define PI_ERR_SYSSTATE_B 0x00000100
+#define PI_ERR_SYSSTATE_B 0x00000100
#define PI_ERR_SYSSTATE_A 0x00000200
-#define PI_ERR_SYSAD_DATA_B 0x00000400
+#define PI_ERR_SYSAD_DATA_B 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSAD_DATA_A 0x00000800
-#define PI_ERR_SYSAD_ADDR_B 0x00001000
+#define PI_ERR_SYSAD_ADDR_B 0x00001000
#define PI_ERR_SYSAD_ADDR_A 0x00002000
-#define PI_ERR_SYSCMD_DATA_B 0x00004000
+#define PI_ERR_SYSCMD_DATA_B 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSCMD_DATA_A 0x00008000
-#define PI_ERR_SYSCMD_ADDR_B 0x00010000
+#define PI_ERR_SYSCMD_ADDR_B 0x00010000
#define PI_ERR_SYSCMD_ADDR_A 0x00020000
-#define PI_ERR_BAD_SPOOL_B 0x00040000
+#define PI_ERR_BAD_SPOOL_B 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_BAD_SPOOL_A 0x00080000
-#define PI_ERR_UNCAC_UNCORR_B 0x00100000
+#define PI_ERR_UNCAC_UNCORR_B 0x00100000
#define PI_ERR_UNCAC_UNCORR_A 0x00200000
-#define PI_ERR_SYSSTATE_TAG_B 0x00400000
+#define PI_ERR_SYSSTATE_TAG_B 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSSTATE_TAG_A 0x00800000
-#define PI_ERR_MD_UNCORR 0x01000000
+#define PI_ERR_MD_UNCORR 0x01000000
#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa
#define PI_ERR_CLEAR_ALL_B 0x00555555
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -266,8 +266,8 @@
#define ERR_STK_ADDR_SHFT 7
#define ERR_STAT0_ADDR_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_MIN_STACK_SIZE 4096
-#define PI_STACK_SIZE_SHFT 12
+#define PI_MIN_STACK_SIZE 4096
+#define PI_STACK_SIZE_SHFT 12
#define ERR_STACK_SIZE_BYTES(_sz) ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -323,15 +323,15 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef u64 rtc_time_t;
#endif
-#define PI_SYSAD_ERRCHK_ECCGEN 0x01
-#define PI_SYSAD_ERRCHK_QUALGEN 0x02
+#define PI_SYSAD_ERRCHK_ECCGEN 0x01
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_SYSAD_ERRCHK_SADP 0x04
-#define PI_SYSAD_ERRCHK_CMDP 0x08
-#define PI_SYSAD_ERRCHK_STATE 0x10
-#define PI_SYSAD_ERRCHK_QUAL 0x20
+#define PI_SYSAD_ERRCHK_SADP 0x04
+#define PI_SYSAD_ERRCHK_CMDP 0x08
+#define PI_SYSAD_ERRCHK_STATE 0x10
+#define PI_SYSAD_ERRCHK_QUAL 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PI_SYSAD_CHECK_ALL 0x3f
+#define PI_SYSAD_CHECK_ALL 0x3f
#define HUB_IP_PEND0 0x0400
#define HUB_IP_PEND1_CC 0x0800
#define HUB_IP_RT 0x1000