Switch kernel header parsing to python libclang
Replace the tokenizer in cpp.py with libclang.
Bug: 18937958
Change-Id: I27630904c6d2849418cd5ca3d3c612ec3078686d
diff --git a/libc/kernel/uapi/asm-x86/asm/msr-index.h b/libc/kernel/uapi/asm-x86/asm/msr-index.h
index 9326f42..221cec2 100644
--- a/libc/kernel/uapi/asm-x86/asm/msr-index.h
+++ b/libc/kernel/uapi/asm-x86/asm/msr-index.h
@@ -38,15 +38,15 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _EFER_LMSLE 13
#define _EFER_FFXSR 14
-#define EFER_SCE (1<<_EFER_SCE)
-#define EFER_LME (1<<_EFER_LME)
+#define EFER_SCE (1 << _EFER_SCE)
+#define EFER_LME (1 << _EFER_LME)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define EFER_LMA (1<<_EFER_LMA)
-#define EFER_NX (1<<_EFER_NX)
-#define EFER_SVME (1<<_EFER_SVME)
-#define EFER_LMSLE (1<<_EFER_LMSLE)
+#define EFER_LMA (1 << _EFER_LMA)
+#define EFER_NX (1 << _EFER_NX)
+#define EFER_SVME (1 << _EFER_SVME)
+#define EFER_LMSLE (1 << _EFER_LMSLE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define EFER_FFXSR (1<<_EFER_FFXSR)
+#define EFER_FFXSR (1 << _EFER_FFXSR)
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
@@ -166,10 +166,10 @@
#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
#define MSR_AMD64_MC0_MASK 0xc0010044
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
-#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
-#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
-#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
+#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4 * (x))
+#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4 * (x))
+#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4 * (x))
+#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4 * (x))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
#define MSR_IA32_MC0_CTL2 0x00000280
@@ -202,7 +202,7 @@
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_AMD64_IBSFETCH_REG_COUNT 3
-#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
+#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL << MSR_AMD64_IBSFETCH_REG_COUNT) - 1)
#define MSR_AMD64_IBSOPCTL 0xc0011033
#define MSR_AMD64_IBSOPRIP 0xc0011034
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -213,7 +213,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
#define MSR_AMD64_IBSOP_REG_COUNT 7
-#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
+#define MSR_AMD64_IBSOP_REG_MASK ((1UL << MSR_AMD64_IBSOP_REG_COUNT) - 1)
#define MSR_AMD64_IBSCTL 0xc001103a
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_AMD64_IBSBRTARGET 0xc001103b
@@ -227,7 +227,7 @@
#define MSR_F15H_NB_PERF_CTR 0xc0010241
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
-#define FAM10H_MMIO_CONF_ENABLE (1<<0)
+#define FAM10H_MMIO_CONF_ENABLE (1 << 0)
#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -307,14 +307,14 @@
#define MSR_IA32_BNDCFGS 0x00000d90
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_IA32_XSS 0x00000da0
-#define FEATURE_CONTROL_LOCKED (1<<0)
-#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
-#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
+#define FEATURE_CONTROL_LOCKED (1 << 0)
+#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1 << 1)
+#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_IA32_APICBASE 0x0000001b
-#define MSR_IA32_APICBASE_BSP (1<<8)
-#define MSR_IA32_APICBASE_ENABLE (1<<11)
-#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+#define MSR_IA32_APICBASE_BSP (1 << 8)
+#define MSR_IA32_APICBASE_ENABLE (1 << 11)
+#define MSR_IA32_APICBASE_BASE (0xfffff << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_IA32_TSCDEADLINE 0x000006e0
#define MSR_IA32_UCODE_WRITE 0x00000079