tree e944658c6ea3eafc732d7362dae7e8ce49206137
parent 4d421901e587fd1563da94baf59b015017c01b91
author Duane Sand <duane.sand@imgtec.com> 1405377014 -0700
committer Duane Sand <duane.sand@imgtec.com> 1406149050 -0700

[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models

Save and restore floating point registers via 64-bit
load/stores when possible.  Use assembler's builtin macro
ops to generate pairs of 32-bit load/stores on Mips I cpus.

Some cpus or FR modes have only 16 even-numbered dp fp regs.
This is exposed by _MIPS_FPSET, defined by existing compilers.

Change-Id: I7f617a3ffea8da41c402ef3a68ab32c91d3d7622