tree aef71bc86c9dd98b85089ed665a5e44d80220088
parent 79f6667f8c80630c3782ad1c47d965ac20706d2a
author Wilco Dijkstra <wdijkstr@arm.com> 1438257060 +0100
committer Jackeagle <jackeagle102@gmail.com> 1477491882 +0530

libc: ARM64: optimize memset.

 This is an optimized memset for AArch64.  Memset is split into 4 main
 cases: small sets of up to 16 bytes, medium of 16..96 bytes which are
 fully unrolled.  Large memsets of more than 96 bytes align the
 destination and use an unrolled loop processing 64 bytes per
 iteration.  Memsets of zero of more than 256 use the dc zva
 instruction, and there are faster versions for the common ZVA sizes 64
 or 128.  STP of Q registers is used to reduce codesize without loss of
 performance.

Change-Id: I0c5b5ec5ab8a1fd0f23eee8fbacada0be08e841f