commit fe6338da9168330d44b409b2ee36103e8bfe6697
author Henrik Smiding <henrik.smiding@stericsson.com> Wed Sep 15 16:08:03 2010 +0200
committer Christian Bejram <christian.bejram@stericsson.com> Mon May 07 14:18:02 2012 +0200
tree 904bc5df5c840b96996259fb9658b492161117e3
parent f7db5ecc4d662da8368f31d57401ca1a39690e40

Adjust memcpy for ARM Cortex A9 cache line size

ARM Cortex A8 use 64 bytes and ARM Cortex A9 use 32 bytes cache line
size.

The following patch:
  Adds code to adjust memcpy cache line size to match A9 cache line
  size.
  Adds a flag to select between 32 bytes and 64 bytes cache line
  size.

  Copyright (C) ST-Ericsson SA 2010
    Modified neon implementation to fit Cortex A9 cache line size
    Author: Henrik Smiding henrik.smiding@stericsson.com for
            ST-Ericsson.

Change-Id: I8a55946bfb074e6ec0a14805ed65f73fcd0984a3
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>

libc/Android.mk

diff --git a/libc/Android.mk b/libc/Android.mk
index 9881d59..2628507 100644
--- a/libc/Android.mk
+++ b/libc/Android.mk
@@ -471,6 +471,14 @@
   ifeq ($(ARCH_ARM_HAVE_TLS_REGISTER),true)
     libc_common_cflags += -DHAVE_ARM_TLS_REGISTER
   endif
+  #
+  # Define HAVE_32_BYTE_CACHE_LINES to indicate to C
+  # library it should use to 32-byte version of memcpy, and not
+  # the 64-byte version.
+  #
+  ifeq ($(ARCH_ARM_HAVE_32_BYTE_CACHE_LINES),true)
+    libc_common_cflags += -DHAVE_32_BYTE_CACHE_LINE
+  endif
 else # !arm
   ifeq ($(TARGET_ARCH),x86)
     libc_crt_target_cflags :=