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review.blissroms.org / platform_bionic / 7f3d65de8cf2920981d73adee278c0d7bee79170 / . / libc / kernel / uapi / asm-x86 / asm / msr-index.h
blob: a83f3503db84550efa860c1018f72e8e6b72a0ec [file] [log] [blame]
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _ASM_X86_MSR_INDEX_H
20#define _ASM_X86_MSR_INDEX_H
21#define MSR_EFER 0xc0000080
22#define MSR_STAR 0xc0000081
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define MSR_LSTAR 0xc0000082
25#define MSR_CSTAR 0xc0000083
26#define MSR_SYSCALL_MASK 0xc0000084
27#define MSR_FS_BASE 0xc0000100
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define MSR_GS_BASE 0xc0000101
30#define MSR_KERNEL_GS_BASE 0xc0000102
31#define MSR_TSC_AUX 0xc0000103
32#define _EFER_SCE 0
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define _EFER_LME 8
35#define _EFER_LMA 10
36#define _EFER_NX 11
37#define _EFER_SVME 12
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define _EFER_LMSLE 13
40#define _EFER_FFXSR 14
41#define EFER_SCE (1<<_EFER_SCE)
42#define EFER_LME (1<<_EFER_LME)
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define EFER_LMA (1<<_EFER_LMA)
45#define EFER_NX (1<<_EFER_NX)
46#define EFER_SVME (1<<_EFER_SVME)
47#define EFER_LMSLE (1<<_EFER_LMSLE)
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define EFER_FFXSR (1<<_EFER_FFXSR)
50#define MSR_IA32_PERFCTR0 0x000000c1
51#define MSR_IA32_PERFCTR1 0x000000c2
52#define MSR_FSB_FREQ 0x000000cd
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define MSR_NHM_PLATFORM_INFO 0x000000ce
55#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
56#define NHM_C3_AUTO_DEMOTE (1UL << 25)
57#define NHM_C1_AUTO_DEMOTE (1UL << 26)
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
60#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
61#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
62#define MSR_PLATFORM_INFO 0x000000ce
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define MSR_MTRRcap 0x000000fe
65#define MSR_IA32_BBL_CR_CTL 0x00000119
66#define MSR_IA32_BBL_CR_CTL3 0x0000011e
67#define MSR_IA32_SYSENTER_CS 0x00000174
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define MSR_IA32_SYSENTER_ESP 0x00000175
70#define MSR_IA32_SYSENTER_EIP 0x00000176
71#define MSR_IA32_MCG_CAP 0x00000179
72#define MSR_IA32_MCG_STATUS 0x0000017a
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define MSR_IA32_MCG_CTL 0x0000017b
75#define MSR_OFFCORE_RSP_0 0x000001a6
76#define MSR_OFFCORE_RSP_1 0x000001a7
77#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
80#define MSR_LBR_SELECT 0x000001c8
81#define MSR_LBR_TOS 0x000001c9
82#define MSR_LBR_NHM_FROM 0x00000680
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define MSR_LBR_NHM_TO 0x000006c0
85#define MSR_LBR_CORE_FROM 0x00000040
86#define MSR_LBR_CORE_TO 0x00000060
87#define MSR_IA32_PEBS_ENABLE 0x000003f1
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define MSR_IA32_DS_AREA 0x00000600
90#define MSR_IA32_PERF_CAPABILITIES 0x00000345
91#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
92#define MSR_MTRRfix64K_00000 0x00000250
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define MSR_MTRRfix16K_80000 0x00000258
95#define MSR_MTRRfix16K_A0000 0x00000259
96#define MSR_MTRRfix4K_C0000 0x00000268
97#define MSR_MTRRfix4K_C8000 0x00000269
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99#define MSR_MTRRfix4K_D0000 0x0000026a
100#define MSR_MTRRfix4K_D8000 0x0000026b
101#define MSR_MTRRfix4K_E0000 0x0000026c
102#define MSR_MTRRfix4K_E8000 0x0000026d
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104#define MSR_MTRRfix4K_F0000 0x0000026e
105#define MSR_MTRRfix4K_F8000 0x0000026f
106#define MSR_MTRRdefType 0x000002ff
107#define MSR_IA32_CR_PAT 0x00000277
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109#define MSR_IA32_DEBUGCTLMSR 0x000001d9
110#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
111#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
112#define MSR_IA32_LASTINTFROMIP 0x000001dd
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114#define MSR_IA32_LASTINTTOIP 0x000001de
115#define DEBUGCTLMSR_LBR (1UL << 0)
116#define DEBUGCTLMSR_BTF (1UL << 1)
117#define DEBUGCTLMSR_TR (1UL << 6)
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119#define DEBUGCTLMSR_BTS (1UL << 7)
120#define DEBUGCTLMSR_BTINT (1UL << 8)
121#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
122#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
125#define MSR_IA32_POWER_CTL 0x000001fc
126#define MSR_IA32_MC0_CTL 0x00000400
127#define MSR_IA32_MC0_STATUS 0x00000401
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define MSR_IA32_MC0_ADDR 0x00000402
130#define MSR_IA32_MC0_MISC 0x00000403
131#define MSR_PKG_C3_RESIDENCY 0x000003f8
132#define MSR_PKG_C6_RESIDENCY 0x000003f9
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define MSR_PKG_C7_RESIDENCY 0x000003fa
135#define MSR_CORE_C3_RESIDENCY 0x000003fc
136#define MSR_CORE_C6_RESIDENCY 0x000003fd
137#define MSR_CORE_C7_RESIDENCY 0x000003fe
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define MSR_PKG_C2_RESIDENCY 0x0000060d
140#define MSR_PKG_C8_RESIDENCY 0x00000630
141#define MSR_PKG_C9_RESIDENCY 0x00000631
142#define MSR_PKG_C10_RESIDENCY 0x00000632
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define MSR_RAPL_POWER_UNIT 0x00000606
145#define MSR_PKG_POWER_LIMIT 0x00000610
146#define MSR_PKG_ENERGY_STATUS 0x00000611
147#define MSR_PKG_PERF_STATUS 0x00000613
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#define MSR_PKG_POWER_INFO 0x00000614
150#define MSR_DRAM_POWER_LIMIT 0x00000618
151#define MSR_DRAM_ENERGY_STATUS 0x00000619
152#define MSR_DRAM_PERF_STATUS 0x0000061b
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154#define MSR_DRAM_POWER_INFO 0x0000061c
155#define MSR_PP0_POWER_LIMIT 0x00000638
156#define MSR_PP0_ENERGY_STATUS 0x00000639
157#define MSR_PP0_POLICY 0x0000063a
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159#define MSR_PP0_PERF_STATUS 0x0000063b
160#define MSR_PP1_POWER_LIMIT 0x00000640
161#define MSR_PP1_ENERGY_STATUS 0x00000641
162#define MSR_PP1_POLICY 0x00000642
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]164#define MSR_CORE_C1_RES 0x00000660
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]165#define MSR_AMD64_MC0_MASK 0xc0010044
166#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
167#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]169#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]170#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
171#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
172#define MSR_IA32_MC0_CTL2 0x00000280
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]174#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]175#define MSR_P6_PERFCTR0 0x000000c1
176#define MSR_P6_PERFCTR1 0x000000c2
177#define MSR_P6_EVNTSEL0 0x00000186
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]179#define MSR_P6_EVNTSEL1 0x00000187
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]180#define MSR_KNC_PERFCTR0 0x00000020
181#define MSR_KNC_PERFCTR1 0x00000021
182#define MSR_KNC_EVNTSEL0 0x00000028
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]184#define MSR_KNC_EVNTSEL1 0x00000029
185#define MSR_IA32_PMC0 0x000004c1
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]186#define MSR_AMD64_PATCH_LEVEL 0x0000008b
187#define MSR_AMD64_TSC_RATIO 0xc0000104
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]189#define MSR_AMD64_NB_CFG 0xc001001f
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]190#define MSR_AMD64_PATCH_LOADER 0xc0010020
191#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
192#define MSR_AMD64_OSVW_STATUS 0xc0010141
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define MSR_AMD64_LS_CFG 0xc0011020
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]195#define MSR_AMD64_DC_CFG 0xc0011022
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]196#define MSR_AMD64_BU_CFG2 0xc001102a
197#define MSR_AMD64_IBSFETCHCTL 0xc0011030
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]199#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
200#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]201#define MSR_AMD64_IBSFETCH_REG_COUNT 3
202#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]204#define MSR_AMD64_IBSOPCTL 0xc0011033
205#define MSR_AMD64_IBSOPRIP 0xc0011034
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]206#define MSR_AMD64_IBSOPDATA 0xc0011035
207#define MSR_AMD64_IBSOPDATA2 0xc0011036
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]209#define MSR_AMD64_IBSOPDATA3 0xc0011037
210#define MSR_AMD64_IBSDCLINAD 0xc0011038
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]211#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
212#define MSR_AMD64_IBSOP_REG_COUNT 7
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]214#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
215#define MSR_AMD64_IBSCTL 0xc001103a
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]216#define MSR_AMD64_IBSBRTARGET 0xc001103b
217#define MSR_AMD64_IBS_REG_COUNT_MAX 8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]219#define MSR_F16H_L2I_PERF_CTL 0xc0010230
220#define MSR_F16H_L2I_PERF_CTR 0xc0010231
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]221#define MSR_F15H_PERF_CTL 0xc0010200
222#define MSR_F15H_PERF_CTR 0xc0010201
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]224#define MSR_F15H_NB_PERF_CTL 0xc0010240
225#define MSR_F15H_NB_PERF_CTR 0xc0010241
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]226#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
227#define FAM10H_MMIO_CONF_ENABLE (1<<0)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]229#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
230#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]231#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
232#define FAM10H_MMIO_CONF_BASE_SHIFT 20
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]234#define MSR_FAM10H_NODE_ID 0xc001100c
235#define MSR_K8_TOP_MEM1 0xc001001a
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]236#define MSR_K8_TOP_MEM2 0xc001001d
237#define MSR_K8_SYSCFG 0xc0010010
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]239#define MSR_K8_INT_PENDING_MSG 0xc0010055
240#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]241#define MSR_K8_TSEG_ADDR 0xc0010112
242#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]244#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000
245#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]246#define MSR_K7_EVNTSEL0 0xc0010000
247#define MSR_K7_PERFCTR0 0xc0010004
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]249#define MSR_K7_EVNTSEL1 0xc0010001
250#define MSR_K7_PERFCTR1 0xc0010005
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]251#define MSR_K7_EVNTSEL2 0xc0010002
252#define MSR_K7_PERFCTR2 0xc0010006
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]254#define MSR_K7_EVNTSEL3 0xc0010003
255#define MSR_K7_PERFCTR3 0xc0010007
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]256#define MSR_K7_CLK_CTL 0xc001001b
257#define MSR_K7_HWCR 0xc0010015
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]259#define MSR_K7_FID_VID_CTL 0xc0010041
260#define MSR_K7_FID_VID_STATUS 0xc0010042
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]261#define MSR_K6_WHCR 0xc0000082
262#define MSR_K6_UWCCR 0xc0000085
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]264#define MSR_K6_EPMR 0xc0000086
265#define MSR_K6_PSOR 0xc0000087
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]266#define MSR_K6_PFIR 0xc0000088
267#define MSR_IDT_FCR1 0x00000107
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]269#define MSR_IDT_FCR2 0x00000108
270#define MSR_IDT_FCR3 0x00000109
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]271#define MSR_IDT_FCR4 0x0000010a
272#define MSR_IDT_MCR0 0x00000110
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]274#define MSR_IDT_MCR1 0x00000111
275#define MSR_IDT_MCR2 0x00000112
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]276#define MSR_IDT_MCR3 0x00000113
277#define MSR_IDT_MCR4 0x00000114
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]279#define MSR_IDT_MCR5 0x00000115
280#define MSR_IDT_MCR6 0x00000116
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]281#define MSR_IDT_MCR7 0x00000117
282#define MSR_IDT_MCR_CTRL 0x00000120
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]284#define MSR_VIA_FCR 0x00001107
285#define MSR_VIA_LONGHAUL 0x0000110a
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]286#define MSR_VIA_RNG 0x0000110b
287#define MSR_VIA_BCR2 0x00001147
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]289#define MSR_TMTA_LONGRUN_CTRL 0x80868010
290#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]291#define MSR_TMTA_LRTI_READOUT 0x80868018
292#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]294#define MSR_IA32_P5_MC_ADDR 0x00000000
295#define MSR_IA32_P5_MC_TYPE 0x00000001
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]296#define MSR_IA32_TSC 0x00000010
297#define MSR_IA32_PLATFORM_ID 0x00000017
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]299#define MSR_IA32_EBL_CR_POWERON 0x0000002a
300#define MSR_EBC_FREQUENCY_ID 0x0000002c
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]301#define MSR_SMI_COUNT 0x00000034
302#define MSR_IA32_FEATURE_CONTROL 0x0000003a
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]304#define MSR_IA32_TSC_ADJUST 0x0000003b
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]305#define MSR_IA32_BNDCFGS 0x00000d90
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]306#define FEATURE_CONTROL_LOCKED (1<<0)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]307#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]309#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]310#define MSR_IA32_APICBASE 0x0000001b
311#define MSR_IA32_APICBASE_BSP (1<<8)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]312#define MSR_IA32_APICBASE_ENABLE (1<<11)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]314#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]315#define MSR_IA32_TSCDEADLINE 0x000006e0
316#define MSR_IA32_UCODE_WRITE 0x00000079
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]317#define MSR_IA32_UCODE_REV 0x0000008b
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]319#define MSR_IA32_PERF_STATUS 0x00000198
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]320#define MSR_IA32_PERF_CTL 0x00000199
321#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]322#define MSR_AMD_PERF_STATUS 0xc0010063
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]324#define MSR_AMD_PERF_CTL 0xc0010062
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]325#define MSR_IA32_MPERF 0x000000e7
326#define MSR_IA32_APERF 0x000000e8
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]327#define MSR_IA32_THERM_CONTROL 0x0000019a
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]329#define MSR_IA32_THERM_INTERRUPT 0x0000019b
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]330#define THERM_INT_HIGH_ENABLE (1 << 0)
331#define THERM_INT_LOW_ENABLE (1 << 1)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]332#define THERM_INT_PLN_ENABLE (1 << 24)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]334#define MSR_IA32_THERM_STATUS 0x0000019c
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]335#define THERM_STATUS_PROCHOT (1 << 0)
336#define THERM_STATUS_POWER_LIMIT (1 << 10)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]337#define MSR_THERM2_CTL 0x0000019d
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]339#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]340#define MSR_IA32_MISC_ENABLE 0x000001a0
341#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]342#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]344#define ENERGY_PERF_BIAS_PERFORMANCE 0
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]345#define ENERGY_PERF_BIAS_NORMAL 6
346#define ENERGY_PERF_BIAS_POWERSAVE 15
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]347#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]349#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]350#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
351#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]352#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]354#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]355#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
356#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]357#define THERM_SHIFT_THRESHOLD0 8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]359#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]360#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
361#define THERM_SHIFT_THRESHOLD1 16
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]362#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]364#define THERM_STATUS_THRESHOLD0 (1 << 6)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]365#define THERM_LOG_THRESHOLD0 (1 << 7)
366#define THERM_STATUS_THRESHOLD1 (1 << 8)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]367#define THERM_LOG_THRESHOLD1 (1 << 9)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]369#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
370#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
371#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
372#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]374#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
375#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
376#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
377#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]379#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
380#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
381#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
382#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]384#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
385#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
386#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
387#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]389#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
390#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
391#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
392#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]394#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
395#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
396#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
397#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]399#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
400#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
401#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
402#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
404#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
405#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
406#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
407#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
409#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
410#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
411#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
412#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
414#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
415#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
416#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
417#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
419#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
420#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
421#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
422#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
424#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
425#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
426#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
427#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
429#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
430#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]431#define MSR_IA32_TSC_DEADLINE 0x000006E0
432#define MSR_IA32_MCG_EAX 0x00000180
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]434#define MSR_IA32_MCG_EBX 0x00000181
435#define MSR_IA32_MCG_ECX 0x00000182
436#define MSR_IA32_MCG_EDX 0x00000183
437#define MSR_IA32_MCG_ESI 0x00000184
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]439#define MSR_IA32_MCG_EDI 0x00000185
440#define MSR_IA32_MCG_EBP 0x00000186
441#define MSR_IA32_MCG_ESP 0x00000187
442#define MSR_IA32_MCG_EFLAGS 0x00000188
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]444#define MSR_IA32_MCG_EIP 0x00000189
445#define MSR_IA32_MCG_RESERVED 0x0000018a
446#define MSR_P4_BPU_PERFCTR0 0x00000300
447#define MSR_P4_BPU_PERFCTR1 0x00000301
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]449#define MSR_P4_BPU_PERFCTR2 0x00000302
450#define MSR_P4_BPU_PERFCTR3 0x00000303
451#define MSR_P4_MS_PERFCTR0 0x00000304
452#define MSR_P4_MS_PERFCTR1 0x00000305
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]454#define MSR_P4_MS_PERFCTR2 0x00000306
455#define MSR_P4_MS_PERFCTR3 0x00000307
456#define MSR_P4_FLAME_PERFCTR0 0x00000308
457#define MSR_P4_FLAME_PERFCTR1 0x00000309
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]459#define MSR_P4_FLAME_PERFCTR2 0x0000030a
460#define MSR_P4_FLAME_PERFCTR3 0x0000030b
461#define MSR_P4_IQ_PERFCTR0 0x0000030c
462#define MSR_P4_IQ_PERFCTR1 0x0000030d
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]464#define MSR_P4_IQ_PERFCTR2 0x0000030e
465#define MSR_P4_IQ_PERFCTR3 0x0000030f
466#define MSR_P4_IQ_PERFCTR4 0x00000310
467#define MSR_P4_IQ_PERFCTR5 0x00000311
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]469#define MSR_P4_BPU_CCCR0 0x00000360
470#define MSR_P4_BPU_CCCR1 0x00000361
471#define MSR_P4_BPU_CCCR2 0x00000362
472#define MSR_P4_BPU_CCCR3 0x00000363
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]474#define MSR_P4_MS_CCCR0 0x00000364
475#define MSR_P4_MS_CCCR1 0x00000365
476#define MSR_P4_MS_CCCR2 0x00000366
477#define MSR_P4_MS_CCCR3 0x00000367
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]479#define MSR_P4_FLAME_CCCR0 0x00000368
480#define MSR_P4_FLAME_CCCR1 0x00000369
481#define MSR_P4_FLAME_CCCR2 0x0000036a
482#define MSR_P4_FLAME_CCCR3 0x0000036b
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]484#define MSR_P4_IQ_CCCR0 0x0000036c
485#define MSR_P4_IQ_CCCR1 0x0000036d
486#define MSR_P4_IQ_CCCR2 0x0000036e
487#define MSR_P4_IQ_CCCR3 0x0000036f
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]489#define MSR_P4_IQ_CCCR4 0x00000370
490#define MSR_P4_IQ_CCCR5 0x00000371
491#define MSR_P4_ALF_ESCR0 0x000003ca
492#define MSR_P4_ALF_ESCR1 0x000003cb
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]494#define MSR_P4_BPU_ESCR0 0x000003b2
495#define MSR_P4_BPU_ESCR1 0x000003b3
496#define MSR_P4_BSU_ESCR0 0x000003a0
497#define MSR_P4_BSU_ESCR1 0x000003a1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]499#define MSR_P4_CRU_ESCR0 0x000003b8
500#define MSR_P4_CRU_ESCR1 0x000003b9
501#define MSR_P4_CRU_ESCR2 0x000003cc
502#define MSR_P4_CRU_ESCR3 0x000003cd
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]504#define MSR_P4_CRU_ESCR4 0x000003e0
505#define MSR_P4_CRU_ESCR5 0x000003e1
506#define MSR_P4_DAC_ESCR0 0x000003a8
507#define MSR_P4_DAC_ESCR1 0x000003a9
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]509#define MSR_P4_FIRM_ESCR0 0x000003a4
510#define MSR_P4_FIRM_ESCR1 0x000003a5
511#define MSR_P4_FLAME_ESCR0 0x000003a6
512#define MSR_P4_FLAME_ESCR1 0x000003a7
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]514#define MSR_P4_FSB_ESCR0 0x000003a2
515#define MSR_P4_FSB_ESCR1 0x000003a3
516#define MSR_P4_IQ_ESCR0 0x000003ba
517#define MSR_P4_IQ_ESCR1 0x000003bb
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]519#define MSR_P4_IS_ESCR0 0x000003b4
520#define MSR_P4_IS_ESCR1 0x000003b5
521#define MSR_P4_ITLB_ESCR0 0x000003b6
522#define MSR_P4_ITLB_ESCR1 0x000003b7
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]524#define MSR_P4_IX_ESCR0 0x000003c8
525#define MSR_P4_IX_ESCR1 0x000003c9
526#define MSR_P4_MOB_ESCR0 0x000003aa
527#define MSR_P4_MOB_ESCR1 0x000003ab
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]529#define MSR_P4_MS_ESCR0 0x000003c0
530#define MSR_P4_MS_ESCR1 0x000003c1
531#define MSR_P4_PMH_ESCR0 0x000003ac
532#define MSR_P4_PMH_ESCR1 0x000003ad
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]534#define MSR_P4_RAT_ESCR0 0x000003bc
535#define MSR_P4_RAT_ESCR1 0x000003bd
536#define MSR_P4_SAAT_ESCR0 0x000003ae
537#define MSR_P4_SAAT_ESCR1 0x000003af
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]539#define MSR_P4_SSU_ESCR0 0x000003be
540#define MSR_P4_SSU_ESCR1 0x000003bf
541#define MSR_P4_TBPU_ESCR0 0x000003c2
542#define MSR_P4_TBPU_ESCR1 0x000003c3
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]544#define MSR_P4_TC_ESCR0 0x000003c4
545#define MSR_P4_TC_ESCR1 0x000003c5
546#define MSR_P4_U2L_ESCR0 0x000003b0
547#define MSR_P4_U2L_ESCR1 0x000003b1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]549#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
550#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
551#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
552#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]554#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
555#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
556#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
557#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]559#define MSR_GEODE_BUSCONT_CONF0 0x00001900
560#define MSR_IA32_VMX_BASIC 0x00000480
561#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
562#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]564#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
565#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
566#define MSR_IA32_VMX_MISC 0x00000485
567#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]569#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
570#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
571#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
572#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]574#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
575#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
576#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
577#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]579#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
580#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]581#define MSR_IA32_VMX_VMFUNC 0x00000491
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]582#define VMX_BASIC_VMCS_SIZE_SHIFT 32
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]584#define VMX_BASIC_64 0x0001000000000000LLU
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]585#define VMX_BASIC_MEM_TYPE_SHIFT 50
586#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
587#define VMX_BASIC_MEM_TYPE_WB 6LLU
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]589#define VMX_BASIC_INOUT 0x0040000000000000LLU
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]590#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]591#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]592#define MSR_VM_CR 0xc0010114
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesabd62612013-11-08 11:45:48 -0800[diff] [blame]594#define MSR_VM_IGNNE 0xc0010115
595#define MSR_VM_HSAVE_PA 0xc0010117
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]596#endif