| commit | 7ad12ae7758eaca2dbb5ec08094278485850be05 | [log] [tgz] |
|---|---|---|
| author | Sander de Smalen <sander.desmalen@arm.com> | Fri Apr 20 08:54:49 2018 +0000 |
| committer | Sander de Smalen <sander.desmalen@arm.com> | Fri Apr 20 08:54:49 2018 +0000 |
| tree | c76ded53ae4eb2832baf256d1b8f1505e0bfba35 | |
| parent | caacf2398285cd0c5b7e5b853f146f511ecfad17 [diff] |
[AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes. Summary: This is patch [3/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: SjoerdMeijer Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45689 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330406 91177308-0d34-0410-b5e6-96231b3b80d8