| commit | 14cfc65a1c5022a3fd38d6c8ed308692c620ddfe | [log] [tgz] |
|---|---|---|
| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Thu Apr 05 16:42:32 2018 +0000 |
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Thu Apr 05 16:42:32 2018 +0000 |
| tree | d7fdd5c6f533522b434ea27f015c73c7fa694f67 | |
| parent | 0122eda6e9756f463fe1cb1d6b5126f2066104cc [diff] |
[documentation][llvm-mca] Update the documentation. Scheduling models can now describe processor register files and retire control units. This updates the existing documentation and the README file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329311 91177308-0d34-0410-b5e6-96231b3b80d8