| commit | 8e4a223f7bb3ee0ae6a0888b8e670a6bd4983a0a | [log] [tgz] |
|---|---|---|
| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Mon May 19 20:38:59 2014 +0000 |
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | Mon May 19 20:38:59 2014 +0000 |
| tree | 629d5a730a36b7a4fafafba32d37a8c012b8ff8b | |
| parent | 86ad7b70cb994a9ebde84053026e560a37061ce9 [diff] |
[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209159 91177308-0d34-0410-b5e6-96231b3b80d8