| commit | 0f3982734058d9039d986e9d1dd3a879ff3512f0 | [log] [tgz] |
|---|---|---|
| author | Tom Stellard <thomas.stellard@amd.com> | Fri Nov 22 23:07:58 2013 +0000 |
| committer | Tom Stellard <thomas.stellard@amd.com> | Fri Nov 22 23:07:58 2013 +0000 |
| tree | af772a39274b3bf23567b7b493058f58da04b7a9 | |
| parent | 695de7692c26f5cb57eb67edb6b9ccf6d0ddafa2 [diff] |
R600/SI: Fixing handling of condition codes We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8