| commit | 577615c652f7a20689f168e0c1e393a1a55a3401 | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@intel.com> | Mon May 21 19:27:50 2018 +0000 |
| committer | Craig Topper <craig.topper@intel.com> | Mon May 21 19:27:50 2018 +0000 |
| tree | b4241daafb6d7b2eb3ccae9bb015cb17078ea2b2 | |
| parent | 09ac21d393d64fd04e4bd702fc48adfe89f7dfa4 [diff] |
[X86] Add test cases for missed vector rotate matching due to SimplifyDemandedBits interfering with the AND masks As requested in D47116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332869 91177308-0d34-0410-b5e6-96231b3b80d8