| commit | 72d5de4e70614b9e8f891eb3a972b946df224abf | [log] [tgz] |
|---|---|---|
| author | Alex Bradbury <asb@lowrisc.org> | Tue Nov 01 23:40:28 2016 +0000 |
| committer | Alex Bradbury <asb@lowrisc.org> | Tue Nov 01 23:40:28 2016 +0000 |
| tree | 53f58047625029ab89aef8078ead0674ce31e95f | |
| parent | ac4d1bb2a0ccc2f29f5e8fb304acf030b76151a7 [diff] |
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
For now, only add instruction definitions for basic ALU operations. Our
initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D23561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285769 91177308-0d34-0410-b5e6-96231b3b80d8