| commit | 8499a501e4381f8afd654eff0001e1ad4dc7bc09 | [log] [tgz] |
|---|---|---|
| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | Sun Dec 28 08:54:45 2014 +0000 |
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | Sun Dec 28 08:54:45 2014 +0000 |
| tree | 30810d0cf870c3b5a8cc95aef239b093eb8d140f | |
| parent | 04c853b26927b29ed61c66ddecfed2824ca216fe [diff] |
Scalarizer for masked load and store intrinsics. Masked vector intrinsics are a part of common LLVM IR, but they are really supported on AVX2 and AVX-512 targets. I added a code that translates masked intrinsic for all other targets. The masked vector intrinsic is converted to a chain of scalar operations inside conditional basic blocks. http://reviews.llvm.org/D6436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224897 91177308-0d34-0410-b5e6-96231b3b80d8