| commit | 68e835e9f0298f240716bcb6df0ea8c24e1497d3 | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@intel.com> | Thu Sep 06 23:55:34 2018 +0000 |
| committer | Craig Topper <craig.topper@intel.com> | Thu Sep 06 23:55:34 2018 +0000 |
| tree | c41c06dcf83ff484f097c88bfa770184e70912be | |
| parent | 1c0d3f0a7bd218f53928aaa24c1e29cafc863170 [diff] |
[X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel. The ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341605 91177308-0d34-0410-b5e6-96231b3b80d8