| commit | acf8758c20c2fd51db8dfb533dfc01941f8112e1 | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@intel.com> | Mon Nov 06 22:49:04 2017 +0000 |
| committer | Craig Topper <craig.topper@intel.com> | Mon Nov 06 22:49:04 2017 +0000 |
| tree | 7784bcf39832c0168e3a705995cab344be12d110 | |
| parent | 490bc3940dd4098ef1cd81c1f3f19203b4317d3f [diff] |
[X86] Make FeatureAVX512 imply FeatureF16C. The EVEX to VEX pass is already assuming this is true under AVX512VL. We had special patterns to use zmm instructions if VLX and F16C weren't available. Instead just make AVX512 imply F16C to make the EVEX to VEX behavior explicitly legal and remove the extra patterns. All known CPUs with AVX512 have F16C so this should safe for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317521 91177308-0d34-0410-b5e6-96231b3b80d8