96ed12f5f361a0a95d3e7461beb38380d7c059e5 - platform_external_llvm

commit	96ed12f5f361a0a95d3e7461beb38380d7c059e5	[log] [tgz]
author	Francis Visoiu Mistrih <francisvm@yahoo.com>	Thu Jan 18 17:59:06 2018 +0000
committer	Francis Visoiu Mistrih <francisvm@yahoo.com>	Thu Jan 18 17:59:06 2018 +0000
tree	3c98c04bc121db2f9472f8cbc3d124570a196dda
parent	fb4e566d08a9e42c1d64443c52169ca422d971d5 [diff]

[CodeGen] Print RegClasses on MI in verbose mode

r322086 removed the trailing information describing reg classes for each
register.

This patch adds printing reg classes next to every register when
individual operands/instructions/basic blocks are printed. In the case
of dumping MIR or printing a full function, by default don't print it.

Differential Revision: https://reviews.llvm.org/D42239

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322867 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/MachineBasicBlock.h[diff]
include/llvm/CodeGen/MachineInstr.h[diff]
include/llvm/CodeGen/MachineOperand.h[diff]
lib/CodeGen/MIRPrinter.cpp[diff]
lib/CodeGen/MachineBasicBlock.cpp[diff]
lib/CodeGen/MachineFunction.cpp[diff]
lib/CodeGen/MachineInstr.cpp[diff]
lib/CodeGen/MachineOperand.cpp[diff]
lib/CodeGen/MachineOptimizationRemarkEmitter.cpp[diff]
test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll[diff]
test/CodeGen/AArch64/aarch64-stp-cluster.ll[diff]
test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll[diff]
test/CodeGen/AArch64/arm64-misched-memdep-bug.ll[diff]
test/CodeGen/ARM/misched-int-basic-thumb2.mir[diff]
test/CodeGen/ARM/misched-int-basic.mir[diff]
test/CodeGen/ARM/single-issue-r52.mir[diff]
test/CodeGen/X86/GlobalISel/x86_64-fallback.ll[diff]
test/CodeGen/X86/misched-copy.ll[diff]
unittests/CodeGen/MachineOperandTest.cpp[diff]

19 files changed

tree: 3c98c04bc121db2f9472f8cbc3d124570a196dda