| commit | 0ee7f2ef5cadacbeec590c7bffc0a4363074ea5d | [log] [tgz] |
|---|---|---|
| author | Chad Rosier <mcrosier@codeaurora.org> | Tue Sep 29 16:07:32 2015 +0000 |
| committer | Chad Rosier <mcrosier@codeaurora.org> | Tue Sep 29 16:07:32 2015 +0000 |
| tree | f34b9b554ee2b4f179fff711f8547e8dccee012b | |
| parent | a9db22a72adfa23572762457a88d104085f97f6d [diff] |
[AArch64] Scale offsets by the size of the memory operation. NFC. The immediate in the load/store should be scaled by the size of the memory operation, not the size of the register being loaded/stored. This change gets us one step closer to forming LDPSW instructions. This change also enables pre- and post-indexing for halfword and byte loads and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248804 91177308-0d34-0410-b5e6-96231b3b80d8