| commit | d4b8b33a93d04151332df2fa938ae7d2bff72ba4 | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@intel.com> | Thu Apr 05 04:42:01 2018 +0000 |
| committer | Craig Topper <craig.topper@intel.com> | Thu Apr 05 04:42:01 2018 +0000 |
| tree | 90c33c697bf963b788cd7e97bed586ccab9bb762 | |
| parent | 224b7027524942efb701f50650034c06f5e002d4 [diff] |
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge. We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329252 91177308-0d34-0410-b5e6-96231b3b80d8