| commit | ad69a64d4aac849d14e51af0bb547a542d4b50bf | [log] [tgz] |
|---|---|---|
| author | Chad Rosier <mcrosier@codeaurora.org> | Thu Sep 03 18:13:57 2015 +0000 |
| committer | Chad Rosier <mcrosier@codeaurora.org> | Thu Sep 03 18:13:57 2015 +0000 |
| tree | eb642a182d01cdadc5b75d265d9578d167b3ca45 | |
| parent | 7ab20090242a84ebba3afa25973fda03be5f2a7e [diff] |
[AArch64] Improve ISel using across lane addition reduction. In vectorized add reduction code, the final "reduce" step is sub-optimal. This change wll combine : ext v1.16b, v0.16b, v0.16b, #8 add v0.4s, v1.4s, v0.4s dup v1.4s, v0.s[1] add v0.4s, v1.4s, v0.4s into addv s0, v0.4s PR21371 http://reviews.llvm.org/D12325 Patch by Jun Bum Lim <junbuml@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246790 91177308-0d34-0410-b5e6-96231b3b80d8