commit | c1fa0731c3def3cacc8491c12e008eeb605f930f | [log] [tgz] |
---|---|---|
author | Matthias Braun <matze@braunis.de> | Wed Jan 18 00:59:19 2017 +0000 |
committer | Matthias Braun <matze@braunis.de> | Wed Jan 18 00:59:19 2017 +0000 |
tree | 4cb05fb09e235886034f692a5c4a9b51fd40fb1e | |
parent | 13bc67e541a37da51c8bf46530c90f58cf720b65 [diff] |
MIRParser: Allow regclass specification on operand You can now define the register class of a virtual register on the operand itself avoiding the need to use a "registers:" block. Example: "%0:gr64 = COPY %rax" Differential Revision: https://reviews.llvm.org/D22398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8