| commit | c5330c71212d6b9764f8f221baaffa74b4881d84 | [log] [tgz] |
|---|---|---|
| author | Sander de Smalen <sander.desmalen@arm.com> | Thu Apr 26 08:43:22 2018 +0000 |
| committer | Sander de Smalen <sander.desmalen@arm.com> | Thu Apr 26 08:43:22 2018 +0000 |
| tree | 1d10d89353d362af1fbc89f6fe5675cb3c159fc1 | |
| parent | 9821cf74ede777a9302d705056e43fdabcb2fb69 [diff] |
[AArch64][SVE] Asm: Negative tests for all LD1 gather (scalar+vector) load instructions. Patch [3/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330929 91177308-0d34-0410-b5e6-96231b3b80d8