| commit | f78df63bf0318d2f8daf33dc1ec6f5b69864c948 | [log] [tgz] |
|---|---|---|
| author | Amara Emerson <aemerson@apple.com> | Mon Oct 09 15:15:09 2017 +0000 |
| committer | Amara Emerson <aemerson@apple.com> | Mon Oct 09 15:15:09 2017 +0000 |
| tree | 1d7dcf075cdbc2e26fa67ba1fbf1134be4a0498f | |
| parent | 18fc4d6b1d866f52f3067ca6c50b1cc37c6f0dd4 [diff] |
[AArch64] Improve codegen for inverted overflow checking intrinsics E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the inverted condition code for the CSEL. rdar://28495949 Reviewed By: kristof.beyls Differential Revision: https://reviews.llvm.org/D38160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315205 91177308-0d34-0410-b5e6-96231b3b80d8