| commit | fe5554490adbce96f78cb478d956480ef25d59b1 | [log] [tgz] |
|---|---|---|
| author | Sanjay Patel <spatel@rotateright.com> | Wed Sep 19 21:48:30 2018 +0000 |
| committer | Sanjay Patel <spatel@rotateright.com> | Wed Sep 19 21:48:30 2018 +0000 |
| tree | 0542f4681a460a780d42a667fd6eea73c792db2e | |
| parent | 2327768f69d30d24810203a18978ecb737d38bfd [diff] |
[SelectionDAG] allow vector types with isBitwiseNot() The test diff in not-and-simplify.ll is from a use in SimplifyDemandedBits, and the test diff in add.ll is from a DAGCombiner transform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342594 91177308-0d34-0410-b5e6-96231b3b80d8