tree 43f239bb376f3b4f6d3b06439f7d18b77d205383
parent cba94587c780e7f6173d5cab9eb9f5d1b3e0f6c9
author Craig Topper <craig.topper@intel.com> 1504378426 +0000
committer Craig Topper <craig.topper@intel.com> 1504378426 +0000

[X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64

Summary:
ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort.

We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code.

Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one.

The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed.

Reviewers: spatel, zvi, igorb, guyblank, RKSimon

Reviewed By: guyblank

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37320

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312422 91177308-0d34-0410-b5e6-96231b3b80d8