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review.blissroms.org / platform_external_llvm / 39cd0c8e477255a7296b2bd1dc67193f8d38c003
  1. 39cd0c8 Remove Function::getParamAttributes and use the AttributeSet accessor methods instead. by Bill Wendling · 13 years ago
  2. 831737d Remove the Function::getFnAttributes method in favor of using the AttributeSet by Bill Wendling · 13 years ago
  3. 37766035 s/hasAttribute/contains/g to be more consistent with other method names. by Bill Wendling · 13 years ago
  4. db23675 LoopVectorizer: Fix a bug in the code that updates the loop exiting block. by Nadav Rotem · 13 years ago
  5. a654292 Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID by Dmitri Gribenko · 13 years ago
  6. 979aff6 Add a few more c'tors: by Bill Wendling · 13 years ago
  7. a51edf0 Add a check to the test Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll by Dmitri Gribenko · 13 years ago
  8. 529ec71 Add a few (as yet unused) query methods to determine if the attribute that's by Bill Wendling · 13 years ago
  9. b4912b9 Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID by Dmitri Gribenko · 13 years ago
  10. 435654b Uniquify the AttributeImpl based on the Constant pointer, since those are by Bill Wendling · 13 years ago
  11. c966e08 s/Raw/getBitMask/g to be more in line with current naming conventions. This method won't be sticking around. by Bill Wendling · 13 years ago
  12. f35cb76 llvm/test/Transforms/GVN/null-aliases-nothing.ll: Fix a RUN line not to emit ModuleID. by NAKAMURA Takumi · 13 years ago
  13. 22d8f0d Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. by Craig Topper · 13 years ago
  14. 6f57f39 Merge similar functionality using a nested switch. by Craig Topper · 13 years ago
  15. 6d183e4 Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. by Craig Topper · 13 years ago
  16. c20323a Simplify code, no functionality change. by Jakub Staszak · 13 years ago
  17. 3c0307d Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h. by Jakub Staszak · 13 years ago
  18. 7c1683d Use a 'Constant' object instead of a bit field to store the attribute data. by Bill Wendling · 13 years ago
  19. 4d5e5e5 Use the accessor method instead of the raw ivar to get the bits. by Bill Wendling · 13 years ago
  20. a84e750 Nuke some dead code that snuck in some how. I thought I had already by Chandler Carruth · 13 years ago
  21. 73527d3 Fix a stunning oversight in the inline cost analysis. It was never by Chandler Carruth · 13 years ago
  22. ba94204 Teach the inline cost analysis about calls that can be simplified and by Chandler Carruth · 13 years ago
  23. e949aa1 Teach instsimplify to use the constant folder where appropriate for by Chandler Carruth · 13 years ago
  24. c98bd9f Add entry points to instsimplify for simplifying calls. The entry points by Chandler Carruth · 13 years ago
  25. f045df1 Add proper support for -fsanitize-blacklist= flag for TSan and MSan. LLVM part. by Alexey Samsonov · 13 years ago
  26. ae34b42 CostModel: initial checkin for code that estimates the cost of special shuffles. by Nadav Rotem · 13 years ago
  27. 40ef8b7 wrap 80-col lines. by Nadav Rotem · 13 years ago
  28. 0509db2 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. by Nadav Rotem · 13 years ago
  29. 587fb1d Reverse the 'if' condition and reduce the indentation. by Nadav Rotem · 13 years ago
  30. cccccab Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. by Craig Topper · 13 years ago
  31. 1a330af AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function. by Nadav Rotem · 13 years ago
  32. d5fc507 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. by Craig Topper · 13 years ago
  33. a455fdd Add support to BasicBlocks for iterating backwards over the by Chandler Carruth · 13 years ago
  34. edf315c Provide a common half-open interval map info implementation, and just by Chandler Carruth · 13 years ago
  35. 7ccc2f7 Make this parameter be named consistently with most other by Chandler Carruth · 13 years ago
  36. bdb0c0a docs: Add FAQ about "storing to a virtual register". by Sean Silva · 13 years ago
  37. 6fa16e1 docs: Move link to the new "external tutorials" area. by Sean Silva · 13 years ago
  38. 1c8b825 [ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments by Alexey Samsonov · 13 years ago
  39. 3190be9 DAGCombinerInformation: add a getter that exposes the dagcombine level. by Nadav Rotem · 13 years ago
  40. 44185d4 Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer by Alexey Samsonov · 13 years ago
  41. 898c5e8 docs: Update the benchmark with updated perf numbers. by Nadav Rotem · 13 years ago
  42. d6fb53a On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized by Nadav Rotem · 13 years ago
  43. 3c22a44 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. by Nadav Rotem · 13 years ago
  44. 068aec5 Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. by Craig Topper · 13 years ago
  45. 444b4bf Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum. by Nadav Rotem · 13 years ago
  46. d0f28c0 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. by Craig Topper · 13 years ago
  47. 025c5de Update tablegen parser to allow defm names to start with #NAME. by Craig Topper · 13 years ago
  48. 87073aa Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. by Craig Topper · 13 years ago
  49. 766cbae Mark the divide instructions as hasSideEffects=0. by Craig Topper · 13 years ago
  50. 64f824c For the dwarf5 split debug info code split out the string section by Eric Christopher · 13 years ago
  51. d84aa00 FileCheck-ize. by Eric Christopher · 13 years ago
  52. 5211876 FileCheck-ize. by Eric Christopher · 13 years ago
  53. 0b9c5e2 Add hasSideEffects=0 to CMP*rr_REV. by Craig Topper · 13 years ago
  54. d92ee75 whitespace by Nadav Rotem · 13 years ago
  55. 5e6a86c Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. by Craig Topper · 13 years ago
  56. 32b3768 Right now all of the relocations are 32-bit dwarf, and the relocation by Eric Christopher · 13 years ago
  57. 5dd8394 If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified. by Nadav Rotem · 13 years ago
  58. e9fd6ad Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. by Craig Topper · 13 years ago
  59. ee5b63c Add hasSideEffects=0 to some atomic instructions. by Craig Topper · 13 years ago
  60. b87a5b3 Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. by Craig Topper · 13 years ago
  61. dbf5081 80 columns. No functionality change. by Nick Lewycky · 13 years ago
  62. 1dec62e Remove mid-optimizer warning. This situation should be handled differently, by Nick Lewycky · 13 years ago
  63. 37cb839 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. by Craig Topper · 13 years ago
  64. a85cbfe Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. by Craig Topper · 13 years ago
  65. 8c6cb31 Update the docs with the new workload that was added. by Nadav Rotem · 13 years ago
  66. 13eb1e7 LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1 by Nadav Rotem · 13 years ago
  67. f1a26cf Fix comment typo by Eli Bendersky · 13 years ago
  68. b53be53 [msan] Raise alignment of origin stores/loads when possible. by Evgeniy Stepanov · 13 years ago
  69. ab29644 [msan] Expand the file comment with track-origins info. by Evgeniy Stepanov · 13 years ago
  70. 23c5021 Fix quoting in configure. Patch by Krzysztof Parzyszek! by Benjamin Kramer · 13 years ago
  71. 0a5ead9 Merge still more SSE/AVX instruction definitions. by Craig Topper · 13 years ago
  72. 07555fc Merge more SSE/AVX instruction definitions. by Craig Topper · 13 years ago
  73. fc093de TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction(). by NAKAMURA Takumi · 13 years ago
  74. 00ba301 revert an accidental commit. by Nadav Rotem · 13 years ago
  75. 755841d Fix 80 column violation. by Craig Topper · 13 years ago
  76. 6f9d44e Fix class name in comment. by Craig Topper · 13 years ago
  77. 219bc2d Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. by Craig Topper · 13 years ago
  78. f7769e3 Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel. by Nadav Rotem · 13 years ago
  79. 02082ef Remove 'v' from mnemonic to fix asm matching failures. by Craig Topper · 13 years ago
  80. 3cdc382 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. by Craig Topper · 13 years ago
  81. a05f7cb Reformat the docs. by Nadav Rotem · 13 years ago
  82. 4595528 white space by Nadav Rotem · 13 years ago
  83. 09a326d Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN by Craig Topper · 13 years ago
  84. 1fe132a Merge an AVX/SSE 256-bit and 128-bit multiclass. by Craig Topper · 13 years ago
  85. b5c590a Mark VANDNPD/VANDNPDS as not commutable. by Craig Topper · 13 years ago
  86. b1a3baf llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. by NAKAMURA Takumi · 13 years ago
  87. 05c8fd9 llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. by NAKAMURA Takumi · 13 years ago
  88. 174a3d3 Remove alignment from a bunch more VEX encoded operations in the folding tables. by Craig Topper · 13 years ago
  89. d83a73a Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... by Craig Topper · 13 years ago
  90. 1ac0046 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. by Craig Topper · 13 years ago
  91. a777284 BBVectorize: Use VTTI to compute costs for intrinsics vectorization by Hal Finkel · 13 years ago
  92. 0f77910 Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. by Craig Topper · 13 years ago
  93. 1d59f5f LoopVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 13 years ago
  94. 64a7a24 BBVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 13 years ago
  95. abdf755 Loosen scheduling restrictions on the PPC dcbt intrinsic by Hal Finkel · 13 years ago
  96. cd9ea51 Expand PPC64 atomic load and store by Hal Finkel · 13 years ago
  97. 59a65f7 [msan] Fix handling of vectors of pointers. by Evgeniy Stepanov · 13 years ago
  98. 6607716 [msan] Fix handling of select with vector condition. by Evgeniy Stepanov · 13 years ago
  99. 50ec431 Harden test so it's not affected by changes to compare lowering. by Benjamin Kramer · 13 years ago
  100. 99f7806 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. by Benjamin Kramer · 13 years ago