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review.blissroms.org / platform_external_llvm / 3b1040c703c5e76b85b4431f4c84ccc4aa9f8508
  1. 3b1040c The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes. by Bill Wendling · 12 years ago
  2. 07418cd No need to store the TargetMachine variable in this class. by Bill Wendling · 12 years ago
  3. d02c8f4 Remove unused #include. by Bill Wendling · 12 years ago
  4. 4e6b24f Rename LoopSimplify.h to LoopUtils.h by Hal Finkel · 12 years ago
  5. b02834c add polly to check-all by Sebastian Pop · 12 years ago
  6. 1aeb13b [mips] Add (setne $lhs, 0) instruction selection pattern. by Akira Hatanaka · 12 years ago
  7. f894199 [mips] Trap on integer division by zero. by Akira Hatanaka · 12 years ago
  8. 08f92c9 Remove copied preheader insertion logic from PPCCTRLoops by Hal Finkel · 12 years ago
  9. fc32605 Expose InsertPreheaderForLoop from LoopSimplify to other passes by Hal Finkel · 12 years ago
  10. 9b39c72 [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX. by Justin Holewinski · 12 years ago
  11. d223675 [NVPTX] Add programmatic interface to NVVMReflect pass by Justin Holewinski · 12 years ago
  12. 85c08b0 Rename PPC MTCTRse to MTCTRloop by Hal Finkel · 12 years ago
  13. e50c8c1 Add a PPCCTRLoops verification pass by Hal Finkel · 12 years ago
  14. d54bf7c R600: Fix bug detected by GCC warning. by Benjamin Kramer · 12 years ago
  15. 4f8d90d R600: Fix rotr.ll on non-asserts builds by Tom Stellard · 12 years ago
  16. 5ad6d08 R600/SI: Use a multiclass for MUBUF_Load_Helper by Tom Stellard · 12 years ago
  17. 307a844 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions by Tom Stellard · 12 years ago
  18. 0bbfc93 R600/SI: Add pattern for rotr by Tom Stellard · 12 years ago
  19. ba534c2 R600: Swap the legality of rotl and rotr by Tom Stellard · 12 years ago
  20. a9d5d0b R600/SI: Add patterns for 64-bit shift operations by Tom Stellard · 12 years ago
  21. fbdd318 R600/SI: Use the same names for VOP3 operands and encoding fields by Tom Stellard · 12 years ago
  22. 9bf4590 R600/SI: Make fitsRegClass() operands const by Tom Stellard · 12 years ago
  23. 30a7a7c VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). by Mihai Popa · 12 years ago
  24. bac932e Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). by Mihai Popa · 12 years ago
  25. 44b486e [SystemZ] Add long branch pass by Richard Sandiford · 12 years ago
  26. e932e89 Enable pod-like optimizations for pred and succ iterators. by Benjamin Kramer · 12 years ago
  27. 7536ecf [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs by Justin Holewinski · 12 years ago
  28. 55fdf53 [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels. by Justin Holewinski · 12 years ago
  29. 083bc97 PR15868 fix. by Stepan Dyatkovskiy · 12 years ago
  30. 3a408fa Disable remote MCJIT on pre-v6 ARM by Renato Golin · 12 years ago
  31. a4de3f2 Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs. by Bob Wilson · 12 years ago
  32. 89f530e Also expand 64-bit bitcasts. by Jakob Stoklund Olesen · 12 years ago
  33. 5e5b78c Implement spill and fill of I64Regs. by Jakob Stoklund Olesen · 12 years ago
  34. 900622e Mark i64 SETCC as expand so it is turned into a SELECT_CC. by Jakob Stoklund Olesen · 12 years ago
  35. 4dc8bdf Replace some bit operations with simpler ones. No functionality change. by Benjamin Kramer · 12 years ago
  36. 634123e Don't use %g0 to materialize 0 directly. by Jakob Stoklund Olesen · 12 years ago
  37. 60abcb7 Select i64 values with %icc conditions. by Jakob Stoklund Olesen · 12 years ago
  38. 2ed2ad0 Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072> by Bob Wilson · 12 years ago
  39. 51d46c3 Add floating point selects on %xcc predicates. by Jakob Stoklund Olesen · 12 years ago
  40. 89db673 Implement SPselectfcc for i64 operands. by Jakob Stoklund Olesen · 12 years ago
  41. 4e4464b SubArch support in MCJIT unittest by Renato Golin · 12 years ago
  42. 21886a4 [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. by Venkatraman Govindaraju · 12 years ago
  43. 233a4d7 AArch64: enable MCJIT unittests by Tim Northover · 12 years ago
  44. 00ce0f6 Handle i64 FrameIndex nodes in SPARC v9 mode. by Jakob Stoklund Olesen · 12 years ago
  45. 675b9e9 AArch64: make RuntimeDyld relocations idempotent by Tim Northover · 12 years ago
  46. 820b147 Invalidate instruction cache when setting memory to be executable. by Tim Northover · 12 years ago
  47. ff9a6b4 Temporarily disable this test because it is failing when using libc++. by Bob Wilson · 12 years ago
  48. ebe7a52 Move the remaining simplify-libcalls tests to instcombine, merging most of them into a single file. by Benjamin Kramer · 12 years ago
  49. a73a614 Print uint64_t -debug text correctly on 32-bit hosts by Tim Northover · 12 years ago
  50. 6d65f33 Unsupported remote JIT on ARM by Renato Golin · 12 years ago
  51. cb9d466 isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also. by David Majnemer · 12 years ago
  52. 688b510 LoopVectorize: Handle single edge PHIs by Arnold Schwaighofer · 12 years ago
  53. edc399a docs/Passes: fix some typos by Dmitri Gribenko · 12 years ago
  54. 769b70e Add basic support for ELF32-ppc relocations to llvm-dwarfdump. by Benjamin Kramer · 12 years ago
  55. bf0bc3b Check InlineAsm clobbers in PPCCTRLoops by Hal Finkel · 12 years ago
  56. 9f61e48 AArch64: add CMake dependency to fix very parallel builds by Tim Northover · 12 years ago
  57. 8a55c2e X86: Bad peephole interaction between adc, MOV32r0 by David Majnemer · 12 years ago
  58. 24623dc Remove duplicated comment by Matt Arsenault · 12 years ago
  59. 225ed70 Add LLVMContext argument to getSetCCResultType by Matt Arsenault · 12 years ago
  60. bab06ba Support unaligned load/store on more ARM targets by JF Bastien · 12 years ago
  61. 637cb17 Fix the configure build. by Rafael Espindola · 12 years ago
  62. 2bbe378 Convert obj2yaml to use yamlio. by Rafael Espindola · 12 years ago
  63. eee6cdd Fix the build in c++11 mode. by Rafael Espindola · 12 years ago
  64. 9aa8fdf Replace redundant code by Matt Arsenault · 12 years ago
  65. 63f3ca5 Add missing -*- C++ -*- to headers by Matt Arsenault · 12 years ago
  66. 115fb70 Add missing verb to comment in PassNameParser.h Patch by Mark Seaborn. by Derek Schuff · 12 years ago
  67. df98ad3 R600: Lower int_load_input to copyFromReg instead of Register node by Vincent Lejeune · 12 years ago
  68. 76fc2d0 R600: Use bottom up scheduling algorithm by Vincent Lejeune · 12 years ago
  69. 21ca0b3 R600: Use depth first scheduling algorithm by Vincent Lejeune · 12 years ago
  70. f63f85a R600: Replace big texture opcode switch in scheduler by usesTC/usesVC by Vincent Lejeune · 12 years ago
  71. 4ed9917 R600: Relax some vector constraints on Dot4. by Vincent Lejeune · 12 years ago
  72. d3293b4 R600: Improve texture handling by Vincent Lejeune · 12 years ago
  73. 4109bd8 R600: Rename 128 bit registers. by Vincent Lejeune · 12 years ago
  74. 25c209e R600: Some factorization by Vincent Lejeune · 12 years ago
  75. dcfcf1d R600: Factorize Fetch size limit inside AMDGPUSubTarget by Vincent Lejeune · 12 years ago
  76. 9a9e936 R600: prettier dump of clamp by Vincent Lejeune · 12 years ago
  77. 0976e3c R600: Fix encoding for R600 family GPUs by Tom Stellard · 12 years ago
  78. 34f533a R600: Pass MCSubtargetInfo reference to R600CodeEmitter by Tom Stellard · 12 years ago
  79. a65d337 [Sparc] Implements hasReservedCallFrame and hasFP. by Venkatraman Govindaraju · 12 years ago
  80. a0de26c X86: Make shuffle -> shift conversion more aggressive about undefs. by Benjamin Kramer · 12 years ago
  81. c032d1a FileCheckize test. by Benjamin Kramer · 12 years ago
  82. c53bee6 LoopVectorize: Simplify code. No functionality change. by Benjamin Kramer · 12 years ago
  83. 91c623d r182085 introduced a change that triggered an assertion on ARM. This is an immediate fix by David Tweed · 12 years ago
  84. 4456a8e by Ulrich Weigand · 12 years ago
  85. e152eac by Ulrich Weigand · 12 years ago
  86. c299ad3 by Ulrich Weigand · 12 years ago
  87. d14743e Fix a typo (ouput => output) by Sylvestre Ledru · 12 years ago
  88. 033f3b7 Don't cast away constness. by Benjamin Kramer · 12 years ago
  89. abb38fe Minor changes to the MCJITTest unittests to use the correct API for finalizing by David Tweed · 12 years ago
  90. e919678 R600/SI: return undef instead of null for skipped arguments by Christian Konig · 12 years ago
  91. d6b4caf [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot. by Venkatraman Govindaraju · 12 years ago
  92. df68803 Generate debug info for by-value struct args even if they are not used. by Adrian Prantl · 12 years ago
  93. 27a33ad llvm-objdump: Initialize MCDisassembler once instead of for each section. by Ahmed Bougacha · 12 years ago
  94. ae7e7cb [mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr). by Akira Hatanaka · 12 years ago
  95. 6b67ffd Remove addFrameMove. by Rafael Espindola · 12 years ago
  96. 529874c More test coverage for addFrameMove. by Rafael Espindola · 12 years ago
  97. 6345143 [mips] Factor out unaligned store lowering code. by Akira Hatanaka · 12 years ago
  98. ae06fa2 Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll by Hal Finkel · 12 years ago
  99. e351865 Mips assembler: Add TwoOperandConstraint definitions by Jack Carter · 12 years ago
  100. d761004 Mips td file formatting: white space and long lines by Jack Carter · 12 years ago