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review.blissroms.org / platform_external_llvm / 43c2ba74fca95ca61abf3717b10a8a3b7369f3b3
  1. 43c2ba7 [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print by Francis Visoiu Mistrih · 8 years ago
  2. 30e8e01 [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print by Francis Visoiu Mistrih · 8 years ago
  3. a6e4a6b [CodeGen] Refactor printOffset from MO and MIRPrinter by Francis Visoiu Mistrih · 8 years ago
  4. 65104c6 [CGP] Format. NFC by Haicheng Wu · 8 years ago
  5. 9e15e21 TargetLoweringBase: Fix darwinHasSinCos() by Matthias Braun · 8 years ago
  6. ca4d818 [dwarfdump][test] Add test case for r321064 by Jonas Devlieghere · 8 years ago
  7. a7ce6d3 [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed. by Mark Searles · 8 years ago
  8. 14eb98a [SeparateConstOffsetFromGEP] Fix a typo. NFC. by Haicheng Wu · 8 years ago
  9. 3070381 [X86] Regenerate popcnt tests by Simon Pilgrim · 8 years ago
  10. ea090c0 [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types. by Amara Emerson · 8 years ago
  11. e63c3fb [DAG] Elide overlapping store by Nirav Dave · 8 years ago
  12. 223840e [X86][AVX512] Attempt target shuffle combining to different types instead of early-out by Simon Pilgrim · 8 years ago
  13. fcfc7b2 [CodeGen] Move printing MO_CFIIndex operands to MachineOperand::print by Francis Visoiu Mistrih · 8 years ago
  14. 0dbbce2 [CFGVPrinter] Fix -dot-cfg-only by Francis Visoiu Mistrih · 8 years ago
  15. 0d49e11 [ThinLTO][C-API] Correct api comments by Ben Dunbobbin · 8 years ago
  16. 5b5d262 [Support][CachePruning] Disable cache pruning regression fix by Ben Dunbobbin · 8 years ago
  17. 0b59f46 [X86] Fix uninitialized variable sanitizer warning from rL321074 by Simon Pilgrim · 8 years ago
  18. 08a0d23 [InlineCost] Skip volatile loads when looking for repeated loads by Haicheng Wu · 8 years ago
  19. 264f0e7 [X86][SSE] Add cpu feature for aggressive combining to variable shuffles by Simon Pilgrim · 8 years ago
  20. 57ebda3 [ARM] Register the Thumb2SizeReducePass. NFC by David Green · 8 years ago
  21. 9524e3f [Support] Add WritableMemoryBuffer class by Pavel Labath · 8 years ago
  22. 7466c9c [X86][SSE] Use (V)PHMINPOSUW for vXi8 SMAX/SMIN/UMAX/UMIN horizontal reductions (PR32841) by Simon Pilgrim · 8 years ago
  23. d7f987b Fix: [YAML] Always double quote UTF-8 characters by Francis Visoiu Mistrih · 8 years ago
  24. 25a46d2 [YAML] Always double quote UTF-8 characters by Francis Visoiu Mistrih · 8 years ago
  25. 664fc77 [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop. by Simon Dardis · 8 years ago
  26. d900f82 [dwarfdump] Lookup needs to be an unsigned long long parameter. by Jonas Devlieghere · 8 years ago
  27. 8cc707a [JumpThreading] Restrict PRE across instructions that don't pass control to successors by Max Kazantsev · 8 years ago
  28. f416f48 [FuzzMutate] Don't crash when mutator is unable to find operation by Igor Laevsky · 8 years ago
  29. 9cf2067 Treat sret arguments as being dereferenceable in getPointerDereferenceableBytes() by Bjorn Steinbrink · 8 years ago
  30. fe2aed6 [X86] Don't extend v16i8 non-uniform shifts to v16i32 if we have BWI. Use v16i16 instead. by Craig Topper · 8 years ago
  31. b920287 [X86] Use a specific list of MVTs in combineShiftRightArithmetic instead of iterating over every integer VT and checking their size. by Craig Topper · 8 years ago
  32. 4cd3501 [X86] Remove unnecessary check for integer VT from combineShiftRightArithmetic. by Craig Topper · 8 years ago
  33. 11d26e6 [X86] Remove dead code for turning vector shifts by large amounts into a zero vector. by Craig Topper · 8 years ago
  34. f401296 [X86] Use ZERO_EXTEND instead of ANY_EXTEND when extending the shift amount for a non-uniform shift. by Craig Topper · 8 years ago
  35. 643edab Fix APFloat from string conversion for Inf by Serguei Katkov · 8 years ago
  36. 4bebdd9 [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before the emission by Quentin Colombet · 8 years ago
  37. e3014ee Fix Wasm as a follow up to r321035 and the other one by Reid Kleckner · 8 years ago
  38. 437b240 update_mir_test_checks: Accept IR as input as well as MIR by Justin Bogner · 8 years ago
  39. e812fcb [llvm-objcopy] Add option to add a progbits section from a file by Jake Ehrlich · 8 years ago
  40. 51a1d9a TargetLoweringBase: Followup to r321035 by Matthias Braun · 8 years ago
  41. ea2d46a TargetLowering: Fix InitLibcallCallingConvs() overriding things set in InitLibcalls() by Matthias Braun · 8 years ago
  42. d53e702 TargetLowering: Fix off-by-one error by Matthias Braun · 8 years ago
  43. 44b9704 [llvm-readobj] Dump wasm init functions by Sam Clegg · 8 years ago
  44. c2b744f TargetLoweringBase: Remove unnecessary watchos exception; NFC by Matthias Braun · 8 years ago
  45. 537c6ee update_mir_test_checks: Add "mir" to some states and regex names by Justin Bogner · 8 years ago
  46. 8f06a7d [X86] Don't use NOPL when the assembler is passed an empty CPU string. by Craig Topper · 8 years ago
  47. 209f048 LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFC by Matthias Braun · 8 years ago
  48. 4f43d6f X86/AArch64/ARM: Factor out common sincos_stret logic; NFCI by Matthias Braun · 8 years ago
  49. 40c1668 AArch64/X86: Factor out common bzero logic; NFC by Matthias Braun · 8 years ago
  50. b01d498 [Hexagon] Cache loads to select to avoid traversing mutating DAG by Krzysztof Parzyszek · 8 years ago
  51. fd4ed12 Revert part of r321026 "[X86] Don't use NOPL when the assembler is passed an empty CPU string." while I investigate how to fix an lld test failure. by Craig Topper · 8 years ago
  52. 456d279 [AArch64] Expand test coverage of vector element shuffling to Exynos by Evandro Menezes · 8 years ago
  53. df42abc [TableGen][GlobalISel] Make the arguments of the Instruction and Operand Matchers consistent by Quentin Colombet · 8 years ago
  54. b43be72 Fix buffer overrun in WindowsResourceCOFFWriter::writeSymbolTable() by Bob Haarman · 8 years ago
  55. f56fea2 Add test for .req directive starting with 'p' by Reid Kleckner · 8 years ago
  56. 2bd867a [MachineOutliner][NFC] Gardening: use std::any_of instead of bool + loop by Jessica Paquette · 8 years ago
  57. a0209c5 [X86] Don't use NOPL when the assembler is passed an empty CPU string. Update tests to force a CPU with NOPL by Craig Topper · 8 years ago
  58. ebf7d45 [TableGen][GlobalISel] Refactor optimizeRules related bit to allow code reuse by Quentin Colombet · 8 years ago
  59. b198292 Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo by Reid Kleckner · 8 years ago
  60. 7c48f0a [Analysis] Generate more precise TBAA tags when one access encloses the other by Ivan A. Kosarev · 8 years ago
  61. 833c475 [PGO] Fix handling of cold entry count for instrumented PGO by Teresa Johnson · 8 years ago
  62. d3fbd02 [TableGen][GlobalISel] Optimize MatchTable for faster instruction selection by Quentin Colombet · 8 years ago
  63. d1fe0c4 Fix more inconsistent line endings. NFC. by Dimitry Andric · 8 years ago
  64. 93e431a [X86] Minor formatting fix to getHostCPUFeatures. NFC by Craig Topper · 8 years ago
  65. d4a00a6 [MachineOutliner] Recommit r320229 by Jessica Paquette · 8 years ago
  66. 7db7ed3 [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation. by Benjamin Kramer · 8 years ago
  67. d33f76c [cmake] Update experimental target error message by Don Hinton · 8 years ago
  68. a6d921e Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header." by Paul Robinson · 8 years ago
  69. 0aa7e5a [PPC] Disable reg+reg to reg+imm transformation. by Benjamin Kramer · 8 years ago
  70. 68e8e68 Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC. by Dimitry Andric · 8 years ago
  71. 65d3bc2 [Hexagon] Higher versions of HVX imply presence of lower versions by Krzysztof Parzyszek · 8 years ago
  72. b10a40f7 [IR] Support the new TBAA metadata format in IR verifier by Ivan A. Kosarev · 8 years ago
  73. 826e27c Fix inconsistent line endings in ARCDisassembler.cpp. NFC. by Dimitry Andric · 8 years ago
  74. 7364392 i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004 by Krzysztof Parzyszek · 8 years ago
  75. 228589c [Hexagon] Generate HVX code for vector sign-, zero- and any-extends by Krzysztof Parzyszek · 8 years ago
  76. cfd421b [X86] Regenerate test to improve codegen testing for D41350 by Simon Pilgrim · 8 years ago
  77. 5966988 [Hexagon] Prefer to widen HVX vectors instead of promoting by Krzysztof Parzyszek · 8 years ago
  78. 1f57e5d Removed unused DominanceFrontier by Matt Arsenault · 8 years ago
  79. 2b18c99 [ThinLTO] Make distributed indexes test more robust by Teresa Johnson · 8 years ago
  80. 03a6f4a [PGO] add MST min edge selection heuristic to ensure non-zero entry count by Xinliang David Li · 8 years ago
  81. 65ad22d [YAML] Add support for non-printable characters by Francis Visoiu Mistrih · 8 years ago
  82. d6be214 [IR] Add MDBuilder helpers for the new TBAA metadata format by Ivan A. Kosarev · 8 years ago
  83. f829832 [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified by Sander de Smalen · 8 years ago
  84. 6b66227 Reland "[mips] Fix the target specific instruction verifier" by Simon Dardis · 8 years ago
  85. b71c6a9 [Memcpy Loop Lowering] Remove the fixed int8 lowering. by Sean Fertile · 8 years ago
  86. a1f6793 [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction by Sander de Smalen · 8 years ago
  87. 7a7c05d [LVI] Support for ashr in LVI by Max Kazantsev · 8 years ago
  88. 1346bcc [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524 by Diana Picus · 8 years ago
  89. afb8875 Constexprify LaneBitmask factory methods. by Benjamin Kramer · 8 years ago
  90. 5cecfe9 [ConstantRange] Support for ashr in ConstantRange computation by Max Kazantsev · 8 years ago
  91. 7a92215 Revert "[mips] Fix the target specific instruction verifier" by Simon Dardis · 8 years ago
  92. bf08176 [mips] Fix the target specific instruction verifier by Simon Dardis · 8 years ago
  93. 9d49216 [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors) by Sander de Smalen · 8 years ago
  94. 29dd081 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support by Sander de Smalen · 8 years ago
  95. 0e72a72 [ThinLTO] Remove unused code by Eugene Leviant · 8 years ago
  96. f66f36e AArch64: work around how Cyclone handles "movi.2d vD, #0". by Tim Northover · 8 years ago
  97. b887495 [TargetLibraryInfo] Discard library functions with incorrectly sized integers by Igor Laevsky · 8 years ago
  98. 2e83f99 [ARM] Adjust test checks by Sam Parker · 8 years ago
  99. 72b2ece [DAGCombine] Move AND nodes to multiple load leaves by Sam Parker · 8 years ago
  100. 805454d [NFC][CodeGen][ExpandMemCmp] Fix documentation. by Clement Courbet · 8 years ago