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review.blissroms.org / platform_external_llvm / 666da1611a87f84c3971323445a6687bee4606fd
  1. 666da16 Whitespace. by Chad Rosier · 13 years ago
  2. 36a273a [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove by Chad Rosier · 13 years ago
  3. 9f2e160 Fix assembling ARM vst2 instructions with double-spaced registers. by Kevin Enderby · 13 years ago
  4. 07cdd80 ARM non-scattered MachO relocations for movw/movt. by Jim Grosbach · 13 years ago
  5. 1fc999e Fix test. by Chad Rosier · 13 years ago
  6. 33e528d [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. by Chad Rosier · 13 years ago
  7. 5c062ad The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. by Silviu Baranga · 13 years ago
  8. 8da7a46 test commit by Silviu Baranga · 13 years ago
  9. db9ca59 Test Commit - add a newline by Richard Barton · 13 years ago
  10. 21e42d0 It's possible to have a constant expression who's size is quite big (e.g., by Bill Wendling · 13 years ago
  11. 89f4e66 Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. by Craig Topper · 13 years ago
  12. a1ffc68 Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. by Craig Topper · 13 years ago
  13. 0c9da21 When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. by Craig Topper · 13 years ago
  14. 8c5293c Do everything up to generating code to try to get a register for by Eric Christopher · 13 years ago
  15. c415af2 Untabify. by Eric Christopher · 13 years ago
  16. 4476bae Add another debugging statement here. by Eric Christopher · 13 years ago
  17. 4e27027 Use lookUpRegForValue here instead of duplicating the code. by Eric Christopher · 13 years ago
  18. 1aa73cc Fix two bugpoint bugs: by Chris Lattner · 13 years ago
  19. e0ac6f8 fix PR12301 - llvm-bcanalyze should print to stdout, not stderr (except for errors). by Chris Lattner · 13 years ago
  20. cfe2998 f16 FDIV can now be legalized by promoting to f32 by Pete Cooper · 13 years ago
  21. e59b0e7 fix a build failure with libc++ by Chris Lattner · 13 years ago
  22. fa1f744 ARM branch relaxation for unconditional t1 branches. by Jim Grosbach · 13 years ago
  23. ceee984 ARM assembly, accept optional '#' on lane index number. by Jim Grosbach · 13 years ago
  24. 1f6e3f9 [Object/COFF]: Expose getSectionContents. by Michael J. Spencer · 13 years ago
  25. b35a896 [Object/COFF]: Expose getSectionName. Also add some documentation. by Michael J. Spencer · 13 years ago
  26. 2d7ea04 Perform mul combine when multiplying wiht negative constants. by Anton Korobeynikov · 13 years ago
  27. 23f1cbb Add an option to the MI scheduler to cut off scheduling after a fixed number of by Lang Hames · 13 years ago
  28. 8c0134a [asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- they are currently used only for experiments by Kostya Serebryany · 13 years ago
  29. 5587a8e llvm/test/DebugInfo: Move two tests to DebugInfo/X86. They are X86-dependent. by NAKAMURA Takumi · 13 years ago
  30. 00294ca Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala. by Duncan Sands · 13 years ago
  31. 3e99b71 This patch adds X86 instruction itineraries for non-pseudo opcodes in by Preston Gurd · 13 years ago
  32. 8118c94 Add a note for -ffast-math optimization of vector norm. by Benjamin Kramer · 13 years ago
  33. a87a75f Make the formatting of this file more consistent, and fix the 80-columns by Chandler Carruth · 13 years ago
  34. 080b862 Teach InstVisitor about the UnaryInstruction layer in the instruction by Chandler Carruth · 13 years ago
  35. f201a06 Factor out the multiply analysis code in ComputeMaskedBits and apply it to the by Nick Lewycky · 13 years ago
  36. 97327dc isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask. by Craig Topper · 13 years ago
  37. 75d05e6 This clause (although matching parts of the implementation) can't be correct. by Nick Lewycky · 13 years ago
  38. cff4ad7 CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector. by Benjamin Kramer · 13 years ago
  39. 79aa341 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. by Craig Topper · 13 years ago
  40. 85f9cef MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty. by Benjamin Kramer · 13 years ago
  41. 70de1e4 Fix some copy and paste remnants of Cell and SPU in Hexagon files. by Craig Topper · 13 years ago
  42. 8aea2dd Fix typo in file header. by Craig Topper · 13 years ago
  43. 1e0c9ab Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class. by Craig Topper · 13 years ago
  44. c1f6f42 Reorder includes to match coding standards. Fix an issue or two exposed by that. by Craig Topper · 13 years ago
  45. ae151ed MC asm parser macro argument count was wrong when empty. by Jim Grosbach · 13 years ago
  46. 5aeff31 Check if we can handle the arguments of a call (and therefore the call) in by Bill Wendling · 13 years ago
  47. 391c145 Revert r152915. Chapuni's WinWaitReleased refactoring: It doesn't work for me by Francois Pichet · 13 years ago
  48. 748c1ec clarify the coding standards a bit. by Chris Lattner · 13 years ago
  49. 11d5dc3 ARM fix silly typo in optional operand alias. by Jim Grosbach · 13 years ago
  50. 66cba30 ARM divided syntax fmrx/fmxr mnemonics. by Jim Grosbach · 13 years ago
  51. be7cf2b ARM ldm/stm register lists can be out of order. by Jim Grosbach · 13 years ago
  52. 0ccae0b Revert r152907. by Bill Wendling · 13 years ago
  53. a82d526 ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs. by Benjamin Kramer · 13 years ago
  54. 861ea23 Limit the number of memory operands in MachineInstr to 2^16 and store the number in padding. by Benjamin Kramer · 13 years ago
  55. 87f3dbc CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the cached value. by Benjamin Kramer · 13 years ago
  56. bb0b6ed lit/TestRunner.py: [Win32] Check all opened_files[] released, rather than (obsoleted) written_files[]. by NAKAMURA Takumi · 13 years ago
  57. 7c6ac2e lit/TestRunner.py: [Win32] Rework WinWaitReleased(). by NAKAMURA Takumi · 13 years ago
  58. ff030fd The alignment of the pointer part of the store instruction may have an by Bill Wendling · 13 years ago
  59. 5a4c790 More const-correcting of FixedLenDecoderEmitter. by Craig Topper · 13 years ago
  60. b2442fc Rip out support for 'llvm.noinline'. This thing has a strange history... by Chandler Carruth · 13 years ago
  61. f91f5af Start removing the use of an ad-hoc 'never inline' set and instead by Chandler Carruth · 13 years ago
  62. eb5cd61 Const-correct the FixedLenDecoderEmitter. Pass a few things by const reference instead of value to avoid some copying. by Craig Topper · 13 years ago
  63. 9b081d9 Pull the implementation of the code metrics out of the inline cost by Chandler Carruth · 13 years ago
  64. d3a7486 misched: add DAG edges from vreg defs to ExitSU. by Andrew Trick · 13 years ago
  65. 75ae203 LSR fix: Add isSimplifiedLoopNest to IVUsers analysis. by Andrew Trick · 13 years ago
  66. d936045 Spacing fixes. Mostly aligning arguments that spilled onto next line with the opening parenthese instead of 2 spaces in. by Craig Topper · 13 years ago
  67. bace5da Revert r152705, which reapplied r152486 as this appears to be causing failures by Chad Rosier · 13 years ago
  68. 797ba55 Remove unused field NumVariable from Filter class. Even it was needed the same result could be found with VariableInstructions.size(). Also fix some typos in comments. by Craig Topper · 13 years ago
  69. e9f15c8 In InstCombiner::visitOr, make sure we reverse the operand swap used for checking for or-of-xor operations after those checks; a later check expects that any constant will be in Op1. PR12234. by Eli Friedman · 13 years ago
  70. 213d2e7 ARM optional operand on MRC/MCR assembly instructions. by Jim Grosbach · 13 years ago
  71. 9426ac7 ARM vmrs system registers mvfr0 and mvfr1 handling. by Jim Grosbach · 13 years ago
  72. 75df9f2 Do the right thing on NULL uint64 fields. by Eric Christopher · 13 years ago
  73. b99ea7c Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." for workaround of g++-4.4's miscompilation. by NAKAMURA Takumi · 13 years ago
  74. 2125d5a For types with a parent of the compile unit make sure and emit by Eric Christopher · 13 years ago
  75. 89eaa6f Remove inadvertant commit. by Jim Grosbach · 13 years ago
  76. 0ac754f [fast-isel] Address Eli's comments for r152847. Specifically, add a test case by Chad Rosier · 13 years ago
  77. 90d9e02 docs: Update TestingGuide to change recommended practice to using LNT to drive by Daniel Dunbar · 13 years ago
  78. 530b19b [fast-isel] Don't try to encode LONG_MIN using cmn instructions. rdar://11038907 by Chad Rosier · 13 years ago
  79. b84ad4a ARM case-insensitive checking for APSR_nzcv. by Jim Grosbach · 13 years ago
  80. ccaea7d We actually handle AllocaInst via getRegForValue below just fine. by Eric Christopher · 13 years ago
  81. bb54d21 Add some debugging output into fast isel as well. by Eric Christopher · 13 years ago
  82. 8f2a88d Add another debug statement. by Eric Christopher · 13 years ago
  83. b82062f Tabs. by Eric Christopher · 13 years ago
  84. 7cc5177 Typo. by Eric Christopher · 13 years ago
  85. 7044cce Make MnemonicTable const again. That part of r152202 was OK. by Jakob Stoklund Olesen · 13 years ago
  86. 6357cae ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. by Jim Grosbach · 13 years ago
  87. dd20af2 Don't assume all mnemonics fit in 64k. by Jakob Stoklund Olesen · 13 years ago
  88. cb18ca2 line endings by Matt Beaumont-Gay · 13 years ago
  89. f72e0ca Type sizes and fields offsets inside structs are unsigned. This is a highly by Duncan Sands · 13 years ago
  90. 45b5f88 Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on by Lang Hames · 13 years ago
  91. bcfa982 Revert r152202: "Use uint16_t to store InstrNameIndices in MCInstrInfo." by Jakob Stoklund Olesen · 13 years ago
  92. d66b9a2 Revert r152105: "Use uint16_t to store indices into string table" by Jakob Stoklund Olesen · 13 years ago
  93. 8a6bcc3 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. by Kristof Beyls · 13 years ago
  94. 33a1805 Fix bug found by warning. by Michael J. Spencer · 13 years ago
  95. 2453dff Short term fix for pr12270 before we change dominates to handle unreachable by Rafael Espindola · 13 years ago
  96. 847d381 Use an iterator instead of calling .size() on the worklist every time, which is wasteful. by Bill Wendling · 14 years ago
  97. d03a29b Implement relocation-overflow behavior for PE/COFF. by Michael J. Spencer · 14 years ago
  98. 6431ff9 When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations. by Nadav Rotem · 14 years ago
  99. 8d101c3 Revert the removal of DW_AT_MIPS_linkage_name when we aren't putting by Eric Christopher · 14 years ago
  100. f963cd3 Follow-up to r152620: restore JIT event listener tests to unittest/ExecutionEngine/JIT by Eli Bendersky · 14 years ago