- 7ebf60f [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma by Dmitry Preobrazhensky · 8 years ago
- 7e1d153 [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579) by Sanjay Patel · 8 years ago
- 2c552fa [MSan] introduce getShadowOriginPtr(). NFC. by Alexander Potapenko · 8 years ago
- 302da6a [X86] Add SAR/SHL/SHR schedule tests by Simon Pilgrim · 8 years ago
- d8ae433 [X86] Add RCL/RCR schedule tests by Simon Pilgrim · 8 years ago
- 5a03908 [Hexagon] Crash in instruction selection for insert_vector_elt for HVX by Krzysztof Parzyszek · 8 years ago
- 6c0ae87 [PowerPC] Sign-extend negative constant stores by Nemanja Ivanovic · 8 years ago
- 3386088 [DAGCombiner] Add combined indexed load to the work list by Nemanja Ivanovic · 8 years ago
- a4f4129 [ARM GlobalISel] Add test for a MOVTi16 pattern. NFC by Diana Picus · 8 years ago
- 504620e [X86] Add fsgsbase schedule tests. by Simon Pilgrim · 8 years ago
- 181a9c9 [RISCV] Add custom CC_RISCV calling convention and improved call support by Alex Bradbury · 8 years ago
- d001eea [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore by Alex Bradbury · 8 years ago
- dcfcbe7 [RISCV] Implement prolog and epilog insertion by Alex Bradbury · 8 years ago
- 1b5e053 [X86] Regenerate fsgsbase intrinsic tests. NFCI. by Simon Pilgrim · 8 years ago
- f815701 [ARM] Use ADDCARRY / SUBCARRY by Roger Ferrer Ibanez · 8 years ago
- 1e4e464 [RISCV] Support lowering FrameIndex by Alex Bradbury · 8 years ago
- 5e9125c [ARM GlobalISel] Add tests for PKHBT and PKHTB by Diana Picus · 8 years ago
- 9d32402 [mips] Removal of microMIPS64R6 by Aleksandar Beserminji · 8 years ago
- 823bc66 [AVR] Implement some missing code paths by Dylan McKay · 8 years ago
- 7135491 [AVR] Fix incorrectly-calculated AVRMCExpr evaluations by Dylan McKay · 8 years ago
- ff09090 [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors. by Craig Topper · 8 years ago
- ec65f94 [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC by Craig Topper · 8 years ago
- f4e6ea2 [X86] Regenerate test with update_llc_test_checks.py by Craig Topper · 8 years ago
- 2f772f1 [X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 while other types are legal. by Craig Topper · 8 years ago
- 4c7cc92 [X86] Add ROL/ROR schedule tests by Simon Pilgrim · 8 years ago
- c9e47b5 [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests by Simon Pilgrim · 8 years ago
- 526fb7c [X86] Add DEC/INC schedule tests by Simon Pilgrim · 8 years ago
- 100df14 [X86] Add INS/OUTS schedule tests by Simon Pilgrim · 8 years ago
- d2cf8e2 [X86] Add CMPS/MOVS/SCAS/STOS schedule tests by Simon Pilgrim · 8 years ago
- 83b413a [X86] Add CMOV schedule tests by Simon Pilgrim · 8 years ago
- 3bbb614 [X86] Add BT/BTC/BTR/BTS schedule tests by Simon Pilgrim · 8 years ago
- 8f64ace [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model by Craig Topper · 8 years ago
- 0355803 [X86] Rename some instructions that start with Int_ to have the _Int at the end. by Craig Topper · 8 years ago
- b6c07b3 [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns by Simon Pilgrim · 8 years ago
- 9b03651 [X86][X87] Add missing x87 scheduler tests by Simon Pilgrim · 8 years ago
- 8ec1b21 [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them. by Craig Topper · 8 years ago
- 00aa30f [X86] Add VCVTQQ2PS to the skylake server scheduler models. by Craig Topper · 8 years ago
- 992aa46 [X86] Add VPMULLWZ256 to the skylake server scheduler model by Craig Topper · 8 years ago
- 75be9e0 [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler model. by Craig Topper · 8 years ago
- 68e4113 [X86] Fix a few instructions that were named Z512 instead of just Z. by Craig Topper · 8 years ago
- 8a79d6a [X86] Add VPSRLWZrr to skylake server scheduler model. by Craig Topper · 8 years ago
- b03920f [X86] Add VPUNPCKLWDZrr to skylake server scheduler model. by Craig Topper · 8 years ago
- 64b3a01 [X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs. by Craig Topper · 8 years ago
- ac349fb [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) call by Sanjay Patel · 8 years ago
- 922e023 [InstCombine] add test for pow(x, -1.0) with FMF; NFC by Sanjay Patel · 8 years ago
- 80f4596 [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601) by Sanjay Patel · 8 years ago
- 8235ce6 [InstCombine] add test for pow(x, 2.0) with FMF; NFC by Sanjay Patel · 8 years ago
- f5f4d81 [X86] Flag BroadWell scheduler model as complete by Simon Pilgrim · 8 years ago
- 1c5c608 Regenerate some AVX2+ scheduling tests that got missed by Simon Pilgrim · 8 years ago
- f314360 Strip trailing whitespace. NFCI. by Simon Pilgrim · 8 years ago
- a6fc11e Regenerate some scheduling tests that got missed by Simon Pilgrim · 8 years ago
- bb43613 [X86] Flag ZNVER1 scheduler model as complete by Simon Pilgrim · 8 years ago
- 6093f14 [X86] Flag SLM scheduler model as complete by Simon Pilgrim · 8 years ago
- d045c39 [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes by Simon Pilgrim · 8 years ago
- f8abf97 [X86] Tag SSE4A instructions as SSE INTALU scheduler classes by Simon Pilgrim · 8 years ago
- 0f9bf70 [X86] Flag BTVER2 scheduler model as complete by Simon Pilgrim · 8 years ago
- d430491 [X86] Tag ADJSTACK instructions as INTALU scheduler class by Simon Pilgrim · 8 years ago
- 6ae5d1f [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts by Dorit Nuzman · 8 years ago
- 9b5897c [X86] Tag MORESTACK instructions as ret scheduler class by Simon Pilgrim · 8 years ago
- 237da2f [X86] Fix duplicate entries in skylake server scheduler model by changing Z128 to Z256 by Craig Topper · 8 years ago
- 0e58de2 [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information by Craig Topper · 8 years ago
- ce74d6a [X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake by Craig Topper · 8 years ago
- 109ab07 [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake by Craig Topper · 8 years ago
- 15efc6e [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. by Craig Topper · 8 years ago
- 73043b6 [X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r' by Craig Topper · 8 years ago
- fb7278b [X86] Add CMPSDrr/rm to the scheduler models. by Craig Topper · 8 years ago
- bbc0301 [Docs] Fix typo in scheduler model documentation. enumemation->enumeration by Craig Topper · 8 years ago
- 43a268a PowerPC: support external pid instructions in MC layer. by Tim Northover · 8 years ago
- 6b57278 [PGO] change arg type to uint64_t to match member field type by Xinliang David Li · 8 years ago
- 6775191 [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics. by Craig Topper · 8 years ago
- 2d75e63 [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int by Craig Topper · 8 years ago
- a39bd6c [X86] Remove ReadAfterLd from several several rb instructions by Craig Topper · 8 years ago
- 400a9b1 [X86] Fix test case I failed ot update in r320279. by Craig Topper · 8 years ago
- 59ec4e4 [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions by Craig Topper · 8 years ago
- 27cda75 [X86] Make the _Int part of some instregex sheduler patterns optional by Craig Topper · 8 years ago
- 1444db5 [X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models. by Craig Topper · 8 years ago
- 5243083 [X86] Tag PIC setup instruction as jump scheduler class by Simon Pilgrim · 8 years ago
- 42bc798 [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes by Simon Pilgrim · 8 years ago
- e3e57e9 [X86] Tag TLS instructions as system scheduler classes by Simon Pilgrim · 8 years ago
- 9117185 [X86] Tag ALLOCA/VAARG instructions as system scheduler classes by Simon Pilgrim · 8 years ago
- 14ef303 [AArch64] Improve loop unrolling performance on Cavium T99 by Joel Jones · 8 years ago
- e3aae88 [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515) by Simon Pilgrim · 8 years ago
- 1134b2a Infer lowest bits of an integer Multiply when the low bits of the operands are known by Simon Dardis · 8 years ago
- 84e367e [X86] Use KMOV instructions to zero upper bits of vectors when possible. by Craig Topper · 8 years ago
- 03b324a [X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits. by Craig Topper · 8 years ago
- 386a961 [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes by Simon Pilgrim · 8 years ago
- ff701cc Strip trailing whitespace. NFCI. by Simon Pilgrim · 8 years ago
- d062140 [X86] Tag FS/GS BASE R/W instruction scheduler classes by Simon Pilgrim · 8 years ago
- 68b3779 [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classes by Simon Pilgrim · 8 years ago
- 20f66c3 [X86] Tag missing EH pseudo instruction scheduler classes by Simon Pilgrim · 8 years ago
- 0282531 [X86] Tag frame pointer XORs instruction scheduler classes by Simon Pilgrim · 8 years ago
- a9a921c [X86] Don't use getTargetConstant for all 0s and all 1s mask vector. by Craig Topper · 8 years ago
- 012e6e5 Remove duplicate option from documentation. by Adrian Prantl · 8 years ago
- e0380a5 [X86] Tag segment prefixes as NOP instruction scheduling classes by Simon Pilgrim · 8 years ago
- 89d33c5 [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. NFCI. by Simon Pilgrim · 8 years ago
- 0fb0fea Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. NFCI. by Simon Pilgrim · 8 years ago
- 0b6ce32 Fix signed/unsigned gcc warning. NFCI. by Simon Pilgrim · 8 years ago
- b45da9e [InlineFunction] Set debug loc for call to forward varargs. by Florian Hahn · 8 years ago
- c005469 [X86] When inserting into the upper bits of a vXi1 vector, make sure we shift enough bits if we widened the vector. by Craig Topper · 8 years ago
- 4f04548 Revert and accidentally committed revert commit by Dylan McKay · 8 years ago