- 7f0125b For Mips16, start to consolidate all forms of 32 bit literal loading so that by Reed Kotler · 12 years ago
- e3ba15c Add missing #include's to cctype when using isdigit/alpha/etc. by Will Dietz · 12 years ago
- 87b110a Debug Info: remove form from function addDIEEntry. by Manman Ren · 12 years ago
- 4bad07f Fixing problems in lli's RemoteMemoryManager. by Andrew Kaylor · 12 years ago
- 528f6d7 Adding multiple object support to MCJIT EH frame handling by Andrew Kaylor · 12 years ago
- b19b474 R600: Add scalar i32 add test by Matt Arsenault · 12 years ago
- 2ad612a Use CHECK-LABEL by Matt Arsenault · 12 years ago
- e1bd218 Fix typo by Matt Arsenault · 12 years ago
- 4c5956c fConversion: Attempt #2 at fixing the MSVC build. by Benjamin Kramer · 12 years ago
- ae6fa27 IfConversion: Try to unbreak the MSVC build. by Benjamin Kramer · 12 years ago
- 5af763c Mips: Disassemble sign-extended 64 bit immediates properly. by Benjamin Kramer · 12 years ago
- 8573384 Remove kill flags after if conversion if necessary by Matthias Braun · 12 years ago
- da74817 Introduce ad hoc liveness tracking utility: LiveRegUnits by Matthias Braun · 12 years ago
- 8c15b60 [DAGCombiner] Load slicing test case: attempt to really fix the buildbots (used sse4.2 instead of avx!). by Quentin Colombet · 12 years ago
- f02062f Add warning about CHECK-DAG with variable definition by Renato Golin · 12 years ago
- 47cbe03 Debug Info Testing Case: check for the name of a structure. by Manman Ren · 12 years ago
- e5f740c Really fix CHECK-LABEL and CHECK-DAG interaction. This actually just restores the initial implementation that was in r186162 but got lost in some subsequent refactoring. More explicit variable names and comments are present now to hopefully prevent repeat regression, as well as another test. by Stephen Lin · 12 years ago
- 83f743a [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support. by Quentin Colombet · 12 years ago
- 4351741 [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails on ubuntu. by Quentin Colombet · 12 years ago
- 1dfe206 Revert "Tests: Be less dependent on a specific schedule/regalloc" by Matthias Braun · 12 years ago
- c34693f [DAGCombiner] Slice a big load in two loads when the element are next to each by Quentin Colombet · 12 years ago
- 563c182 Fix handling of CHECK-DAG inside of CHECK-LABEL. by Rafael Espindola · 12 years ago
- de2aa60 Better info when debugging vectorizer by Renato Golin · 12 years ago
- fc3dc10 [ARM] Fix FP ABI attributes with no VFP enabled. by Amara Emerson · 12 years ago
- d2f8df5 fix typo in comment by Matthias Braun · 12 years ago
- 5b51fd5 Tests: Be less dependent on a specific schedule/regalloc by Matthias Braun · 12 years ago
- 21d60f0 This reverts 192447 because of compiler warning generated on darwin build. by Matheus Almeida · 12 years ago
- abba716 This reverts r192449 because of compiler warning generated on darwin build. by Matheus Almeida · 12 years ago
- 62a69ee [mips][msa] Direct Object Emission for the majority of the ELM instructions. by Matheus Almeida · 12 years ago
- 6f36ea5 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. by Matheus Almeida · 12 years ago
- 71e7893 [mips][msa] Improves robustness of the test by enhancing pattern matching. by Matheus Almeida · 12 years ago
- 81d9902 [NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc by Justin Holewinski · 12 years ago
- 43777c3 Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs by Justin Holewinski · 12 years ago
- 4fc2774 [ARM] Add a test case for disabled neon/fpu features. by Amara Emerson · 12 years ago
- a6e253d [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) by Daniel Sanders · 12 years ago
- 4fa2c32 [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) by Daniel Sanders · 12 years ago
- ed0ed94 XCore target fix bug in emitArrayBound() causing segmentation fault by Robert Lytton · 12 years ago
- 4315b2b XCore target does not emit '.hidden' or '.protected' attributes by Robert Lytton · 12 years ago
- fb312f9 XCore target: fix bug in XCoreLowerThreadLocal.cpp by Robert Lytton · 12 years ago
- 7b53766 XCore target: add XCoreTargetLowering::isZExtFree() by Robert Lytton · 12 years ago
- c879eab [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) by Daniel Sanders · 12 years ago
- b9bee10 [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) by Daniel Sanders · 12 years ago
- e799dbc Remove another unnecessary filter from the disassembler. by Craig Topper · 12 years ago
- 3b9c5eb LiveRangeCalc.h: Update a description corresponding to r192396. [-Wdocumentation] by NAKAMURA Takumi · 12 years ago
- 767f816 Implement aarch64 neon instruction set AdvSIMD (copy). by Kevin Qin · 12 years ago
- 6c066c0 Fix typo by Matt Arsenault · 12 years ago
- b803d6b Tests: Do not unnecessarily depend on kill comments by Matthias Braun · 12 years ago
- 82eb619 Tests: Use CHECK-LABEL where possible by Matthias Braun · 12 years ago
- 03d9609 Print register in LiveInterval::print() by Matthias Braun · 12 years ago
- 4f3b5e8 Represent RegUnit liveness with LiveRange instance by Matthias Braun · 12 years ago
- e25dde5 Work on LiveRange instead of LiveInterval where possible by Matthias Braun · 12 years ago
- a4aed9a Change MachineVerifier to work on LiveRange + LiveInterval by Matthias Braun · 12 years ago
- 5649e25 Pass LiveQueryResult by value by Matthias Braun · 12 years ago
- 87a8605 Refactor LiveInterval: introduce new LiveRange class by Matthias Braun · 12 years ago
- 331de11 Rename LiveRange to LiveInterval::Segment by Matthias Braun · 12 years ago
- 4afb5f5 Rename parameter: defined regs are not incoming. by Matthias Braun · 12 years ago
- 4d91232 test commit by Sriram Murali · 12 years ago
- 828c9e7 Use getPointerSizeInBits() rather than 8 * getPointerSize() by Matt Arsenault · 12 years ago
- 89dedc1 Fix grammar / missing words by Matt Arsenault · 12 years ago
- b8e48a6 Debug Info: In DIBuilder, the context field of subprogram is updated to use by Manman Ren · 12 years ago
- 75a3ad4 Add comments to debug info testing case. by Manman Ren · 12 years ago
- 1cc41bf R600: Fix trunc i64 to i32 on SI by Matt Arsenault · 12 years ago
- a7d9a5d Provide msbuild integration for vs2013. by Hans Wennborg · 12 years ago
- 6a24c7d Fix msbuild integration install script. by Hans Wennborg · 12 years ago
- 47fbbc2 R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP* by Tom Stellard · 12 years ago
- 3986785 R600/SI: Use -verify-machineinstrs for most tests by Tom Stellard · 12 years ago
- 0f9eaaa R600/SI: Define a separate MIMG instruction for each possible output value type by Tom Stellard · 12 years ago
- 219e788 R600/SI: Mark the EXEC register as reserved by Tom Stellard · 12 years ago
- de28bda R600: Use StructurizeCFGPass for non SI targets by Tom Stellard · 12 years ago
- 6a5a667 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). by Hao Liu · 12 years ago
- 812ddcc Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." by Rafael Espindola · 12 years ago
- d622bef Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). by Hao Liu · 12 years ago
- 8ccf2b3 ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline. by Benjamin Kramer · 12 years ago
- 58e3e10 Disable function padding to get this test to pass on atom. by Benjamin Kramer · 12 years ago
- acd79ce ARM: correct liveness flags during ARMLoadStoreOpt by Tim Northover · 12 years ago
- 15de63c Allow non-AVX form of pmovmskb to take a GR64 operand. by Craig Topper · 12 years ago
- 369cc50 Remove duplicate instructions. by Craig Topper · 12 years ago
- be5c1fd Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. by Craig Topper · 12 years ago
- 25dafa3 [mips] Do not generate INS/EXT nodes if target does not have support for by Akira Hatanaka · 12 years ago
- 6bba6bb Revert "llvm-c: Make target initializer functions external functions in lib." by Rui Ueyama · 12 years ago
- b4d9c11 Debug Info: In DIBuilder, the context and type fields of template_type and by Manman Ren · 12 years ago
- 9360e64 llvm-c: Make target initializer functions external functions in lib. by Anders Waldenborg · 12 years ago
- 5e5d494 Debug Info: In DIBuilder, the context field of a forward decl is updated by Manman Ren · 12 years ago
- bf15f19 Add missing releases. by Bill Wendling · 12 years ago
- 3353c59 Flip the ownership of MCStreamer and MCTargetStreamer. by Benjamin Kramer · 12 years ago
- e040909 Fix a bug in Dead Argument Elimination. by Shuxin Yang · 12 years ago
- 1a525e8 Add a GlobalAlias::isValidLinkage to reduce code duplication. by Rafael Espindola · 12 years ago
- 3b73dea [Sparc] Disable tail call optimization for sparc64. by Venkatraman Govindaraju · 12 years ago
- 0568ba6 Test commit. Remove whitespace from otherwise empty lines. by Greg Bedwell · 12 years ago
- 50dc2ad AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. by Elena Demikhovsky · 12 years ago
- d29bae8 AArch64: enable MISched by default. by Tim Northover · 12 years ago
- ccb06ae AArch64: migrate ADRP relaxation test to be llvm-mc only. by Tim Northover · 12 years ago
- 5747f94 More x86 disassembler filtering cleanup. by Craig Topper · 12 years ago
- 036c6e8 Add missing HasAVX512 predicate. by Andrew Trick · 12 years ago
- 10c7925 Remove some old filters from the x86 disassembler table builder. by Craig Topper · 12 years ago
- 0c73c42 Replace a couple instructions with patterns referring to other instructions with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler. by Craig Topper · 12 years ago
- 28ffa8a Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v' by Craig Topper · 12 years ago
- 442b23a Mark some instructions as CodeGenOnly since they aren't needed by the assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables. by Craig Topper · 12 years ago
- b96a393 Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. by Craig Topper · 12 years ago
- c52566d Add a paragraph about MCTargetStreamer. by Rafael Espindola · 12 years ago