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review.blissroms.org / platform_external_llvm / 92d40b0a3d46461e3e34283d988f27274c3b8beb
  1. 92d40b0 [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs by Simon Pilgrim · 7 years ago
  2. b22cddf [Pipeliner] Check for affine expression in isLoopCarriedOrder by Krzysztof Parzyszek · 7 years ago
  3. 42e9b96 Remove an unneeded (& mislayered) include from Target/TargetLoweringObjectFile on a CodeGen header by David Blaikie · 7 years ago
  4. fecaf52 Remove unneeded (& mislayered) include from TargetMachine.cpp on a CodeGen header by David Blaikie · 7 years ago
  5. b709662 [Pipeliner] Add missing loop carried dependences by Krzysztof Parzyszek · 7 years ago
  6. b9e7253 [SLP] Add a test case. NFC. by Haicheng Wu · 7 years ago
  7. 276ad3c [Pipeliner] Fix renaming in pipeliner when eliminating phis by Krzysztof Parzyszek · 7 years ago
  8. 2d4c98f [Pipeliner] Fix number of phis to generate in the epilog by Krzysztof Parzyszek · 7 years ago
  9. 5f51cb0 [Pipeliner] Use latency to compute RecMII by Krzysztof Parzyszek · 7 years ago
  10. b483db2 [X86][Btver2] Add CVTSD2SS/CVTSS2SD scheduler costs by Simon Pilgrim · 7 years ago
  11. 6023f6c [Pipeliner] Fix assert caused by pipeliner serialization by Krzysztof Parzyszek · 7 years ago
  12. 0c137c5 [InstCombine] reassociate loop invariant GEP chains to enable LICM by Sebastian Pop · 7 years ago
  13. 42f8f94 [Pipeliner] Enable more base+offset dependence changes in pipeliner by Krzysztof Parzyszek · 7 years ago
  14. 1e6d98e [Pipeliner] Fix calculation when reusing phis by Krzysztof Parzyszek · 7 years ago
  15. f0568a8 [X86][Btver2] Account for the "+i" integer pipe transfer costs (1cy use of JALU0 for GPR PRF write) by Simon Pilgrim · 7 years ago
  16. 2fc30a3 [Pipeliner] Fix check for order dependences when finalizing instructions by Krzysztof Parzyszek · 7 years ago
  17. d5ceb00 [Pipeliner] Fix in the pipeliner phi reuse code by Krzysztof Parzyszek · 7 years ago
  18. a13b439 [Pipeliner] Pipeliner should mark physical registers as used by Krzysztof Parzyszek · 7 years ago
  19. b2c8940 [Pipeliner] Correctly update memoperands in the epilog by Krzysztof Parzyszek · 7 years ago
  20. a76b756 [demangler] Fix a bug in r328464 found by oss-fuzz. by Erik Pilkington · 7 years ago
  21. eb1ea2f [Hexagon] Give priority to post-incremementing memory accesses in LSR by Krzysztof Parzyszek · 7 years ago
  22. c6c033f [X86][Btver2] Add CVTSD2SI/CVTSS2SI scheduler costs by Simon Pilgrim · 7 years ago
  23. 474404b Migrate dockerfiles to use multi-stage builds. by Ilya Biryukov · 7 years ago
  24. 3e5c120 [InstCombine] distribute fmul over fadd/fsub by Sanjay Patel · 7 years ago
  25. da4fb16 [X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP instructions costs by Simon Pilgrim · 7 years ago
  26. 7fa3ae5 [llvm-mca] Fix how views are added to the InstructionTables. by Andrea Di Biagio · 7 years ago
  27. 4432622 [InstCombine] check uses before creating instructions for fmul distribution by Sanjay Patel · 7 years ago
  28. 74c171f [X86][Btver2] Add (V)SQRTPD/(V)SQRTSD costs by Simon Pilgrim · 7 years ago
  29. 6e532c9 AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes by Nicolai Haehnle · 7 years ago
  30. fafdf4a [llvm-mca] Add a flag -instruction-info to enable/disable the instruction info view. by Andrea Di Biagio · 7 years ago
  31. 33dfb9d [llvm-mca] Update the commandline docs after r328305. by Andrea Di Biagio · 7 years ago
  32. d1449c9 [X86][Btver2] Double the AGU and schedule pipe resources for YMM by Simon Pilgrim · 7 years ago
  33. 48972e6 [LSR] Allow giving priority to post-incrementing addressing modes by Krzysztof Parzyszek · 7 years ago
  34. 181ce9f [llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874) by Andrea Di Biagio · 7 years ago
  35. df730ad Test commit - adding a new line. by Carlos Alberto Enciso · 7 years ago
  36. edec8af [LoopUnroll] Fix dangling pointers in SCEV by Max Kazantsev · 7 years ago
  37. 7b0d030 Revert r328386 "[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32" by Hans Wennborg · 7 years ago
  38. 120cf63 [DeadArgElim] Strip allocsize attributes when deleting an argument. by Benjamin Kramer · 7 years ago
  39. 7144163 [IRCE] Enable increasing loops of variable bounds by Sam Parker · 7 years ago
  40. 2c3af0c [ARM] Simplify constructing the ARMArchFeature string. NFC. by Martin Storsjo · 7 years ago
  41. 640ccb5 [X86] Fix the SchedRW for intrinsic register form of SQRT/RCP/RSQRT. by Craig Topper · 7 years ago
  42. 0738cbc [X86] Merge the SSE and AVX versions of fp divs and sqrts in the SandyBridge/Haswell/Broadwell/Skylake scheduler models. by Craig Topper · 7 years ago
  43. a514d32 [X86] Add itinerary to intrinsic version of sqrtss, rcpss, and rsqrtss instructions. by Craig Topper · 7 years ago
  44. c2d0f67 [X86] Correct the itineraries for the dot production instructions. by Craig Topper · 7 years ago
  45. 1f70ff8 [X86] Use the same itinerary for VCVTDQ2PD as the SSE version so that the generated scheduler classes will merge. by Craig Topper · 7 years ago
  46. 8816046 [X86] Swap the itineraries on the memory and register forms of CVTDQ2PD. by Craig Topper · 7 years ago
  47. 1214440 [X86] Give VMOVSX/ZX the same itinerary as the SSE version so they'll reuse the same generated scheduler class. by Craig Topper · 7 years ago
  48. 629da0d [X86] Give vpmsadbw the same itinerary as the SSE version so they'll be able to share the same generated scheduler class. by Craig Topper · 7 years ago
  49. f415690 [X86] Move (v)movss to port 5 only for Skylake. Move (v)movups/d to port 015 for Skylake. by Craig Topper · 7 years ago
  50. 21f2826 [demangler] Use a back-patching scheme to resolve forward references. by Erik Pilkington · 7 years ago
  51. 4990859 [demangler] Tweak how parameter pack sizes are determined. by Erik Pilkington · 7 years ago
  52. e7042cf [demangler] Support for clang's enable_if attribute. by Erik Pilkington · 7 years ago
  53. 1017678 [PatternMatch] allow undef elements when matching vector FP +0.0 by Sanjay Patel · 7 years ago
  54. 636b39a [X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI. by Simon Pilgrim · 7 years ago
  55. fb87505 [SchedModel] Remove instregex entries that don't match any instructions by Simon Pilgrim · 7 years ago
  56. 9c2d3ad [X86][SkylakeClient] Fix missing comma by Simon Pilgrim · 7 years ago
  57. cfec5dc [ARM] Remove sched model instregex entries that don't match any instructions (D44687) by Simon Pilgrim · 7 years ago
  58. 0989cb2 [X86] Add missing full stop to comment. NFCI. by Simon Pilgrim · 7 years ago
  59. 1241873 [InstSimplify, InstCombine] add/update tests with FP +0.0 vector with undef; NFC by Sanjay Patel · 7 years ago
  60. d40afef [X86][SkylakeClient] Fix a set of regular expressions that were checking for optionally starting with 'Y' instead of 'V' by Craig Topper · 7 years ago
  61. feb3905 [X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVecMove than WriteMove by Simon Pilgrim · 7 years ago
  62. 96cdb99 [X86][SkylakeServer] Merge multiple instregex. NFCI by Simon Pilgrim · 7 years ago
  63. e192eb0 [X86] Update cost model for Goldmont. Add fsqrt costs for Silvermont by Craig Topper · 7 years ago
  64. 9c0bd4b [InstCombine] adjust test comments; NFC by Sanjay Patel · 7 years ago
  65. eb6f6af [InstCombine] consolidate casted icmp vector tests by Sanjay Patel · 7 years ago
  66. aef1b11 [InstCombine] peek through more icmp of FP cast + bitcast by Sanjay Patel · 7 years ago
  67. 7a1a91f [X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds for Intel models by Simon Pilgrim · 7 years ago
  68. 04dad85 [X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'. by Craig Topper · 7 years ago
  69. 6c053b7 [X86] Update a partially stale comment, since SVN r328386. NFC. by Martin Storsjo · 7 years ago
  70. 419fa24 [SchedModel] Remove an unneeded temporary vector. by Craig Topper · 7 years ago
  71. 284e1ff [SchedModel] Use std::move in a couple places to reduce copying by Craig Topper · 7 years ago
  72. af807a6 [SchedModel] Use std::move to replace a vector instead of vector::swap by Craig Topper · 7 years ago
  73. a078148 Fix module.modulemap after r328395 by Eric Fiselier · 7 years ago
  74. 9201665 [SchedModel] Remove std::vectors that were created with 1 element and then passed to an ArrayRef parameter. by Craig Topper · 7 years ago
  75. ded7cc4 [SchedModel] Record::getName() returns StringRef - avoid std::string creation. NFCI. by Simon Pilgrim · 7 years ago
  76. 79483b2 [SchedModel] Avoid std::string creation for instregex patterns that don't contain regex metas. NFCI. by Simon Pilgrim · 7 years ago
  77. 9a7f9fe [X86][SkylakeClient] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time by Simon Pilgrim · 7 years ago
  78. c6d3a5e [X86][Broadwell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time by Simon Pilgrim · 7 years ago
  79. df93152 [RISCV] Use init_array instead of ctors for RISCV target, by default by Mandeep Singh Grang · 7 years ago
  80. 329aaa6 [X86][Haswell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time by Simon Pilgrim · 7 years ago
  81. 43a7507 [X86][SandyBridge] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time by Simon Pilgrim · 7 years ago
  82. 7780649 [Hexagon] Change std::sort to llvm::sort in response to r327219 by Mandeep Singh Grang · 7 years ago
  83. a71df88 [AMDGPU] Change std::sort to llvm::sort in response to r327219 by Mandeep Singh Grang · 7 years ago
  84. add7b3e [llvm-mca] run clang-format on all files. by Andrea Di Biagio · 7 years ago
  85. 7525290 [llvm-mca] Remove unused field in InstrBuilder. NFC by Andrea Di Biagio · 7 years ago
  86. 51bf112 [InstCombine] peek through FP casts for sign-bit compares (PR36682) by Sanjay Patel · 7 years ago
  87. 97758c9 [InstCombine] fix formatting; NFC by Sanjay Patel · 7 years ago
  88. b747538 [X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets by Simon Pilgrim · 7 years ago
  89. b5d6a0f [X86][SSE] Ensure we're testing both non-VEX/VEX variants of SSE instructions on AVX targets by Simon Pilgrim · 7 years ago
  90. 9055038 [InstCombine] add multi-use/vector tests for intrinsic shrinking; NFC by Sanjay Patel · 7 years ago
  91. 02ccc54 [X86][AVX1] Ensure we don't use later instruction sets in AVX1 schedule tests by Simon Pilgrim · 7 years ago
  92. f5891a0 [X86][AVX2] Ensure we don't use later instruction sets in AVX2 schedule tests by Simon Pilgrim · 7 years ago
  93. 7cff411 [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute. by Craig Topper · 7 years ago
  94. 2280dbe [X86] Use unique_ptr to simplify memory management. NFC by Craig Topper · 7 years ago
  95. ce08cb3 [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF format encodings. NFC by Craig Topper · 7 years ago
  96. 4f709f6 [X86] Remove an unnecessary switch around two other switches. NFC by Craig Topper · 7 years ago
  97. f0c0da8 [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFC by Craig Topper · 7 years ago
  98. 0a0437f Add REQUIRES lines for the targets being checked in this test. by Eric Christopher · 7 years ago
  99. b97c8e6 [X86] Add a DAG combine to simplify PMULDQ/PMULUDQ nodes by Craig Topper · 7 years ago
  100. 3997401 Allow FDE references outside the +/-2GB range supported by PC relative by Eric Christopher · 7 years ago