commit | 42a025965e830f80f5148fa620750404ed71c266 | [log] [tgz] |
---|---|---|
author | Alex Bradbury <asb@lowrisc.org> | Thu Dec 07 10:46:23 2017 +0000 |
committer | Alex Bradbury <asb@lowrisc.org> | Thu Dec 07 10:46:23 2017 +0000 |
tree | caea75662ee3bdf674240ecb0d207c53c9385952 | |
parent | fd11bc081304b8ca3bf7a657eb45af7a6a24246f [diff] |
[RISCV] MC layer support for the standard RV32D instruction set extension As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023 91177308-0d34-0410-b5e6-96231b3b80d8