[RISCV] MC layer support for the standard RV32D instruction set extension

As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023 91177308-0d34-0410-b5e6-96231b3b80d8
10 files changed