[X86][BtVer2] Add support for all vector instructions that should match the dependency-breaking 'zero-idiom'

As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334119 91177308-0d34-0410-b5e6-96231b3b80d8
2 files changed