| commit | 020f4106f820648fd7e91956859844a80de13974 | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Wed Dec 14 20:00:08 2011 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Wed Dec 14 20:00:08 2011 +0000 |
| tree | cdf6a36ab7bed9a0c468813406c2d3403997e886 | |
| parent | e90ac9bce9aa6de288568df9bf6133c08534ae2f [diff] |
Model ARM predicated write as read-mod-write. e.g. r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8