| commit | fc2b3d0ed07d0e4900402f3b07bff350eb3a2a36 | [log] [tgz] |
|---|---|---|
| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | Fri Jul 06 08:03:12 2018 +0000 |
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | Fri Jul 06 08:03:12 2018 +0000 |
| tree | 2a802b5557baf586a04aee773af003af988f249f | |
| parent | a4e191b323716c2dc5aff48e3269b78f365927c4 [diff] |
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336418 91177308-0d34-0410-b5e6-96231b3b80d8