| commit | 0100c808ce5e513ee746be0742191765f1ddc7dd | [log] [tgz] |
|---|---|---|
| author | Adam Nemet <anemet@apple.com> | Thu Apr 13 23:32:47 2017 +0000 |
| committer | Adam Nemet <anemet@apple.com> | Thu Apr 13 23:32:47 2017 +0000 |
| tree | 366e4ebc1c2d70b9ea3280daeefb6b7749ab3772 | |
| parent | 2b1bb6d8f89a8770933b18b8417500222e40db46 [diff] |
[AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16 This further improves Ahmed's change in rL299482. See the new comment for the rationale. The patch recovers most of the regression for bzip2 after D31965. We're down to +2.68% from +6.97%. Differential Revision: https://reviews.llvm.org/D32028 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300276 91177308-0d34-0410-b5e6-96231b3b80d8