[RISC-V] Fixed alias for addi x2, x2, 0

A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339381 91177308-0d34-0410-b5e6-96231b3b80d8
2 files changed