| commit | 68cefd37e8e51ca5c2f04df5a2e1c25ed12e6db9 | [log] [tgz] |
|---|---|---|
| author | Craig Topper <craig.topper@intel.com> | Thu Jul 12 00:54:40 2018 +0000 |
| committer | Craig Topper <craig.topper@intel.com> | Thu Jul 12 00:54:40 2018 +0000 |
| tree | 85feedd17217c97c7058cd41a47db172be31301b | |
| parent | 6c31f1e00d9d92d731fdebdb107fc2badb6d4585 [diff] |
[X86] Add patterns to use VMOVSS/SD zero masking for scalar f32/f64 select with zero. These showed up in some of the upgraded FMA code. We really need to improve these test cases more, but this helps for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336875 91177308-0d34-0410-b5e6-96231b3b80d8